US010050904B2
`
`a2) United States Patent
`US 10,050,904 B2
`(0) Patent No.:
`*Aug. 14, 2018
`(45) Date of Patent:
`Konda
`
`(54)
`
`VLSI LAYOUTS OF FULLY CONNECTED
`GENERALIZED AND PYRAMID NETWORKS
`WITH LOCALITY EXPLOITATION
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`(71)
`
`Applicant: Venkat Konda, San Jose, CA (US)
`
`(72)
`
`Inventor: Venkat Konda, San Jose, CA (US)
`
`(73)
`
`Assignee: Konda Technologies Inc., San Jose,
`CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 10 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`(21)
`
`Appl. No.: 15/351,453
`
`(22)
`
`Filed:
`
`Nov. 15, 2016
`
`(65)
`
`Prior Publication Data
`
`US 2017/0070449 Al
`
`Mar. 9, 2017
`
`Related U.S. Application Data
`
`(63)
`
`Continuation of application No. 14/522,599, filed on
`Oct. 24, 2014, now Pat. No. 9,529,958, which is a
`(Continued)
`
`(51)
`
`Int. Cl.
`
`(52)
`
`(58)
`
`GO6F 17/50
`HOAL 12/933
`HOAL 12/50
`USS. Cl.
`
`(2006.01)
`(2013.01)
`(2006.01)
`
`CPC ...... HO4L 49/1507 (2013.01); GO6F 17/5054
`(2013.01); GO6F 17/5077 (2013.01); HO4L
`12/50 (2013.01); HO4L 49/10 (2013.01)
`Field of Classification Search
`CPC wo. GO6T 15/005; GO6T 1/20; GO6T 1/60;
`GO6T 5/002; GO6F 17/5054; GO6F 3/017;
`(Continued)
`
`5,153,843 A
`5,451,936 A
`
`10/1992 Batcher
`9/1995 Yangetal.
`(Continued)
`
`OTHER PUBLICATIONS
`
`Guy Lemieux et.al., Generating highlyroutablesparse crossbars for
`PLDs. In ACMISIGDAInt’l. Symposium on Field Programmable
`Gate Arrays, pp. 155-164, Monterey, CA, Feb. 2000.
`(Continued)
`
`Primary Examiner — Binh Tat
`
`ABSTRACT
`(57)
`VLSI layouts of generalized multi-stage and pyramid net-
`works for broadcast, unicast and multicast connections are
`presented using only horizontal and vertical
`links with
`spacial
`locality exploitation. The VLSI
`layouts employ
`shuffle exchange links where outlet links of cross links from
`switches in a stage in one sub-integrated circuit block are
`connected to inlet links of switches in the succeeding stage
`in another sub-integrated circuit block so that said cross
`links are either vertical links or horizontal and vice versa.
`Furthermore the shuffle exchange links are employed
`between different sub-integrated circuit blocks so that spa-
`cially nearer sub-integrated circuit blocks are connected
`with shorter links compared to the shuffle exchange links
`between spacially farther sub-integrated circuit blocks. In
`one embodiment
`the sub-integrated circuit blocks are
`arranged in a hypercube arrangement in a two-dimensional
`plane. The VLSI layouts exploit the benefits of significantly
`lower cross points, lower signal latency, lower power and
`full connectivity with significantly fast compilation.
`The VLSI layouts with spacial locality exploitation pre-
`sented are applicable to generalized multi-stage and pyramid
`networks, generalized folded multi-stage and pyramid net-
`works, generalized butterfly fat tree and pyramid networks,
`generalized multi-link multi-stage and pyramid networks,
`generalized folded multi-link multi-stage and pyramid net-
`works, generalized multi-link butterfly fat tree and pyramid
`(Continued)
`
` From the output switch of each destination, recursively derive thethe list of|§
`
`
`
`
`
`|~
`
`- 910
`Recieve requestto form a connection from aninlet link of an input switch
`
`From each outgoing middle link of the input switch, recursively derive the
`lists of reachable middle switches in each middle stage, traveling forward
`from middle stage 1 to middle stage Log N
`Mark all the middle
`links betweenall
`the stages used to
`middle switches, from which the destination is reachable,in each middle
`set up the
`stage,traveling backwards from output stage to middle stage Log N
`connection, so that |
`they are
`unavailable for
`other connections
`Usingthe lists generated in the previous two steps, by matching up tha corresponding
`available middle switchesin the middle stage LogN, generatethelists of reachable
`
`
`destinationsstarting from each outgoing middle link of the input switch
`970
`¢
`input switch through which all destination: 950
`a Single outgoing middie Tink
`tro
`‘Set up the connection through|YES
`1s are
`‘one outgoing middle link trom
`
`
`
`reachable?
`the input awiteh
`960
`
`Set up the connection through
`Find two outgaing middle links from the
`|,”
`two outgoing middle links from /¢———
`input switch through whichall the
`destinations are reachable
`
`the inputswitch
`
`
`
`
`
`Page | of 83
`
`FLEX LOGIX EXHIBIT 1046
`
`FLEX LOGIX EXHIBIT 1046
`
`Page 1 of 83
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`

`US 10,050,904 B2
`Page 2
`
`networks, generalized hypercube networks, and generalized
`cube connected cycles networks for speedup of s21. The
`embodiments of VLSI layouts are useful
`in wide target
`applications such as FPGAs, CPLDs, pSoCs, ASIC place-
`ment and route tools, networking applications, parallel &
`distributed computing, and reconfigurable computing.
`
`20 Claims, 43 Drawing Sheets
`
`Related U.S. Application Data
`
`continuation of application No. 13/502,207, filed as
`application No. PCT/US2010/052984 on Oct. 16,
`2010, now Pat. No. 8,898,611.
`
`(60) Provisional application No. 61/252,603, filed on Oct.
`16, 2009, provisional application No. 61/525,609,
`filed on Oct. 16, 2009.
`(58) Field of Classification Search
`CPC wees GO6F 17/5077; GO6F 15/7867; GO6F
`15/8015; GO6F 19/24; GO6F 19/345;
`GO6F 1/163; GO6F 3/00; GO6F 3/0325;
`GO6F 3/042; GO6F 3/04842; GO6F
`3/04845; GO6F 3/0425; GO6F 17/509;
`GO6F 19/702
`USPC iceccsccessecrssctesecectesssenscnseenaees 716/126-132
`See application file for complete search history.
`
`(56)
`
`References Cited
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`8,363,649 B2
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`
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`Page 2 of 83
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`

`US 10,050,904 B2
`Page 3
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`(56)
`
`References Cited
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`
`V. P. Roychdowdhury et. al., “Segmented Channel Routing,” IEEE
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`
`* cited by examiner
`
`Page 3 of 83
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 1 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 2 of 43
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 3 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 4 of 43
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`US 10,050,904 B2
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`Aug. 14, 2018
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`Sheet 5 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 6 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 7 of 43
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`Aug. 14, 2018
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`Sheet 8 of 43
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`Aug. 14, 2018
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`Sheet 9 of 43
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`Aug. 14, 2018
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`Aug. 14, 2018
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`Sheet 11 of 43
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`Aug. 14, 2018
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`Sheet 12 of 43
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`Aug. 14, 2018
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`Sheet 13 of 43
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`Aug. 14, 2018
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`Sheet 14 of 43
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`Aug. 14, 2018
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`Sheet 15 of 43
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 16 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 17 of 43
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`US 10,050,904 B2
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`U.S. Patent
`
`Aug. 14, 2018
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`Sheet 18 of 43
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`US 10,050,904 B2
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`Aug. 14, 2018
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`Sheet 19 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 20 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 21 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 22 of 43
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 23 of 43
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`US 10,050,904 B2
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`Aug. 14, 2018
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`Aug. 14, 2018
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`Sheet 26 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 28 of 43
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`US 10,050,904 B2
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 29 of 43
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`US 10,050,904 B2
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