4,874,971
`(11) Patent Number:
`United States Patent 15
`
` Fletcher [45] Date of Patent: Oct. 17, 1989
`
`
`[54] EDGE-SENSITIVE DYNAMIC SWITCH
`
`[75]
`
`Inventor:
`
`Thomas D. Fletcher, Orem, Utah
`
`[73] Assignee: North American Philips Corporation,
`Signetics Division, Sunnyvale, Calif.
`
`[21] Appl. No.: 180,425
`
`[22] Filed:
`
`Apr. 8, 1988
`
`[63]
`
`Related U.S. Application Data
`ol,
` Continuation-in-part of Ser. No. 934,753, Nov. 25,
`1986, Pat. No. 4,740,717.
`
`[S2] Unt, CL+ oeesescsssecsssesesscnsesecerenssees H03K 5/153.
`[52] U.S. Ch....cessnscsescnseosecsseneeesesnees 307/605; 307/573;
`
`307/576; 307/594; 307/517
`[58] Field of Search ............... 307/443, 573, 575, 576,
`307/585, 597, 601, 605, 266, 261, 517, 518, 594,
`273; 328/114
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,039,858
`8/1977 Stewart .
`FOREIGN PATENT DOCUMENTS
`0242721 12/1985 Japan eosccoccevcseevecccseeneneencosenes 307/576
`Primary Examiner—John Zazworsky
`Attorney, Agent, or Firm—R. Meetin; D. Treacy; T.
`Briody
`
`ABSTRACT
`[57]
`An edge-sensitive dynamic switch center around a
`transmission gate (16) formed with a pair of comple-
`mentary FET’s (Qw and Qp) coupled togetherin paral-
`lel between a pair of nodes (1 and 2). The signals at the
`two nodes vary between a low voltage level and a high
`voltage level. An inverter (17) is coupled between the
`gate electrodes of the FET’s. A delay element (18) is
`coupled between oneof the nodes and oneofthe gate
`electrodes. Due to the transmission delays through the
`delay element andthe inverter, the switch turns off with
`a controlled delay.
`
`11 Claims, 5 Drawing Sheets
`
`
`
`Page | of 12
`
`FLEX LOGIX EXHIBIT 1045
`
`FLEX LOGIX EXHIBIT 1045
`
`Page 1 of 12
`
`

`

`
`
`US. Patent—Oct. 17, 1989 Sheet 1 of6
`
`4,874,971
`
`Page 2 of 12
`
`Page 2 of 12
`
`

`

`US. Patent
`
`Oct. 17, 1989
`
`Sheet 2 of6
`
`4,874,971
`
`
` aN&Le
`
`Page 3 of 12
`
`Page 3 of 12
`
`

`

`US. Patent
`
`Oct. 17, 1989
`
`Sheet 3 of 6
`
`4,874,971
`
`
`
`VHH
`
`V
`
`LL
`
`ON
`OF
`ON
`OFF
`
`VH
`
`VEL
`
`Fig. Sb
`W
`Va
`“vs
`
`V3 7
`XN B
`NESS
`ALS
`
`Qy CONDITION
`
`Qp CONDITION
`
`.
`
`V0 eee eee eeeee eee
`
`—_
`
`—
`
`TIME —a—
`
`Page 4 of 12
`
`Page 4 of 12
`
`

`

`
`
`US. Patent—oct. 17, 1989 Sheet 40f6 4,874,971
`
`
`
`Page 5 of 12
`
`Page 5 of 12
`
`

`

`
`
`US. Patent—Oct. 17, 1989 OS ‘Sheet 5 of 6 4,874,971
`
`———+
`VOLTAGE
`VOLTAGE
`VOLTAGE—-» VOLTAGE
`
`———» Ss Cc
`
`(PRIOR ART}
`
`3)
`
`yyy ———— t3.5
`
`tT
`
`otis.
`
`te)
`
`Page 6 of 12
`
`Page 6 of 12
`
`

`

`
`
`US. Patent—Oct. 17, 1989 Sheet6 of 6 4,874,971
`
`
`
`Fig. 6
`
`Page 7 of 12
`
`Page 7 of 12
`
`

`

`4,874,971
`
`1
`
`EDGE-SENSITIVE DYNAMIC SWITCH
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This is a continuation-in-part of U.S. patent applica-
`tion Ser. No. 934,753, filed November 25, 1986 now
`U.S. Pat. No. 4,740,717.
`
`FIELD OF USE
`
`This invention relates to an electronic circuitry em-
`ploying transmission gates formed with complementary
`field-effect transistors (FET’s).
`BACKGROUND ART
`
`A useful building block for a semiconductor inte-
`grated circuit (IC)is a transmission gate consisting of a
`pair of opposite-polarity FET’s connected in parallel.
`Depending onthe signals that control the gate, it can be
`placed in a conductive condition across the full range of
`the IC powersupply voltage. This is highly desirable in
`many applications.
`Referring to FIG.1,it illustrates how a transmission
`gate 10 is used in a transition detector as disclosed in
`U.S. Pat. No. 4,039,858. Gate 10 is composed of an
`N-channel insulated-gate FET QO0y and a P-channel
`insulated-gate FET QOp. One source/drain element of
`FET QOyis connected to one source/drain element of
`FET Q0p by way of a node 1 at which a gate input
`signal V1 is received. The other source/drain elementof
`FET Q0y is connected to the other source/drain ele-
`ment of FET Q0pvia a node 2 at which a gate output
`signal V2 is supplied.
`An inverter 11 is connected between the gate elec-
`trodes. In response to a signal V3 provided from a node
`3 connected to the QOy gate electrode, inverter 11
`supplies an inverse signal V4 to the QOp gate electrode.
`Signal V2 is provided toa flip-flop 12 that supplies a
`signal V5 representing theflip-flop state. Signal V2 con-
`trols flip-flop 12 when transmission gate 10 is conduc-
`tive. An EXCLUSIVE NORgate 13 provides a detec-
`tion signal Vs as the EXCLUSIVE NORofsignals V;
`and Vs. The final componentof the transition detector
`is an inverter 14 that generates signal V3 by inverting
`signal V6.
`The transition detector operates as follows. Both of
`FET’s QOy and QOpare normally off so that gate 10 is
`non-conductive. Signal V¢is normally at a high voltage.
`Whensignal V; makesa voltage transition in one direc-
`tion, the signal transmission delays through the detector
`enable gate 10 to turn on briefly. This causes a pulse
`indicative of the transition to appear in signal V». A
`similar pulse occurs in signal V6 when signal V, later
`makesa transition in the opposite direction.
`
`GENERAL DISCLOSURE OF THE INVENTION
`
`10
`
`15
`
`20
`
`40
`
`45
`
`55
`
`2
`signal is present. An inverter responsiveto a third signal
`at a third node coupled to the gate electrode of one of
`the FET’s provides a substantially inverse fourth signal
`to the gate electrode of the other FET.
`A critical part of the switch is a delay element that
`causes the third signal to continually follow the first
`signal, either directly or inversely, by a specified time
`delay. The delay elementis typically an inverting cir-
`cuit coupled between the first and third nodes. The
`delay element may, however, be a non-inverting buffer
`circuit.
`The switch turns off in response to a voltage transi-
`tion of the first signal in one particular direction. By
`virtue of the transmission delays through the delay
`element and the (first-mentioned) inverter, one of the
`FET’s turns on briefly when thefirst signal makes such
`a transition. This delays the time at which the switch
`turns off by a controllable amount.
`There are a variety of uses for the present switch.It
`can replace a capacitor in some applications because the
`delayed turn-off produces a capacitive-like current
`pulse. For the same reason, the switch can be used in
`creating dynamic hysteresis. The switch can also be
`employed to double clock frequencies or make a latch
`into an edge-sensitive flip-flop.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG.1 is a block/circuit diagram of a priorart transi-
`tion detector.
`FIGS.2a, 2b, 2c, and 2d are block/circuit diagrams of
`four general variations of an edge-sensitive dynamic
`switch in accordance with the invention.
`FIGS.2e and 2fare circuit diagrams for implementa-
`tions of the main delay element in FIGS. 2a-2d.
`FIGS.3a and 3b are respective timing diagrams for
`the versions of the dynamic switch shown in FIGS. 2a
`and 26.
`FIG. 4 is a block/circuit diagram for a portion of a
`digital IC that employs an input inverting device having
`dynamic hysteresis.
`FIGS. 5a and 50 are timing diagramspertinent to the
`digital IC in FIG.4.
`FIG.6 is a circuit diagram showing how the present
`switch is employed in a preferred embodiment of the
`input inverting device of FIG.4.
`Like reference symbols are employed in the drawings
`and in the description of the preferred embodiments to
`represent the sameor very similar item or items. In the
`drawings, each N-channel FET has an arrow pointing
`towardsits channel. Each P-channel FET has an arrow
`pointing away from its channel. All of the FET’s shown
`in the drawings discussed below are enhancement-mode
`insulated-gate devices.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The present invention centers around an electronic
`FIGS. 2a-2d illustrate four general ways for imple-
`circuit in which the transmission delays through circuit
`menting the dynamic switch of the invention. Each of
`components employed with a transmission gate enable
`the implementations centers around a transmission gate
`the circuit to function as an edge-sensitive dynamic
`16 consisting of complementary FET’s Qy and Qpcon-
`switch with a controlled turn-off delay. The transmis-
`nected in parallel between nodes 1 and 2 in the same
`sion gate is formed with a pair of complementary
`manner that FET’s QOy and QOp are arranged in the
`FET’s, each havinga first source/drain element, a sec-
`prior art circuit mentioned above. N-channel FET Qn
`ond source/drain element, and a gate electrode. The
`65
`has a positive threshold voltage Vrv whichis typicaily
`first
`source/drain elements are coupled together
`in the vicinity of 1 volt. P-channel FET Qphas a nega-
`through a first node at whichafirst signal is present.
`tive threshold voltage V rp that is usually around —1
`The second source/drain elements are similarly coupled
`volt.
`together through a second node at which a second
`
`Page 8 of 12
`
`Page 8 of 12
`
`

`

`4,874,971
`
`15
`
`20
`
`25
`
`30
`
`35
`
`3
`Signals V; and V2 are again respectively present at
`nodes 1 and 2. During normal operation, signal Vtra-
`verses a voltage range extending from a fixed low sup-
`ply voltage Viz to a fixed high supply voltage Vaz.
`Signal V2 traverses the same voltage range. Letting
`Vps represent the differential power supply voltage
`Vuay—Vit, Ves exceeds both Vry and |V7p|. For
`example, Vps is typically about 5 volts.
`An inverter 17 operating in response to signal V3
`supplied from node 3 to the gate electrode of one of 10
`FET’s Qy and Qp provides substantially inverse signal
`V4 to the gate electrode of the other FET. Inverter 17
`has its input and output respectively connected to the
`Qw gate electrode and the Qpelectrode in the embodi-
`ments of FIGS.2a and 26. The inverter connections are
`reversed in the implementations of FIGS. 2c and 2d.
`A main delay element 18 responsive to signal V
`generatessignal V3 in such a way that changesin signal
`V3 follow changes in signal Veither directly or in-
`versely. In FIGS. 2a and 2c, delay element 18 is an
`inverting circuit whose input and output are respec-
`tively connected to nodes 1 and 3. Signal V3 thus in-
`versely follows signal V1 in these two versions of the
`switch. In FIGS. 26 and 2d, element 18 is a non-invert-
`ing buffer circuit having its input and output respec-
`tively connected to nodes 1 and 3 so that signal V3
`directly follows signal V1.
`Components 17 and 18 are usually implemented in
`such a mannerthat signals V3 and V4 vary across the
`entire Vps voltage range. For example, inverter 17 may
`be a conventional CMOS-type inverter consisting of a
`pair of complementary FET’s connected in series be-
`tween supply lines that receive voltages Viz and Vayu.
`Element 18 in FIGS. 2a and 2c can be formed in the
`same way or as an odd number(e.g., 3, 5, ... ) of such
`inverters connectedin series. FIG.2e illustrates the case
`in which element 18 consists of three serially connected |
`CMOS-type inverters 18), 182, and 183. Element 18 in ©
`FIGS.26 and 2d can be implemented as an even number
`(e.g., 2, 4,...) of conventional CMOS-type inverters
`connected in series. FIG. 2f shows the case in which
`element 18 consists of two serially connected CMOS-
`type inverters 184 and 185.
`The present switch, as represented by the condition
`of gate 16 and thus by the conditions of FET’s Qn and
`Qp, turns off with a controlled time delay in response to
`a transition of signal V in a particular voltage direction.
`Referring to FIGS. 3a and 35, they depict timing dia-
`grams helpful in understanding the operation of the
`switch. FIG. 3a applies specifically to The implementa-
`tion of FIG. 2a. FIG 34 applies to FIG. 2b. The voltage
`curves representing signal V; are shownin thickerline
`in FIGS. 3a and 38 to help distinguish signal V; from
`signals V3 and V4.
`the approximate
`t4 and rp respectively represent
`transmission delays through components 18 and 17 mea-
`sured from threshold to threshold. That is, 7,4 is the
`difference between the time at which signal V, passes
`the threshold voltage for element 18 and the later time
`at which signal V3 passes the same voltage in response
`to the changein signal V1. rgis similarly the time period
`that signal V4 is delayed relative to signal V3 measured
`at the threshold voltage for inverter 17. The total trans-
`mission delay from signal V1 to signal V4 is T4+78.
`The threshold voltages for components 17 and 18
`and, consequently, the transmission delay measurement
`points are typically about halfway between voltages
`Viz and Vay when components 17 and 18 are impie-
`
`40
`
`45
`
`50
`
`355
`
`60
`
`65
`
`Page 9 of 12
`
`4
`mented using the CMOS-type circuitry described
`above. This case is shown in FIGS. 3a and 38.
`Turning specifically to FIG. 3a, assume that signal
`Vis initially at low voltage Viz. V3is initially at high
`voltage Vin due to the inversion provided by element
`18 in FIG. 22. FET Qwis turned on since the V3—V1
`voltage difference equals power supply voltage Vps and
`is therefore greater than N-channel threshold Vry.
`Gate 16 is turned on. Signal V2 is at Vzz. Signal V4is
`also at Viz. Because signal V4 is at the same voltage as
`signals V; and V2, FET Qpis turnedoff.
`Viis now raised to Vyy. V2 starts following V1 up-
`ward. V3--Vdrops towards —Vps so as to turn off
`FET Qw.Delay 7,4 through element 18 extends the time
`during which FET Qwis turned on. This assists V2in its
`upward rise. FET Qw turns off when V3—V drops
`below Vin.
`V4 also follows Vi upward. Due to delays 74 and rp
`through components18 and17, thereis a short period of
`time before FET Qy turns off during which the
`V4—V} voltage difference temporarily drops below
`P-channel threshold Vp. That is, V4 trails V; by more
`than |V7p|. This allows FET Qptoturn onbriefly. The
`dynamic turn on of FET Qp usually enables V2to rise
`all the way up to Vay.
`FET Qp turns off when V4 has risen enough that
`Va—Vi is greater than Vrp. With FET Qp now turned
`off, gate 16 is turned off. The result is that the time at
`which gate 16 turns off in response to a low-to-high
`voltage transition in signal V1 is delayed by an amount
`dependent on delays 74 and rp.
`After gate 16 turns off node 2 is effectively discon-
`nected from node 1. The variation in the V2 voltage, as
`indicated by the dotted portion of the V2 curve in FIG.
`3a, is now determined by whateverfurthercircuitry is
`connected to node 2. At a later time, Vj
`is returned to
`Vit. FET Qnturns back on to reactivate gate 16. If not
`already set at Vzz by the further circuitry connected to
`node 2, V2 returns to Vzz. This completes the cycle.
`Thesituation is similar with the embodiment shown
`in FIG.25 exceptthat the roles of FET’s Qvand Qpare
`largely reversed so that the switch has a delayed turn-
`off when V; makes a high-to-low voltage transition.
`With reference to FIG. 3b, FET Qpis turned on during
`the time that V1 is at Vay. Gate 16 is conductive. When
`Vis reduced to Viz, FET Qn turnson briefly to delay
`the time at which gate 16 turns off by an amountdeter-
`mined by delays r4 and rg.
`The implementations of FIGS.2c and 2d respectively
`operate in the same way as those of FIGS. 2a and 26
`with the voltage polarities and roles of FET’s Qn and
`Qp reversed.
`When a fast IC interacts with the outside world, the
`voltages on the internal supply lines often “bounce” up
`and down. The bounce can cause the IC to operate
`improperly whenit responds to an input signal having a
`slowly changing voltage. The problem usually becomes
`more serious as the IC speed increases. FIGS. 4, 5a, 5d,
`and6 illustrate an example of how the present dynamic
`switch is employed in creating dynamic hysteresis to
`prevent supply line bounce from causing improper IC
`operation.
`Beginning with FIG.4, it shows a portion of a digital
`IC 20 that receives supply voltages Vay and Viz at
`respective supply terminals (or pads) Tyand Tz. IC 20
`producesa circuit output voltage Voat an output termi-
`nal Tg in responseto a circuit input voltage Vrreceived
`at an input terminal T;. A capacitor Co (real or para-
`
`Page 9 of 12
`
`

`

`5
`sitic) is connected between terminal To and the Vzzr
`supply.
`The illustrated portion of IC 20 is a very fast logic
`circuit powered by high and low internal supply volt-
`ages Vy and Vz provided on lines connected respec-
`tively to terminals Tzand Tz. Responsiveto an internal
`input voltage V4 supplied on a line connected to termi-
`nal T;, the logic circuit produces an internal output
`voltage Vpon a line connected to terminal To. Parasitic
`inductances Lz, Ly, L, and Loarerespectively associ-
`ated with the lines carrying voltages Vz, Vy, V4, Vp.
`The logic circuit consists of (a) an input inverting
`device 22 formed with an input inverter 23 and a dy-
`namic hysteresis circuit 24 that together generate a
`voltage Vg inverse to voltage V4, (b) an intermediate
`logic section 26 that operates on voltage Vz and possi-
`bly on other input voltages (not shown) to produce a
`voltage Vc at a value that is logically the same as or
`inverse to voltage Va, and (c) an output inverter 27 that
`generates voltage Vp as the inverse of voltage Vc.
`Inverter 23 is a conventional CMOS-type inverter
`formed with complementary input FET’s Qlwand Q1p.
`Inverter 27 is similarly formed with complementry
`output FET’s Q2y and Q2p.
`Dynamic hysteresis circuit 24 consists of a control
`circuit 28 powered by supply voltages Vy and Vz, an
`N-channel FET Q3y, and a P-channel FET Q3p. In
`response to voltage Vg controlcircuit 28 supplies thre-
`shold-control voltages Vw and Vp to the respective
`gates of FET’s Q3y and Q3p. FET Q3yis “in parallel”
`with FET Qly. FET Q3pis similarly in parallel with
`FET Qip.
`Circuit 24 provides dynamic hysteresis for the thresh-
`old voltage Vr of device 22. More particularly, the
`threshold voltage for an inverter formed with comple-
`mentary FET’s depends on the ratio Rpyy of the P-
`channel width to the N-channel width (at constant
`channel length). This means the widths of the channel
`areas that are conducting at the threshold point. The
`threshold voltage increases when Rp;yn increases and
`vice versa.
`FET’s Q3y and Q3p are normally off or at so low
`conductive levels as to be effectively off. Accordingly,
`the quiescent value of Rpyn for device 22 is simply the
`Q1p channel width divided by the Q1y channel width
`since FET’s Q1y and Q1ip are both conducting at the
`threshold point, one in the midst of turning on and the
`other in the midst of turning off. If FET Q3y is on but
`FET Q3pis off, the N-channel width for device 22
`increases since FET’s Q3y and Q1yare in parallel.
`Rpyw for device 22 is therefore less than its quiescent
`value. In like manner, Rp;y for device 22 is greater than
`the quiescent value when FET Q3pis on but FET Q3y
`is off.
`With the foregoing in mind, device 22 operates as
`follows. FET’s Q3y and Q3? are initially off. Supply
`voltages Vz, and Vy areinitially at (or very near) re-
`spective substantially constant levels Vzz and Vay.
`Under these conditions, threshold V7 is at a quiescent
`value Vs determined by the quiescent Rp;y of device
`22. When the difference V4— Vz passes V7, device 22
`changesstate.
`If V4 rises above Vir+Vs, FET Q1y turns on and
`FET Q1>pturns off. Device 22 as represented by the
`conductive conditions of FET’s Q1,y and Q1p switches
`from a high logic state to a low logic state, causing Vz
`to go from a high level near Vy to a low level near
`VL. Responsiveto this change in Vz, control circuit 28
`
`20
`
`25
`
`40
`
`45
`
`55
`
`60
`
`65
`
`4,874,971
`
`6
`temporarily raises Vx enough to turn FET Q3y on for
`a brief period. FET Q3p remains off. Rpyxy drops below
`its quiescent level. This reduces V7 until circuit 28 re-
`duces Vy sufficiently to turn FET Q3y backoff.
`Largely the reverse occurs when Vy drops below
`Vir+Vs. FET Q1y turns off and FET Q1>pturns on,
`causing device 22 to switch from its low logicstateto its
`high logic state. Vg goes from Vzup to Vay.In re-
`sponse to this Vz change, circuit 28 temporarily pro-
`vides Vp at a sufficiently low voltage to turn FET Q3p
`on for a short time. FET Q3y stays off. Consequently,
`Rpyntises aboveits quiescent value so as to increase V7.
`Whencircuit 28 subsequently raises Vpto turn off FET
`Q3p, Vrdrops back down.
`Now, look at what happens in IC 20 if input Vz
`changes very slowly. Assume (for example) that logic
`section 26 provides a voltage inversion so that Vcis the
`inverse of Vz.
`First consider how IC 20 would operate if (as in the
`prior art) dynamic hysteresis circuit 24 were absent.
`This case is represented by the voltage variations shown
`in FIG. 5a. Assumethat Vis initially low. Also assume
`that Vz and Vyare respectively at Vrz and Vay. Vais
`then low, causing Vz to be at Vy. Vc is low so that
`FET Q2wis turned off and FET Q2pis turned on. Vp
`and Vg are both at VaH. Capacitor Co is charged to a
`high level.
`As Vrrises slowly, V4 tracks V; closely. Inductance
`Ly; does not have anysignificant effect. At a time t1, V4
`starts to go above Vri+Vs. This causes Vz to drop
`rapidly to Viz. Vc goes high to turn FET Q2;y on and
`FET Q2p?off. Vp drops rapidly to Vzzr. At a time tz
`depending on the transmission delays through compo-
`nents 26 and 27, capacitor Co starts discharging to the
`VL supply by way of a. path through elements Lo,
`Q2n, and Lz to pull Vo rapidly down to Vz.
`The current. flowing through this path varies with
`time in a non-linear manner. Since the voltage across an
`inductoris the inductancetimes the time rate of change
`of current flowing through the inductor, a positive
`voltage builds up across inductance Lz, reaching a
`maximum at a time t3. A positive (or upward going)
`spike in Vz thereby occurs at t3 as shown in FIG.5a.
`The Vz spikeat t3 is the “first” spike in a set of timewise
`contiguous pairs of alternating apikes that die out
`quickly, of which onlythefirst pair of alternating spikes
`are actually shownin FIG.5a.
`The Vz spike at t3 is often so high that V4— Vz tem-
`porarily drops below threshold V7. See shaded area 29
`in FIG. 5a. Inverter 23 then makes a pair of rapid
`changesin logic state at approximately a time t4, caus-
`ing Vg to spike upwards. In turn, the Vz spike causes a
`positive Vo spike to occur at a time ts.
`The samesituation arises if Vz drops slowly, except
`that the polarities and supply lines are reversed. The
`first spike is a negative Vy spike that results from the
`rapid charging of capacitor Co by way of a path
`through elements Ly, Q2p, and Lo.
`The Vo spikes and the corresponding spikes in Va,
`Vc, and Vp can be disastrous. They could causea cir-
`cuit (such as a flip-flop) responsive to Vo, Va, Vc, or
`Vp to beset at a wrongstate.
`Circuit 24 enables IC 20 to avoid unwanted changes
`of state that would otherwise occuras a result of supply
`line bounce. FIG. 5b, which is an analogous timing
`diagram to FIG. 5a for the case in which circuit 24 is -
`present, is helpful in showing how this is accomplished.
`
`Page 10 of 12
`
`Page 10 of 12
`
`

`

`4,874,971
`
`8
`gradually turns off, positive charge from the Vy line
`now flows through FET’s Q4pand Q8pto the Q3y gate
`to raise Vy further. This continues for the entire time
`needed for inverter 36 to raise VG up to Vay. At some
`point during the charging of the Q3y gate, FET Q3v
`turns on.
`Wheninverter 38 finally switches, FET Q8pturnsoff
`to stop the charging of the Q3,ygate. At this point, FET
`QS5;turnson.It opens a path to the Vz line for discharg-
`ing the Q3y gate, causing FET Q3y to turn off. Invert-
`ers 36 and 38 and FET’s Q4n, Q9n, Q9p, and Q5p oper-
`ate in a similar, complementary manner to enable FET
`Q3p to turn on briefly when Vz later returns to Vy.
`If the transmission delay of inverter 36 or 38 is too
`small to allow enough time to charge the Q3y gate
`and/or the Q3p gate, a further delay element can be
`placed in series with inverter 36 or 38. The delay ele-
`ment might, for example, consist of a pair of inverters in
`series.
`While the invention has been described with refer-
`ence to particular embodiments,
`this description is
`solely for the purpose ofillustration and is not to be
`construedas limiting the scope of the invention claimed
`below. For example, junction FET’s could be used
`instead of insulated-gate FET’s. Certain of the enhance-
`ment-mode FET’s could be replaced with depletion-
`mode FET’s. Various modifications and applications
`may thus be made by those skilled in the art without
`departing from the true scope andspirit of the invention
`as defined by the appended claims.
`I claim:
`1, An electronic circuit comprising (a) a pair of com-
`plementary field-effect transistors (FET’s), each having
`a first source/drain element, a second source/drain
`element, and a gate electrode, the first source/drain
`“ elements coupled together througha first node at which
`a first signal is present, the second source/drain ele-
`ments coupled together through a second node at
`which a second signal is present, both of the first and
`second signals substantially varying between a low
`voltage level and a high voltage level, and (b) an in-
`verter responsive to a third signal at a third node cou-
`pled to the gate electrode of one of the FET’s for pro-
`viding a substantially inverse fourth signal to the gate
`electrode of the other FET, characterized by delay
`means for causing the third signal to continually follow
`the first signal, either directly or inversely, by a speci-
`fied time-delay.
`2. A circuit as in claim 1 characterized in that the
`inverter provides a further time delay such that the
`fourth signal continually follows the first signal, either
`inversely or directly, by the sum of the two delays.
`3. A circuit as in claim 1 characterized in that the
`delay means comprises inverting means coupled be-
`tween the first and third nodes.
`4. A circuit as in claim 3 characterized in that the
`inverting means comprises a single inverter or an odd
`numberof inverters coupled in series.
`5. A circuit as in claim 3 characterized in that the
`FET’s are enhancement-mode insulated-gate FET’s.
`6. A circuit as in claim 1 characterized in that delay
`means comprises non-inverting buffer means coupled
`between the first and third nodes.
`7. A circuit as in claim 6 characterized in that the
`buffer means comprises an even number of inverters
`coupled in series.
`8. A circuit as in claim 6 characterized in that the
`FET’s are enhancement-modeinsulated-gate FET’s.
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`60
`
`65
`
`7
`Theinitial conditions for the case shown in FIG. 55
`are the same as those for FIG. 5a. As Vyrises slowly,
`Va follows closely. When V4 passes Viz+Vsat time
`t1, Vz drops rapidly to Vzz. In response, hysteresis
`circuit 24 reduces V starting at a time t;,5. The differ-
`ence between dottedline 30 and the solid line represent-
`ing Va—Vrin FIG.5b indicates the amount of reduc-
`tion in Vr.
`Capacitor Costarts discharging at time tz. This pro-
`duces a positive Vz spike at time t3 according to the
`mechanism described above. Due to the V7 reduction
`producedbycircuit 24, V4— Vz stays above Vduring
`the positive Vz spike. Capacitor Co thereby remains
`discharged so as to substantially inhibit any further
`internal supply line voltage bounce. Accordingly, no
`spikes occur in Vz, Vc, Vp, and Vo. Ata later timet3,s,
`Vr automatically returns to Vs.
`The situation in which V;falls slowly is essentially
`the complementof that shown in FIG.5d. In the inter-
`val between t;.5 and t3,5, circuit 24 increases V7 by an
`amount sufficient to prevent spikes from occurring in
`Ve, Vc, Vo, and Vo. If section 26 supplies Vc at the
`samelogical value as Vg,circuit 24 operates in basically
`the same way to prevent undesired changesin state.
`The dynamic switch of the invention is employed in
`a capacitive-like mode in a preferred embodiment of
`control circuit 28 shown in FIG. 6. Circuit 28 consists
`of (a) an inverter 34 formed with complementary FET’s
`Q4ynand Q4p that produce a voltage Vz inverse to volt-
`age Vp, (b) dynamic switches 35, and 35p that respec-
`tively produce voltages Vj and Vpin response to volt-
`age Vz, and (c) complementary discharge FET’s Q5n
`and Q5p whose gate electrodes receive a voltage Vo.
`FET Q85wis source-drain connected between the Vz
`line and the Q3w gate. FET Q5pis source-drain con-
`nected between the Vy line and the Q3>pgate.
`Switch 35y consists of an inverter 36 that provides a
`voltage Vas the inverse of voltage Va, an inverter 38
`that produces voltage Va as the inverse of voltage Vr,
`and a transmission gate 40. Inverter 36 is formed with
`complementary FET’s Q6n and Q6p. Inverter 38 is
`formed with complementary FET’s Q7w and Q7p.
`Transmission gate 40 is formed with complementary
`FET’s Q8y and Q8p whosegate electrodes respectively
`receive voltages Vrand Vg. FET’s Q8y and Q8p have
`interconnectedfirst source/drain elements connected to
`the Q4y and Q4p drains and interconnected second
`source/drain elements connected to the Q3y gate. Con-
`sequently, switch 35x is an embodimentof the switch
`version shown in FIG.2a.
`Switch 35p consists of a transmission gate 42 along
`with inverters 36 and 38. Gate 42 consists of comple-
`mentary FET’s Q9vy and Q9p arranged with regard to
`the Q3p gate in a manner that is complementary to the
`arrangement of gate 40 with respect to the Q3y gate.
`Switch 35pis thus an embodimentof the version shown
`in FIG.2c.
`Circuit 28 in FIG. 6 operates as follows. Assumethat
`Vapis initially at Vaso that FET Q4y is on and FET
`Q4pis off. Vris likewise at Via. Vgand Vaare both at
`Vi. FET Q8wis on, thereby setting Vyat Viz. FET’s
`Q3n, Q5n, and Q8y areall off.
`When Vg drops to Vzz, FET Q4y turns off and FET
`Q4p turns on. Vz starts rising toward Vyy. During an
`initial part of the time needed for inverter 36 to drop
`Vr down to Vzz, positive charge from the Vqline
`flows through FET’s Q4pand Q8y to the Q3y gate. Vv
`starts to rise as FET Q8pturns on. Although FET Q8y
`
`Page 11 of 12
`
`Page 11 of 12
`
`

`

`9
`
`4,874,971
`
`10
`comprises logic means for performing a logical opera-
`tion.
`11. A circuit as in claim 10 characterized in that the
`inverter provides a further time delay such that the
`fourth signal continually follows thefirst signal, either
`inversely or directly, by the sum of the two delays.
`x
`*
`#€
`*
`*
`
`9. A circuit as in claim 1 further including circuit
`means coupled to the second node for producing a
`furthersignal that varies in response to the secondsig-
`nal as it varies between the low and high voltagelevels.
`10. A circuit as in claim 9 wherein the circuit means
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`35
`
`65
`
`Page 12 of 12
`
`Page 12 of 12
`
`