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`US 7,558,967 B2
`(10) Patent No.:
`a2) United States Patent
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`Jul. 7, 2009
`(45) Date of Patent:
`Wong
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`US007558967B2
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`(54) ENCRYPTION FOR A STREAMFILE IN AN
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`FPGA INTEGRATED CIRCUIT
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`(75)
`Inventor; Wayne Wong, Sunnyvale, CA (US)
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`(73) Assignee: (us) Corporation, MountainView, CA
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`(*) Notice:
`Subject to any disclaimer, the term ofthis
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`patent is extended or adjusted under 35
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`U.S.C. 154(b) by 583 days.
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`(21) Appl. No.: 09/953,580
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`Sep. 13, 2001
`Filed:
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`5,768,372 A
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`5,946,478 A *
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`5,970,142 A
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`6,028,445 A *
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`6,118,869 A *
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`6,205,574 B1L*
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`6.351.142 BL*
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`6,357,037 B1*
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`6,446,242 BL*
`6.507.943 BI*
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`EP
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`6/1998 Sungetal.
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`8/1999 Lawman ou... eee 716/17
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`10/1999 Erickson.....
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`2/2000 Lawman ........
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`9/2000 Kelemetal. oe. 380/44
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`3/2001 Dellinger et al... , 716/16
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`2/2002 Abbott oo...
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`3/2002 Burmhametal.
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`9/2002 Li
`tad.
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`eee eeee 716/6
`1/2003 Kelem 716/16
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`(Continued)
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`FOREIGN PATENT DOCUMENTS
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`4/2001
`1093056
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`(Continued)
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`OTHER PUBLICATIONS
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`Microsoft Press Computer Dictionary, 3rd edition, Copyright 1997,
`p.421.*
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`4,910,417 A
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`5.451.887 A
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`5,548,648 A *
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`5,675,553 A
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`Prior Publication Data
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`US 2003/0163715 Al
`Aug. 28, 2003
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`Int. Cl.
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`(2006.01)
`HOAL 9/18
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`(52) U.S.C. eens 713/189; 716/16; 716/17;
`326/8; 326/38; 326/39; 713/191; 713/193
`primaryPxaminerBambiaNes
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`(58) Field of Classification Search............. 716/16-17; Avent.orFirm—LewisTA) Att and Roca LLP
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`326/8, 37-41, 4, 44: 380/44. 42. 37: 708/232,
`Attorney, Agent, or Firm—Lewis and
`Roca
`(74)
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`(57)
`_ 708/626, 712/206; 713/191, 188, 189, 193
`ABSTRACT
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`See application file for complete search history.
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`References Cited
`A system for encrypting and decrypting data in a data stream
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`for programminga Field Programmable Gate Array (FPGA).
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`U.S. PATENT DOCUMENTS
`The system allows for an enable bit to be set for a gap in the
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`data stream andthe data is then encrypted from the beginning
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`ofthe gap. A gap beingbits in said data stream that correspond
`3/1990 EL Gamal et al. «........-. 307/465
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`2/1995 Austin ..scecseesnesseeee 3804
` mproorammed addresses of a memory
`in the field vro-
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`4/1995 Thompsonetal. .......... 380/237
`programm
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`P
`ty
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`6/1995 Trimberger.....
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`grammable gate array. The data is then decrypted by the
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`9/1995 El Avatetal.
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`FPGA when the bit stream is received and an enable bit is
`...
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`5/1996 Kattaetal. wc 380/217
`detected in a gap of the data stream.
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`8/1996 Yorke-Smith «0.0.00... 713/193
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`10/1997 O’Brien, Jr. etal.
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`(Continued)
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`30 Claims, 4 Drawing Sheets
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`|PROGRAMFPGA]____-——— 200
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`PRODUCE DATA STREAM 210
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`SELECT ENCRYPTION OF DATA STREAM|___ 20
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`ENCRYPT DATA STREAM
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`STORE ON EXTERNAL SOURCE
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`~~ 240
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`SEND ENCRYPTED DATA STREAM TO FPGA |~ 250
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`DE-ENCRYPT DATA STREAM
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`“260
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`CONFIGURE RAM/PROM
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`WITH DE-ENCRYPTED
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`DATA STREAM
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`JP
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`7-281596 A
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`2000-76075 A
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`2000-78023 A
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`2005-518691 A
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`10/1996
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`3/2000
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`6/2005
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`2/2003 Young et al. ......... 716/16
`6,526,557 B1*
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`6,654,889 B1* 11/2003 Trimberger
`. 713/191
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`6,735,291 BL*
`5/2004 Schmid etal.
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`6,738,962 B1*
`5/2004 Flaherty etal.
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`6,756,811 B2
`6/2004 Or-Bach.....
`326/41
`Glenn, R. and Kent, S., “The NULL Encryption Algorithm andIts
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`6,904,527 BL*
`6/2005 Parlour etal.
`. 713/189
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`Use with IPsec,” RFC 2410,Network Working Group, Nov. 1998, UR
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`6,931,543 BL*
`8/2005 Pangetal.
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`weve 713/193
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`http://www.faqs.org/ftp/rfe/pdf/rfc2410.txt.pdf, 6 pages.
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`2001/0032318 Al* 10/2001 Yipetal.
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`Patent Application
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`2001/0056546 AL* 12/2001 Ogilvie... 713/200 apanese*arent Appicaion No. - uniicaliion (NO.
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`2005-518691) Notice ofAllowance and English translation of Infor-
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`mation Sheetfor priorart listed in Notice ofAllowance dated Sep. 30,
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`2008, 4 pages.
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`* cited by examiner
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`FOREIGN PATENT DOCUMENTS
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`05056267 A
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`U.S. Patent
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`Sheet 1 of 4
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`US 7,558,967 B2
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`SEND DATA STREAM TO FPGA
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`CONFIGURE RAM/PROM WITH DATA STREAM |— 140
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`PRIOR ART
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`FIG. 1
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`U.S. Patent
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`Sheet 2 of 4
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`PROGRAM FPGA |_---_-_ 200
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`PRODUCE DATA STREAM | nig
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`SELECT ENCRYPTION OF DATA STREAM|__
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`ENCRYPT DATA STREAM|———-——— 230
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`STORE ON EXTERNAL SOURCE|—-~_ 249
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`SEND ENCRYPTED DATA STREAM TO FPGA|™ 250
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`DE-ENCRYPT DATA STREAM~—— 260
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`CONFIGURE RAM/PROM
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`WITH DE-ENCRYPTED
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`DATA STREAM _—
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`FIG. 2
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`Sheet 3 of 4
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`US 7,558,967 B2
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`START
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`OF GAP?
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`ENCRYPTION
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`ENABLED?
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`COMPLEMENT EVERY
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`8th BIT UNTIL
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`DATA STREAM?
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`Sheet 4 of 4
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`OF GAP?
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`Sth BIT UNTIL
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`DATA STREAM? CONFIGURE RAM/PROM
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`END OF
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`US 7,558,967 B2
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`1
`ENCRYPTION FOR A STREAM FILE IN AN
`FPGA INTEGRATED CIRCUIT
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`BACKGROUND OF THE INVENTION
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`2
`can make design changes or correct design errors. The CM
`can be downloaded from an external source or stored on-chip.
`This type of FPGA can be reprogrammedrepeatedly, which
`significantly reduces development and manufacturing costs.
`Design software may be used to program the FPGA. The
`design software may compile a specific configuration of the
`programmable switches desired by the end-user, into FPGA
`configuration data. The design software assembles the con-
`figuration data into a bit stream, 1.e., a stream of ones and
`zeros, that is fed into the FPGA and used to program the
`configuration memories for the programmable switches. The
`bitstream is the data-pattern to be loaded into the CM that
`determines whether each memory cell stores a “1” or “0”. The
`stored bit in each CM controls whetherits associated transis-
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`tor switch is turned on oroff. End users typically use software
`to create the bitstream after they have simulated and, tested
`the design for the FPGA.
`Referring to the flow chart of FIG. 1, a designer or end user
`programs an FPGA 100. The design software assembles the
`configuration data into a data stream 110. This act mayalso be
`performed by software personnel. The data stream may be
`stored on a source external to the FPGA 120. Onstart up, the
`external source sendsthe data stream to the FPGA 130. Once
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`in the FPGA,the data stream configures the RAM or PROM
`within the FPGA.
`Ina FPGAthatuses a data stream that is downloaded from
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`1. Field of the Invention
`The present invention relates to field programmable gate
`array (FPGA) integrated circuits. More particularly,
`the
`present invention relates to a method and apparatus for
`encrypting a data stream used to program an FPGAdevice.
`2. Backgroundofthe Invention
`A field-programmable gate array (FPGA)is an integrated
`circuit (IC) that includes a two-dimensional array of general
`purposelogic circuits, called cells or blocks, whose functions
`are programmable. The cells are linked to one another by
`programmable buses. Thecell types may be small multifunc-
`tion circuits (or configurable functional blocks or groups)
`capable of realizing all Boolean functions of a few variables.
`The cell types are notrestricted to gates. For example, con-
`figurable functional groups typically include memory cells
`and connectiontransistors that may be used to configure logic
`functions such as addition, subtraction, etc., inside of the
`FPGA.A cell may also contain sequential elements such as
`flip-flops. Two types of logic cells found in FPGAsare those
`based on multiplexers and those based on programmable read
`only memory (PROM) table-lookup memories. Erasable
`FPGAscan be reprogrammed manytimes. This technology is
`especially convenient when developing and debugging a pro-
`totype design for a new product and for manufacture.
`FPGAs may typically include a physical template that
`includes an array of circuits, sets of uncommitted routing
`interconnects, and sets of user programmable switches asso-
`ciated with both the circuits and the routing interconnects.
`Whenthese switches are properly programmed(set to on or
`off states), the template or the underlying circuit and inter-
`connect of the FPGA is customized or configured to perform
`specific customized functions. By reprogramming the on-off
`states ofthese switches, an FPGA can perform manydifferent
`functions. Once a specific configuration of an FPGA has been
`decided upon, it can be configured to perform that one spe-
`cific function.
`The user programmable switches in an FPGA can be
`implementedin various technologies, such as Oxide Nitrogen
`Oxide (ONO)antifuse, Metal- Metal (M-M)antifuse, Static
`Random Access Memory (SRAM) memory cell, Flash Eras-
`able Programmable Read Only Memory (EPROM) memory
`cell, and electronically Erasable Progammable Read Only
`Memory (EEPROM) memory cell. FPGAs that employ fuses
`or antifuses as switches can be programmed only once. A
`memory cell controlled switch implementation of an FPGA
`can be reprogrammedrepeatedly. In this scenario, a NMOS
`FIG. 1 is a flow chart showingthepriorart.
`transistor may be used asthe switch to either connector leave
`FIG. 2 is a flow chart showing one embodiment of the
`unconnected two selected points (A,B) in the circuit. The
`disclosed system.
`source and drain nodesofthe transistor may be connected to
`FIG. 3 is a flow chart showing one embodiment of the
`points A, B respectively, and its gate node maybedirectly or
`disclosed system.
`indirectly connected to the memory cell. By setting the state
`FIG. 4 is a flow chart showing one embodiment of the
`ofthe memory cell to either logical “1”or “0”, the switch can
`disclosed system.
`be turned on or off and thus point A andBare either connected
`or remain unconnected. Thus, the ability to program these
`switches provides for a very flexible device.
`FPGAsmaystore the program that determinesthe circuit
`to be implemented in a RAM or PROM on the FPGA chip.
`The pattern of the data in this configuration memory (CM)
`determines the cell’s functions andtheir interconnection wir-
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`an external source, a person maybeable to intercept the data
`stream asit is being loaded onto the FPGA, betweenacts 120
`and 130 of FIG. 1. This may allow such a person to reverse
`engineer the IC if he or sheis able to read the data stream.
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`BRIEF DESCRIPTION OF THE INVENTION
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`The present invention is directed towards a method and
`apparatus for encrypting a data stream used to program an
`FPGAdevice comprising: determiningif there is at least one
`gap in the data stream; determining whether encryption is
`enabled for the at least one gap in the data stream; and
`encrypting the data stream, if encryption is enabledfor the at
`least one gap.
`The present invention is also directed towards a method
`and apparatus for de-encrypting an encrypted data stream
`used to program an FPGA device comprising: determining if
`there is at least one gap in the data stream; determining
`whether encryption was enabledfor the at least one gap in the
`data stream; and de-encrypting the data stream, if encryption
`wasenabled for the at least one gap.
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`BRIEF DESCRIPTION OF THE DRAWING
`FIGURES
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`DETAILED DESCRIPTION OF THE INVENTION
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`Those of ordinary skill in the art will realize that the fol-
`lowing description ofthe present inventionis illustrative only
`and not in any way limiting. Other embodimentsofthe inven-
`tion will readily suggest themselves to such skilled persons.
`FIG.2 refers to a flow chart describing one embodiment of
`the disclosed method. In the first act 200 a designer or user
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`ing. Each bit of CM controls a transistor switch in the target
`circuit that can select some cell function or make (or break)
`some connection. By replacing the contents of CM,designers
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`configuration data into a data stream 210. The design soft-
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`ware may inquire as to whether the designer or the user
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`wishes to have the data stream encrypted. If the designer or
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`user wants the data stream to be encrypted, then he or she may
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`select the option for encryption at act 220. The data stream is
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`encrypted at act 230. This act 230 may also be performed by
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`software personnel. The data stream may bestored on a
`source external to the FPGA 240. The external data source
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`may be a PROM, CPU or any other memory device. On
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`start-up, the external source sends the data stream to the
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`FPGA 250. The FPGA may de-encrypt the data stream prior
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`to configuring the RAM or PROM 260. Once de-encrypted,
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`the data stream configures the RAM or PROM within the
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`FPGA 270. The RAM associated with each programmable
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`transistor on the FPGA may also be referred to as RAM
`CELLS.
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`In many systems, the data stream is loaded into CM which
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`is addressed by X and Y address lines running horizontally
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`and vertically. During the configuration, the data stream bits
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`are loaded sequentially column (Y) by column (Y). Within
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`one column,it is loaded bit by bit from the top to the bottom
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`(stepping through all the rows or X’s). Someintersections of
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`X and Y lines or addresses may have no physical CM bits
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`since those locations may be used by logic modules or other
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`components. Although there may be locations with no data
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`stream bits on the FPGA device, the data stream still contains
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`data in the form of 1’s or 0’s corresponding to those empty
`locations.
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`Consecutive empty locations in the addressing space may
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`be referred to as a “GAP”. The stream data inside the gap is
`not written to the CM and therefore has no effect on the
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`functionality of the configured FPGA. An address decoder
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`maysignal the beginning andalso the end of sucha gap. At the
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`end of the gap, the integrity of the configuration data loaded
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`up to this point may be checked by an on-chip 16-bit Cyclic
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`Redundancy Check (CRC)circuit. In another embodiment of
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`the disclosed system that uses a 16-bit CRC, the minimum
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`gap size may be 17 bits. Thefirst bit inside the gap may be the
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`“Encryption Enable”bit. If the Encryption Enable bit is set,
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`then the subsequent section of the data stream will be
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`encrypted. The section may be defined asall the bits after the
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`Encryption Enable Bit up to the beginning of the next gap.
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`the sections may be defined in other ways. If
`However,
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`encryption is enabled, every eighth (8th) bit may be comple-
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`mented (changed from a “1”to a “0”and from a “0”to a “1”’).
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`Itis not necessary that only the 8” bit be complemented, other
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`bits may be complemented, random patterns or un-random
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`patterns of data may be insertedin the data stream gaps. If the
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`encrypted data stream is loaded into the CM ofthe FPGA,the
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`FPGA maynot function correctly. Thus the data stream may
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`be de-encrypted prior to entering the CM but after entering
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`the FPGA device. The encryption can be optionally set to
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`“on” or “off” for each section, thus for a particular design,
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`with a different on/off setting the data stream file can appear
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`very different, thereby making reverse engineering more dif-
`ficult.
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`Referring to FIG. 3, an illustration of one embodiment of
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`the system is shown. The system receives the data stream at
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`act 310. The system determines whether it has received the
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`start of a gap at query 320. In one embodimentofthe dis-
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`closed system a gap may be as small as 2 bits. In another
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`embodimentofthe disclosed system, a gap may beat least 17
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`bits in length upwardsto at least 64 bits in length. The mini-
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`mum of 17 bits may be due to the use of a 16-bit CRC. The
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`system then determines whether encryption has been enabled
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`for that gap at query 330. If encryption has been enabled, the
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`4
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`system then complements every 8” bit until the beginning of
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`the next gap at act 340. The system performsthis method until
`it determinesthat it has reached the end of the data stream at
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`query 350.
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`Referring to FIG. 4, another embodimentof the disclosed
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`method is shown. The FPGA receives the encrypted data
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`stream from the external source at act 410. The system then
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`determines that if it has received the start of a gap at query
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`420. Ifthe system determinesit has received the start of a gap,
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`then the system determines whether the encryption was
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`enabled at query 430. If the encryption was enabled, the
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`system complementsevery 8” bit (or other n” bit ifa number
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`other than 8 was used) until the beginning of the next gap at
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`act 440. Act 440 in effect de-encrypts the data stream. The
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`system then determines whetherit has received the end ofthe
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`data stream at query 450. If the system determinesthat it has
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`received the end of the data stream, then the system config-
`ures the RAM and/or PROM of the FPGA with the de-en-
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`crypted data stream at act 460.
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`In another embodimentof the present invention, portions
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`of the data stream may be compressed andother portions of
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`the data stream may be encrypted, thereby further altering the
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`data stream and thus hindering those who may attempt to
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`reverse engineer the data stream.
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`In another embodimentof the present invention, random
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`bits maybe inserted into the gaps of the data stream to further
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`hinder those who may wish to reverse engineer the data
`stream.
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`While embodiments and applications of this invention
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`have been shown and described, it would be apparentto those
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`skilled in the art that many more modifications than men-
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`tioned aboveare possible without departing from the inven-
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`tive concepts herein. The invention, therefore, is not to be
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`restricted except
`in the spirit of the appended claims.
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`Althoughthe claimsrefer to sending the data stream to RAM
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`CELLS on the FPGA,those skilled in the art are aware that
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`the disclosed system also applies to those devices with other
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`memory devices located in the FPGA,including without limi-
`tation PROMs.
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`Whatis claimedis:
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`1. A methodfor encrypting a data stream used to program
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`a field programmable gate array comprising:
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`receiving said data stream wherein said data stream is a
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`string ofbits;
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`detecting a first gap in said data stream wherein saidfirst
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`gap is bits in said stream for an unused address in said
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`field programmable gate array;
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`determining whether encryption is enabled for said first
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`gap;
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`inserting an encryption identifier into said first gap identi-
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`fying whether encryption has been enabled;
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`encrypting bits in said stream of bits from a beginning of
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`said first gap a prespecified numberof bits at a time
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`utilizing a prespecified set of bits as a bit mask, wherein:
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`the encrypting is a loop comprising:
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`selecting a next prespecified number of bits from the
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`stream ofbits as a selectedset of bits;
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`toggling the specified set of bits from the selected set of
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`bits; and
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`repeating the selecting and the toggling until a second
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`gap in said stream for an unused address in said field
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`programmable gate array is encountered;
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`detecting the second gap;
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`ending encryption ofbits in said stream ofbits at a begin-
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`ning of said second gap in response to detecting said
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`second gap; and
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`20
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`25
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`30
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`35
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`40
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`45
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`Page 8 of 10
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`Page 8 of 10
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`

`

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`5
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`wherein the encrypting further comprise:
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`encrypting a first portion of bits in said first gap from said
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`begining ofsaid first gap responsive to a determination
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`that encrypting is enabled; and
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`compressing data in a second portion of said first gap
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`responsive to a determination that encrypting is not
`enabled.
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`2. The method of claim 1 further comprising:
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`detecting an endofsaid bits stream; and
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`ending encryption at the end ofsaid bit stream.
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`3. The method of claim 1 further comprising:
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`compressing data in said stream of bits in response to a
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`determination that encryption is not enabled.
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`4. The method of claim 1, wherein said step of encrypting
`
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`further comprises:
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`inserting random bitsinto said at least one gap.
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`5. The method of claim 1, wherein said step of encrypting
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`inserts non-random bits into said first gap.
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`6. A memory readable by a processing unit that stores
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`instructions for directing said processing unit for encrypting
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`bits in a data stream for programminga field programmable
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`gatearray, said instructions comprising instructionsto:
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`receive said data stream wherein said data stream is a string
`
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`ofbits;
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`detect a first gap in said data stream whereinsaidfirst gap
`is bits in said stream for an unused address in said field
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`programmable gate array;
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`determine whether encryption is enabledfor said first gap;
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`insert an encryption identifier into said first gap identifying
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`whether encryption has been enabled;
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`encryptbits in said stream of bits prom a beginning ofsaid
`
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`first gap a prespecified numberofbits at a time utilizing
`
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`
`a prespecified set of bits as a bit mask, wherein:
`
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`
`the encrypting is a loop comprising:
`
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`
`
`selecting a next prespecified number of bits prom the
`
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`
`stream ofbits as a selectedset of bits;
`
`
`
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`
`toggling the specified set of bits prom the selected set of
`
`
`bits; and
`
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`
`repeating the selecting and the toggling until a second
`
`
`gap is encountered;
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`
`detect the second gap, and
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`
`end encrypting of bits in said stream ofbits at a beginning
`of said second
`
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`gap in responseto detecting said second gap; and
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`wherein said instruction to encrypt further comprise:
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`encrypt a first portion of bits in said first gap from said
`
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`beginningofsaid first gap responsive to a determination
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`
`that encrypting is enabled, and
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`compress data in a secondportion ofsaidfirst gap respon-
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`
`sive to a determination that encrypting is not enabled.
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`7. The memory of claim 6 wherein said instructions further
`
`comprise:
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`instructions for directing said processing unitto:
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`detect an end ofsaid bits stream, and
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`end encryption at said end ofsaid bit stream.
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`
`8. The memory of claim 6 wherein said instructions to
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`
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`encrypt further comprise:
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`
`
`instructions for directing said processing unitto:
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`compress data in said stream ofbits in responseto a deter-
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`
`mination that encryption is not enabled.
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`
`
`9. The memory claim 6, wherein said instructions to
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`
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`encrypt further comprise:
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`
`instructions for directing said processing unitto:
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`insert random bits into said at least one gap.
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`10. The memory claim 6, wherein said instruction to
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`
`
`encrypt further comprise:
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`
`
`instructions directing said processing unit to:
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`insert non-random bitsinto saidfirst gap.
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`Page 9 of 10
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`US 7,558,967 B2
`
`
`6
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`
`
`11. An apparatus for encrypting a data stream used to
`
`
`
`
`
`
`program a field programmable gate array comprising:
`
`
`
`
`
`
`
`
`means for receiving said data stream wherein said data
`
`
`
`stream is a string ofbits;
`
`
`
`
`
`
`
`meansfor detecting a first gap in said data stream wherein
`
`
`
`
`
`
`
`
`said first gap is bits in said stream for an unused address
`
`
`
`
`
`
`in said field programmable gate array;
`
`
`
`
`
`means for determining whether encryption is enabled for
`
`
`
`said first gap;
`
`
`
`
`
`
`meansfor inserting an encryption identifier into saidfirst
`
`
`
`
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`
`
`gap identifying whether encryption has been enabled;
`
`
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`
`
`
`
`
`
`means for encrypting bits in said stream of bits from a
`
`
`
`
`
`
`
`beginningofsaidfirst gap a prespecified numberofbits
`
`
`
`
`
`
`
`at a timeutilizing a prespecified setof bits as a bit mask,
`
`
`
`
`
`wherein: the encrypting is a loop comprising:
`
`
`
`
`
`
`selecting a next prespecified number of bits from the
`
`
`
`
`
`stream ofbits as a selectedset of bits;
`
`
`
`
`
`
`
`
`
`toggling the specified set of bits from the selected set of
`bits and
`
`
`
`
`
`
`
`
`
`repeating the selecting and the toggling until a second
`
`
`gap is encountered;
`
`
`
`
`
`
`meansfor detecting the second gap; and
`
`
`
`
`
`
`
`meansfor ending encryptionofbits in said stream ofbits at
`
`
`
`
`
`
`
`a beginning of said second gap in responseto detecting
`
`
`
`
`said second gap; and
`
`
`
`
`
`
`wherein said meansfor encrypting further comprises:
`
`
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`
`
`
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`
`
`
`means for encrypting a first portion bits in said first gap
`
`
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`
`
`from said beginning of said first gap responsive to a
`
`
`
`
`
`determination that encrypting is enabled; and
`
`
`
`
`
`
`means for compressing data in a secondportionofsaidfirst
`
`
`
`
`
`gap responsive to a determination that encrypting is not
`enabled.
`
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`
`
`12. The apparatus of claim 11 further comprising:
`
`
`
`
`
`
`
`meansfor detecting an endofsaid bits stream; and
`
`
`
`
`
`
`
`means for ending encryption at the end ofsaid bit stream.
`
`
`
`
`
`
`13. The apparatus of claim 11 further comprising:
`
`
`
`
`
`means for compressing data in said to a determination that
`
`
`
`encryption is not enabled.
`
`
`
`
`
`
`
`
`14. The apparatus of claim 11, wherein said means for
`
`
`
`encrypting further comprises:
`
`
`
`
`
`
`
`
`meansfor inserting random bits into at least one gap.
`
`
`
`
`
`
`
`
`15. The apparatus of claim 11, wherein said means for
`
`
`
`encrypting further comprises:
`
`
`
`
`
`
`
`
`meansfor inserting non-random bits into said first gap.
`
`
`
`
`
`
`16. A methodfor decrypting a data stream used to program
`
`
`
`
`
`
`a field programmable gate array comprising:
`
`
`
`
`
`
`
`
`receiving said data stream wherein said data stream is a
`
`
`string ofbits;
`
`
`
`
`
`
`
`
`detecting a first gap in said data stream wherein saidfirst
`
`
`
`
`
`
`
`gap is bits in said stream for an unused address in said
`
`
`
`
`field programmable gate array;
`
`
`
`
`
`
`reading an encryption identifier in said first gap;
`
`
`
`
`
`determining whether encryption is enabled from said
`
`
`encryption identifier;
`
`
`
`
`
`
`
`decrypting bits in said stream of bits from a beginning of
`
`
`
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`said first gap responsive to a determination that encryp-
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`tion is enabled, wherein:
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`the decrypting is a loop comprising:
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`selecting a next prespecified number of bits from the
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`stream ofbits as a selectedset of bits;
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`toggling a prespecified setofbits from theselected set of
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`bits; and
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`repeating the selecting and the toggling until a second
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`gap is encountered;
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`20
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`25
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`35
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`45
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`55
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`60
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`65
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`Page 9 of 10
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`US 7,558,967 B2
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`7
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`5
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`detecting the second gap;
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`ending decryption ofbits in said stream of bits at a begin-
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`ning of said second gap in response to detecting said
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`second gap; and
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`wherein said step of decrypting further comprises:
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`decrypting a first portion of bits in said first gap from said
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`beginningofsaid first gap responsive to a determination
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`that encrypting is enabled; and
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`decompressing data in a second portion of said first gap
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`responsive to a determination that encrypting is not
`enabled.
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`17. The method of claim 16 further comprising:
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`detecting an endofsaid bits stream; and
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`ending decryption at the end ofsaid bit stream.
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`18. The method of claim 16 further comprising:
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`decompressing data in said first gap responsive to a deter-
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`mination that encryption is not enabled.
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`19. The method of claim 16, wherein said step of decrypt-
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`ing further comprises:
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`removing inserted random bits from at least one gap.
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`20. The method of claim 16, wherein said step of decrypt-
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`ing further comprises removing non-randombits inserted into
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`said first