US00584ATSTIA
`5,847,577
`(114) Patent Number:
`United States Patent 55
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`[45] Date of Patent:
`Trimberger
`*Dec. 8, 1998
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`[54] DRAM MEMORYCELL FOR
`PROGRAMMABLELOGIC DEVICES
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`[75]
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`Inventor: Stephen M. Trimberger, San Jose,
`Calif.
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`[73] Assignee: Xilinx, Inc., San Jose, Calif.
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`[*] Notice:
`The term of this patent shall not extend
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`beyond the expiration date of Pat. No.
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`5,581,198.
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`[21] Appl. No.: 758,286
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`[22]
`Filed:
`Nov. 1, 1996
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`Related U.S. Application Data
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`[63] Continuation-in-part of Ser. No. 394,092,Feb. 24, 1995, Pat.
`No. 5,581,198.
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`[51]
`Int. Cheee H03K 19/177; G11C 7/00
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`[52] U.S. Ch oe 326/38; 326/41; 365/228;
`711/106
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`[58] Field of Search 00... 326/38-40; 365/222,
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`365/228, 230.03, 230.05, 149; 711/100,
`106, 161-162
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`[56]
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`References Cited
`U.S. PATENT DOCUMENTS
`
`
`8/1993 Freeman .
`Re. 34,363
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`2/1975 Yamadaet al. oe eee 340/172.5
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`4,366,560 12/1982 McDermott et al
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`1/1987 Hartung oo... ee ceeeeee 364/200
`4,638,425
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`4,642,487
`2/1987 Carter .
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`
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`7/1987 Sakurai et al. oc. eeeee 365/222
`4,682,306
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`
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`11/1987 Carter ocecieccceenersensseeeees 305/94
`4,706,216
`
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`
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`6/1988 Hsieh un...
`we 365/203
`4,750,155
`
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`
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`6/1990 Matsumuraetal.
`.. 365/187
`4,935,896
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`5,051,887
`9/1991 Bergeret al. cee 364/200
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`2/1993 El Gamaletal. .
`5,187,393
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`5,270,967 12/1993 Moazzamiet al... 365/230.06
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`2/1994 Hollerbauer
`...... ee eeeeeeee 395/425
`5,283,885
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`12/1994 Wahlstrom ...... ce eeeeeseeeeeeeee 326/38
`5,375,086
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`5,450,608
`9/1995 Steele wu...
`.. 395/800
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`5,581,198 12/1996 Trimberger
`occ 326/39
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`1/1997 Freeman 0... eee eeeereeeeneeee 365/222
`5,594,698
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`OTHER PUBLICATIONS
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`R. Sedgewick, “Algorithms”, pp. 283-284, Addison—Wes-
`
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`ley, 1983.
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`R. Sedgewick, “Algorithms”, pp. 295-303, Addison—Wes-
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`ley, 1983.
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`J.F. Wakerly, “Digital Design Principles and Practices” pp.
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`34-44, Prentice Hall, 1990.
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`Bradley Felton and Neil Hastie, “2.6 Configuration Data
`
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`Verification and the Integrity Checking of SRAM-—based
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`FPGAs” GEC Plessey Semiconductors, FPGAs, W.R.
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`Moore & W. Luk(eds.), 1991, Abingdon EE&C Books, 15
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`Harcourt Way, Abingdon, OX14 INV, UK,pp. 54-60.
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`J.F. Wakerly, “Digital Design, Principles and Practices”, pp.
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`255-257, Prentice Hall, 1989.
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`“Semiconductor Memories”, B. Prince, 2nd Edition, pp.
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`31-39 and pp. 654-655, 1991.
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`Primary Examiner—Jon Santamauro
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`Attorney, Agent, or Firm—Anthony C. Murabito; Wagner
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`Murabito & Hao; Jeanette S. Harms
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`ABSTRACT
`[57]
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`A plurality of DRAM cells are used to store the state of the
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`programmable points in a programmable logical device
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`(e.g., a field programmable gate array or FPGA). An indi-
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`vidual DRAM cell is used in conjunction with each pro-
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`grammable interconnect point (PIP) within the FPGA to
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`hold a logical state indicating the connectivity state of the
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`PIP. During a refresh cycle, each DRAM memorycell is
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`loaded with its current logical state in order to maintain this
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`state within the PIP. An information store contains duplicate
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`data for each DRAM cell and this duplicate data is supplied
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`and read during the refresh cycle in order to provide each
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`DRAM cell with its proper logical state. In this manner, the
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`refresh cycle does not alter the logic configuration of its
`associated FPGA DRAM cell. The information store can be
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`a plurality of DRAM cells or the information store can be of
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`non-volatile memory,
`for instance,
`read only memory
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`(ROM), programmable ROM (PROM), erasable PROM
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`(EPROM), electrically erasable PROM (EEPROM), or of
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`non-volatile magnetic storage.
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`23 Claims, 5 Drawing Sheets
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`309
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`DATA
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`307
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`ERROR
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`DETECTION
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`AND CORRECTION
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`306
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`| FPGAWORD |350 310
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`a |
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`DECOMPRESSION|.329a
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`308 7
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`DATA
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`| DECRYPTION|32!
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`ALID
`Vv.
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`GENERATOR
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`REGISTER
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`DRAM
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`LIN
`ne ADDRESS
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`SEQUENCER
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`SHADOW
`ARRAY
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`Page 1 of 11
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`FLEX LOGIX EXHIBIT 1043
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`FLEX LOGIX EXHIBIT 1043
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`Page 1 of 11
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`U.S. Patent
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`Dec. 8, 1998
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`Sheet 1 of 5
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`5,847,577
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`DATA
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`100
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`ADDR
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`FIG. 1
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`PRIOR ART
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`DATA
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`co 200
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`ADDR
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`Page 2 of 11
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`Page 2 of 11
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`U.S. Patent
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`Dec. 8, 1998
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`Sheet 2 of 5
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`5,847,577
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`Page 3 of 11
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`Page 3 of 11
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`U.S. Patent
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`Dec. 8, 1998
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`Sheet 3 of 5
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`5,847,577
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`FIG. 5
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`U.S. Patent
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`Sheet 4 of 5
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`5,847,577
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`TO MUX 520
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`621
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`FIG.6b
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`620
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`FIG.6a 600
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`U.S. Patent
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`Dec. 8, 1998
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`Sheet 5 of 5
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`5,847,577
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`Yl 2
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`FIG. 7
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`Page 6 of 11
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`Page 6 of 11
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`RELATED PATENT APPLICATIONS
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`The present patent application is a continuation-in-part of
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`patent application Ser. No. 08/394,092 filed Feb. 24, 1995,
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`now USS. Pat. No. 5,581,198, entitled “Shadow DRAM for
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`Programmable Logic Devices,” by Stephen Trimberger, and
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`assigned to the assignee of the present invention.
`BACKGROUND OF THE INVENTION
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`includes an access PIP that either connects an interconnect
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`segment to an input pin or an output pin of the CLB.
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`Because the PIPs in the FPGA are programmable, any
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`given output pin of a CLB is connectable to any given input
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`pin of any other desired CLB. Thus, a specific FPGA
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`configuration having a desired function is created by
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`selected generation of control signals to configure the spe-
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`cific function of each CLB in an FPGA,together with
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`selected generation of control signals to configure the vari-
`ous PIPs that interconnect the CLBs within the FPGA.
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`Each PIP typically includes a single pass transistor(i.e.
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`effectively a switch). The state of conduction, i.e. whether
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`the switch is opened or closed, is controlled by application
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`of the control signals discussed aboveto a transistor control
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`terminal, e.g. a gate. The programmed state of each pass
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`transistor is typically latched by a storage device, such as a
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`static random access memory (SRAM)cell 100, illustrated
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`in FIG. 1. As shown in FIG. 1, a high signal ADDR on
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`address line 102 identifies the SRAM cell to be programmed
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`Description of the Related Art
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`by turning on an n-type passtransistor 104, thereby allowing
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`the desired memorycell state DATA to be transferred from
`2. A field programmable gate array (FPGA) is a program-
`the data line 101 to a latch 106. The state of the control
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`mable integrated circuit logic device that consists of a matrix
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`signal stored in the latch 106 determines whether a pass
`of configurable logic blocks (CLBs) embedded in a pro-
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`transistor (PIP) 109 is turned on oroff, thereby opening or
`grammable routing mesh. The combined programming of
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`closing a path in the FPGAinterconnect.
`the CLBs and routing network define the function of the
`device. The device is referred to as an FPGA because the
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`An SRAM cell
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`array of CLBscontained on the device can be configured and
`because the SRAM cell reliably maintains its value as long
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`interconnected by the user in the user’s facility by means of
`as poweris supplied. However, as shownin FIG. 1, because
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`special hardware and software.
`SRAM cell 100 includes two inverters 107/108 and a pass
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`transistor 104, SRAM cell 100 requires significant area on
`FPGAs are well known in the art. For example US. Pat.
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`an integrated circuit. Typically, the larger the area needed to
`No. RE 34,363, reissued on 31 Aug. 1993, describes a
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`implement a PIP, the fewer numberof PIPs that can be fit
`configurable logic array that includes a plurality of CLBs
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`onto an integrated circuit.
`interconnected in response to control signals to perform a
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`selected logic function, and in which a memoryis used to
`In view of the continuing trend to increase the numberof
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`store the particular data used to configure the CLBs. U.S.
`complex functions implemented by an FPGA,a needarises
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`Pat. No. 4,642,487, issued on 10 Feb. 1987, teaches a special
`for a method to reduce the size of the memorycells used to
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`interconnect circuit for interconnecting CLBs in an FPGA
`hold the program for the FPGA interconnect, thereby reduc-
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`without using the general
`interconnect structure of the
`ing the size of the FPGA and lowering its cost. Further,
`40
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`FPGA.USS. Pat. No. 4,706,216, issued on 10 Nov. 1987,
`smaller memory cells would permit larger capacity FPGAs
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`describes a configurable logic circuit that includes a config-
`to be built than were previously possible.
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`urable combinational logic element, a configurable storage
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`A dynamic random access memory (DRAM)cell, which
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`circuit, and a configurable output select logic circuit. U.S.
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`is much smaller than an SRAM cell, has previously not been
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`Pat. No. 4,750,155, issued on 7 June 1988, describes a five
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`used in FPGAs for a numberof reasons, including:
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`transistor memorycell for an FPGAthat can bereliably read
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`1. ADRAM cell is volatile and subject to alpha particle
`and written.
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`upsets that can change the state stored in the cell;
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`Each CLB can provide one or more of the functions
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`2. ADRAM mustbe periodically refreshed. Sensing the
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`provided by an AND gate, flip-flop, latch, inverter, NOR
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`DRAM cell, for example to refresh the cell, destroys
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`gate, exclusive OR gate, as well as combinations of these
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`the current value in the cell; and
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`functions to form more complex functions. The particular
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`3. Nearby signals, or signals running over a DRAM cell,
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`function performed by the CLB is determined by control
`can affect the contents of the cell.
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`signals that are applied to the CLB fromacontrol logic
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`circuit. The control logic circuit is formed integrally with,
`SUMMARYOF THE INVENTION
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`and as part of, the integrated circuit on which the CLBis
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`formed. If desired, control information can be stored and/or
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`In accordance with the present invention, a plurality of
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`generated outside ofthis integrated circuit and transmitted to
`DRAM cells are used to store the state of the programmable
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`the CLB. The actual set of control bits provided to each CLB
`points in a programmable logical device (e.g., a field pro-
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`on the integrated circuit depends upon the functionsthat the
`grammable gate array or FPGA). An individual DRAM cell
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`CLB and, more globally, the integrated circuit are to per-
`is used in conjunction with each programmable interconnect
`60
`form.
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`point (PIP) within the FPGAto holdalogicalstate indicating
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`Each CLB typically has a plurality of input and output
`the connectivity state of the PIP. In one embodiment, the
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`pins, and a set of programmable interconnect points (PIPs)
`information store is typically organized with the same num-
`ber of bits and wordsas there are FPGA DRAM cells within
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`for each input and output pin. The general interconnect
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`structure of the FPGA includes a plurality of interconnect
`the FPGA, e.g.
`there is a one-to-one correspondence
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`segments and a plurality of PIPs, wherein each interconnect
`between FPGA DRAM cells and the memorycells of the
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`segment is connected to one or more other interconnect
`information store. During a refresh cycle, each DRAM
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`segments by programming an associated PIP. An FPGA also
`memory cell is loaded with its current logical state in order
`
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`10
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`15
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`20
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`25
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`30
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`35
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`45
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`55
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`65
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`5,847,577
`
`
`
`
`1
`DRAM MEMORYCELL FOR
`
`
`
`
`PROGRAMMABLELOGIC DEVICES
`
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`1. Technical Field
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`The invention relates to a field programmablegate array,
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`and more particularly, to a shadow memory circuit that is
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`adapted to effect and maintain selected interconnection of
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`various logic and other elements in a field programmable
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`gate array.
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`3
`to maintain this state within the PIP. An information store
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`contains duplicate data for each DRAM cell and this dupli-
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`cate data is supplied and read during the refresh cycle in
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`order to provide each DRAM cell with its proper logical
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`state. In this manner, the refresh cycle does not alter the logic
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`configuration of its associated FPGA DRAM cell. The
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`information store can be a plurality of DRAM cells or the
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`information store can be of non-volatile memory,
`for
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`instance, read only memory (ROM), programmable ROM
`10
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`(PROM), erasable PROM (EPROM),electrically erasable
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`PROM (EEPROM), or of non-volatile magnetic storage.
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`The present invention significantly reduces area on the
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`FPGA compared to the area required by prior art memory
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`cells. Furthermore, the present invention also eliminates the
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`need for separate power and groundlines that support prior
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`art memory cells,
`thereby reducing the number of lines
`within the FPGA.
`
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a schematic diagram of a prior art SRAM
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`interconnect cell for an FPGA;
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`FIG. 2 is a schematic diagram of a DRAM interconnect
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`cell for an FPGA;
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`FIG. 3 is a block schematic diagram of a DRAM inter-
`connect control and refresh circuit for an FPGAin accor-
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`dance with the present invention;
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`FIG. 4 is a schematic diagram of a prior art
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`configuration circuit for an FPGA;
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`FIG. 5 is a schematic diagram of a logic configuration
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`circuit for an FPGA in accordance with the present inven-
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`tion;
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`FIGS. 6a and 6b are block schematic diagramsofalter-
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`native embodimentsof a portion of a storage elementcircuit
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`in accordance with the present invention;
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`FIG. 7 is a block schematic diagram of a logic configu-
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`ration circuit for an FPGA having a DRAM configuration
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`element in accordance with the present invention; and
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`FIG. 8 is a block schematic diagram of another logic
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`configuration circuit for an FPGA having a DRAM configu-
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`ration element in accordance with the present invention.
`DETAILED DESCRIPTION OF THE DRAWINGS
`
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`FIG. 2 illustrates a DRAM cell 200 for an FPGA in
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`accordance with the present invention. As with SRAM cell
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`100 (FIG. 1), a high signal ADDR on an address line 202
`
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`turns on a first pass transistor 204,
`thereby allowing a
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`DRAM cell 200 to be programmed. The state stored by
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`DRAM cell 200 is set by a signal DATA supplied overa data
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`line 201. Specifically, if both signals DATA and ADDRare
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`high, then a capacitor 206 begins to charge. The charge
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`stored in capacitor 206 sets the state of the control terminal
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`of the second passtransistor 209, thereby opening or closing
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`a path in the FPGA interconnect. Note that capacitor 206 is
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`implemented either as a separate circuit structure or as the
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`gate of second passtransistor 209.
`
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`The present invention significantly reduces area of the
`
`
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`FPGA compared to the area required by SRAM cell 100
`
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`
`because DRAM cell 200 stores state information in capaci-
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`tor 206 (one device), whereas SRAM cell 100 stores state
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`information in latch 106 (four devices). DRAM cell 200 also
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`eliminates the need for separate power and groundlines (not
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`shownin FIG. 1) that support SRAM cell 100 in the priorart,
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`thereby reducing the number of lines within the FPGA.
`
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`In accordance with the present invention, a plurality of
`DRAM cells are used to control the FPGA interconnect
`
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`logic
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`25
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`35
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`45
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`55
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`60
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`65
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`5,847,577
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`15
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`20
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`4
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`circuitry. Another information store (shadow memory) per-
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`forms a shadow memory function. The shadow memory can
`
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`be composedof volatile memorycells (e.g., DRAM cells) or
`
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`it can be composed of non-volatile memory cells. Example
`
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`non-volatile memory constitution of the shadow memory
`
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`
`
`includes read only memory (ROM), programmable ROM
`
`
`
`
`
`
`(PROM), erasable PROM (EPROM),electrically erasable
`
`
`
`
`
`PROM (EEPROM), or of non-volatile magnetic storage.
`
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`
`
`In one embodiment using DRAM asthe shadow memory,
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`the shadow memoryis typically organized with the same
`numberof bits and words as there are DRAM interconnect
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`cells within the FPGA, i.e. there is a one-to-one correspon-
`dence between FPGA DRAM interconnectcells and shadow
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`DRAM memory cells.
`In this embodiment wherein the
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`shadow memory is DRAM memory, the shadow memory
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`cells are the same as DRAM cell 200 (FIG.2), with the
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`exception that pass transistor 209 is not required because the
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`shadow memory has no control function.
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`As is well knownto those in the art, while an SRAM cell
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`maintains the state of its contents as long as poweris
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`supplied, a DRAM cell needs periodic refreshing.
`FIG. 3 illustrates a DRAM interconnect control and
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`refresh circuit 300 for an FPGA according to the present
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`invention. A refresh cycle on a data word of the FPGA
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`interconnect DRAM includesthe following steps:
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`1. Initially, a conventional address sequencer and decoder
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`303 (hereinafter “sequencer”) address a particular por-
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`tion of the shadow memory 301. In one embodiment
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`where the shadow memory is DRAM,the sequencer
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`and decoder 303 pulls one shadow memoryaddressline
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`302 high to select one word of a shadow memoryarray
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`301. The contents of shadow memoryarray 301 for the
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`current data word are sensed by a conventional sense
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`circuit 308, and read into a data register 309.
`In
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`embodiments of the present
`invention where the
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`shadow memory 301is non-volatile, the conventional
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`sense amplifier 308 can be eliminated and data can be
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`written directly from memory 301 to the data register
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`309. If shadow memory can be read non-destructively,
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`the write back circuitry including buffer 306 can be
`eliminated.
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`2. The contents of data register 309 are written back into
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`the shadow memory array 301 viatri-state buffer 306
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`(after passing through error detection and correction
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`circuit 307) and these contents are also written into the
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`FPGA interconnect and logic DRAM (hereinafter
`
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`FPGA DRAM)310 via data line 311 to refresh FPGA
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`DRAM 310. Shadow memory array 301 and FPGA
`
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`DRAM 310 are written to simultaneously,
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`independently, or at different intervals, as desired. A
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`preferred embodiment of the present invention pro-
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`vides a simultaneous shadow memoryandinterconnect
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`DRAM refresh sequence.
`In that embodiment,
`
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`sequencer 303 provides address information via lines
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`302 to shadow memoryarray 301 andvia lines 312 to
`FPGA DRAM 310.
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`3. Alow DATA VALIDsignal generated by a data valid
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`circuit 305 (data valid generatorcircuit), is provided to
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`ANDgates 304 to force the signals on bus 312 low. The
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`DATA VALIDsignal is generated to remain low until
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`the data read out of shadow memory array 301 is
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`latched into data register 309, provided to error detec-
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`tion and correction circuit 307, and propagated to the
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`memory cells in FPGA DRAM 310. A high DATA
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`VALID signal, provided totri-state buffer 306, allows
`
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`the transfer of the data held in data register 309 back
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`Page 8 of 11
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`Page 8 of 11
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`

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`5,847,577
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`10
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`5
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`into shadow memory array 301. In one embodiment,
`
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`the DATA VALIDsignal is asserted in a predetermined
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`delay period after the current address is presented over
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`bus 312 by the address sequencer and decoder 303.
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`Thus, the generation of the DATA VALID signal takes
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`into consideration all internal timing and propagation con-
`siderations of the FPGA before FPGA DRAM 310 is
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`refreshed, thereby ensuring that correct data is available to
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`FPGA DRAM 310. The DATA VALID signal ensures that
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`valid data is present over bus 321a during the write cycle
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`when the FPGA DRAM 310 is updated so that transient
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`garbageor invalid data is not written into the FPGA DRAM
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`310. In this manner, the contents of FPGA DRAM 310 are
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`not destroyed during the interval whenthe cell is written. A
`15
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`high DATA VALID signal,
`indicating valid data, and a
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`corresponding high signal on one of address lines 302 forces
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`the output signal from ANDgates 304 (i.e. on line 312) high,
`
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`thereby triggering a refresh cycle and allowing data to be
`
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`written into the cells of FPGA DRAM 310. Note that a high
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`DATA VALIDsignal, provided to tri-state buffer 306, per-
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`mits transfer of the data held in data register 309 to shadow
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`memory array 301. It is appreciated that data valid to 306
`and 304 need not be simultaneous.
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`4. Sequencer 303 which controls the refresh sequence
`
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`continuously cycles throughall addressesto ensure that
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`all DRAM interconnect cells are regularly refreshed.
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`It is appreciated that the shadow memoryarray 301, the
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`address sequencer 303, the data valid circuit 305 and gate
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`304 can be located off-chip in a separate die or device from
`30
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`the FPGA integrated circuit device that contains the FPGA
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`DRAM 310. In this case,
`the shadow memory array is
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`interfaced to communicate the duplicate data to a receiving
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`circuit (e.g., 308) during a refresh cycle. A numberof well
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`known communication interface protocols and circuitry can
`
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`be used for this alternative embodiment of the present
`
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`
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`invention. In this alternative embodiment,
`the data valid
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`circuit 305 operates as discussed above and the address
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`sequencer and decoder 303 address the shared memoryarray
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`301 as discussed above. Gate 304 presents the address to
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`receiving circuit 310 to refresh the FPGA DRAM 310 during
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`a valid period of the refresh cycle.
`
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`
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`invention, DRAM
`In one embodiment of the present
`interconnect control and refresh circuit 300 includesan error
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`detection and correction circuit 307 that minimizes data
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`integrity problems associated with alpha particle hits and
`
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`other data disturbances of shadow memoryarray 301. Fur-
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`ther description of the codes associated with this conven-
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`tional circuit is provided in “Digital Design Principles and
`
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`
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`
`
`
`Practices” by J.F. Wakerly, pages 34-44, 1990, which is
`
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`
`
`herein incorporated by reference. Although shown in con-
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`
`
`nection with the preferred embodiment of the invention,
`error detection and correction circuit 37 is considered
`
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`
`optional.
`
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`
`In contrast to FRGA DRAM 310 which providesa single
`
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`
`
`
`storage cell at each PIP and therefore is distributed through-
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`out the FPGA, shadow memoryarray 301 is preferably a
`
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`standard DRAM array and can therefore be very dense.
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`Shadow memory array 301 is typically built far enough
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`awayfrom linesthat carry currents sufficiently high to cause
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`DRAM storage problems. In this manner, the contents of
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`shadow memory array 301 are not disturbed by any FPGA
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`signal, thereby avoiding upset problems and other related
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`interference that might affect the cells of shadow memory
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`In this way, any errors introduced into the
`array 301.
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`memory cells of FPGA DRAM 310, for example by the
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`routing of various signals through the general interconnect
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`of the FPGA,are readily corrected by shadow memoryarray
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`301 during the next refresh cycle. In another embodiment,
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`each cell of the shadow memory array is built at the same
`location as its associated FPGA DRAM interconnect cell.
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`One embodiment of the shadow memoryarray includes
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`DRAM cells because of the compact size of such arrays. In
`one embodiment of an FPGA in accordance with the
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`invention, a shadow memory array having approximately
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`100,000cells is used. In other embodiments of the invention,
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`the shadow memory array uses other technologies. For
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`example, the shadow memory array could be an SRAM,
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`EPROM, EEPROM,flash EPROM,or ferroelectric array.
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`Although the shadow memoryarray is integrated onto the
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`same die as the FPGA in typical embodiments of the
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`invention, other shadow memoryarrays are fabricated on a
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`separate die. Finally,
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`present invention, a shadow memory is provided for use
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`with standard SRAM interconnect cells, such that these
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`interconnect cells are periodically refreshed to repair any
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`errors that resulted from factors such as power surges.
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`It is appreciated that more than one read and write cycle
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`can be applied to shadow memory301to collect enoughbits
`for one full FPGA DRAM address.
`In this alternative
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`embodiment, a second register 350 is used to store the full
`FPGA DRAM word.
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`The present invention is also intended for other applica-
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`tions in programmable or configurable devices in which a
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`logic state is set and stored. For example, FIG. 4 illustrates
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`a prior art logic configuration circuit that includes a plurality
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`of storage elements 400 whichstore logic states A, B, C and
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`D. These logic states, which determine the logic function
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`performed by the circuit, are provided to a multiplexer 401
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`via lines 402, 403, 404 and 405. Multiplexer 401 consists of
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`a first set of transistors 410, 411, 412, 413 that are controlled
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`by signal I1 provided on a first input line 407, and a second
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`set of transistors 414, 415 that are controlled by a signal I2
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`provided on a second input line 408. The signals on first
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`input line 407 and secondinput line 408 select the logic state
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`bit that is the function value on outputline 406. For example,
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`assume logic states B, C, and D are a logic “0” and logic
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`state A is a logic “1”. Multiplexer 401 selects logic state A
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`whenboth signals I1 and I2 are a logic “1”, the function of
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`the circuit is an AND gate because the function produces a
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`logic “1” only when both inputs are a logic “1”, and the
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`circuit produces a logic “0”if either of the signals provided
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`on input lines 407, 408 is otherwise.
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`Prior art storage elements 400 are typically SRAM cells
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`and, as such, are relatively stable. However, as discussed
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`above, SRAM cells require considerable area on an inte-
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`grated circuit.
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`As is known in the art, a DRAM cell cannot source a
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`current for a logic operation because drawing current from
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`the DRAM cell depletes the charge stored in the cell and thus
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`may change the state of the cell. Thus,.a DRAM cell may
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`only store a logic state. Therefore, if a DRAM cell is used
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`for storage cell 400, the contents of the DRAM cell are lost
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`whenthe cell is sensed. For example, a DRAM cell cannot
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`drive an input line of a steering logic multiplexer and s