M-0045 US
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`VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS
`
`Venkat Konda
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`CROSS REFERENCE TO RELATED APPLICATIONS
`
`This application is related to and incorporates by reference in its entirety the U.S.
`
`Provisional Patent Application Docket No. M-0037USentitled "FULLY CONNECTED
`
`GENERALIZED MULTI-STAGE NETWORKS"by Venkat Konda assigned to the same
`
`assignee as the current application, filed concurrently.
`
`10
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`This application is related to and incorporates by referencein its entirety the U.S.
`
`Provisional Patent Application Docket No. M-0038USentitled "FULLY CONNECTED
`
`GENERALIZED BUTTERFLY FAT TREE NETWORKS"by Venkat Konda assigned
`
`to the same assigneeas the current application, filed concurrently.
`
`This application is related to and incorporates by reference in its entirety the U.S.
`
`15
`
`Provisional Patent Application Docket No. M-0039USentitled "FULLY CONNECTED
`
`GENERALIZED REARRANGEABLY NONBLOCKING MULTI-LINK MULTI-
`
`STAGE NETWORKS" by Venkat Kondaassigned to the same assignee as the current
`
`application, filed concurrently.
`
`This application is related to and incorporates by referencein its entirety the U.S.
`
`20
`
`Provisional Patent Application Docket No. M-0040USentitled "FULLY CONNECTED
`
`GENERALIZED MULTI-LINK BUTTERFLY FAT TREE NETWORKS"by Venkat
`
`Kondaassigned to the same assigneeas the current application, filed concurrently.
`
`This application is related to and incorporates by reference in its entirety the U.S.
`
`Provisional Patent Application Docket No. M-0041USentitled "FULLY CONNECTED
`
`25
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`GENERALIZED FOLDED MULTI-STAGE NETWORKS"by Venkat Kondaassigned
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`to the same assigneeas the current application, filed concurrently.
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`FLEX LOGIX EXHIBIT 1026
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`FLEX LOGIX EXHIBIT 1026
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`M-0045 US
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`This application is related to and incorporates by referencein its entirety the U.S.
`
`Provisional Patent Application Docket No. M-0042USentitled "FULLY CONNECTED
`
`GENERALIZED STRICTLY NONBLOCKING MULTI-LINK MULTI-STAGE
`
`NETWORKS"by Venkat Kondaassigned to the same assignee as the current application,
`
`filed concurrently.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1A is a diagram 100A of an exemplary symmetrical multi-link multi-stage
`
`network V1nine (N.d,5) having inverse Benes connection topology of nine stages with
`
`N = 32, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`10
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention.
`
`FIG. 1B is a diagram 100B of the equivalent symmetrical folded multi-link multi-
`
`stage network Vai mtn (N.d,s) of the network 100A shownin FIG, 1A, having inverse
`
`Benes connection topology of five stages with N = 32, d= 2 and s=2, strictly nonblocking
`
`15
`
`network for unicast connections and rearrangeably nonblocking network for arbitrary fan-
`
`out multicast connections, in accordance with the invention.
`
`FIG. 1C is a diagram 100C layout of the network V
`
`jfold—miink
`
`(N,d,s) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links belonging with in each block
`
`only.
`
`20
`
`FIG. 1D is a diagram 100D layout of the network Viiining (Nsd,5) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links ML(1,i) for i = [1, 64] and
`
`ML(8,1) for i = [1,64].
`
`0.
`FIG. 1E is a diagram 100E layoutof the network V,
`
`d_mine (> d,5) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links ML(2.i) for 1 = [1, 64] and
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`25
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`ML(7,1) for i = [1,64].
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`FIG. 1F is a diagram 100F layout of the network V,01ia_mtine (N,d,5) shown in FIG.
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`1B, in one embodiment, illustrating the connection links ML(3.i) for i = [1, 64] and
`
`ML(6,i) for 1 = [1,64].
`
`FIG. 1G is a diagram 100G layout of the network V,0.id—mlink (N, d, S) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links ML(4,1) for 1 = [1, 64] and
`
`ML(S5,1) for i = [1,64].
`
`FIG. 1H is a diagram 100H layoutof a network V,O01it_-miine (N»d,8) where N = 128,
`
`d = 2, and s = 2, in one embodiment, illustrating the connection links belonging with in
`
`each block only.
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`10
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`FIG. 11 is a diagram 100I detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V(N,d,s) or V,,(N,d,5).
`
`FIG. 1J is a diagram 100J detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`15
`
`when the layout 100C is implementing V(N,d,s) or Vrota (N,d,s).
`
`FIG. 1K is a diagram 100K detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V(N,d,s) or Vona (N,d,s).
`
`FIG. 1K1 is a diagram 100M1 detailed connections of BLOCK 1_2 in the network
`
`20
`
`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V(N,d,s) or Viota (N,d,s) fors=1.
`
`FIG. 1L is a diagram 100L detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V(N,d,s) or Vi4(N,d,5).
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`M-0045 US
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`FIG. 1L1 is a diagram 100L1 detailed connections of BLOCK 1_2 in the network
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`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V(N,d,s) or V,,(N,d,s) fors = 1.
`
`FIG, 2A1 is a diagram 200A1 of an exemplary symmetrical multi-link multi-stage
`
`network Vp14nine (N.d.5) having inverse Benes connection topology of one stage with N
`
`= 2, d = 2 and s=2,
`
`strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention. FIG. 2A2 is a diagram 200A2 of the equivalent
`
`symmetrical folded multi-link multi-stage network Voyiui(N,d,s) of the network
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`10
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`200A1 shown in FIG. 2A1, having inverse Benes connection topology of one stage with
`
`N = 2, d = 2 and s=2, strictly nonblocking network for unicast connections and
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`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention. FIG. 2A3 is a diagram 200A3 layout of the network
`
`Vin
`
`ia—_mtine (N.,5) shown in FIG, 2A2, in one embodiment,illustrating all the connection
`
`15
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`links.
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`FIG. 2B1 is a diagram 200B1 of an exemplary symmetrical multi-link multi-stage
`
`network Viimine (Nd, 5) having inverse Benes connection topology of one stage with N
`
`= 4, d = 2 and s=2,
`
`strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
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`20
`
`accordance with the invention. FIG. 2B2 is a diagram 200B2 of the equivalent
`
`symmetrical folded multi-link multi-stage network V,ntd_mtine’N,d,8) Of the network
`
`200B1 shown in FIG. 2B1, having inverse Benes connection topology of one stage with
`
`N = 4, d = 2 and s=2,strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
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`25
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`accordance with the invention. FIG. 2B3 is a diagram 200B3 layout of the network
`
`Vjotd-mint (N,d,s) shown in FIG. 2B2, in one embodiment, illustrating the connection
`
`links belonging with in each block only. FIG. 2B4 is a diagram 200B4 layout of the
`
`network Vigmine (N.d.5)
`
`shown in FIG. 2B2,
`
`in one embodiment,
`
`illustrating the
`
`connection links ML(1,i) for i = [1, 8] and ML(2,1i) for 1 = [1,8].
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`4.
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`FIG. 2C11 is a diagram 200C11 of an exemplary symmetrical multi-link multi-
`
`stage network Viuigmiine(N.d,5) having inverse Benes connection topology of one stage
`
`with N = 8, d = 2 and s=2,strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention. FIG. 2C12 is a diagram 200C12 of the equivalent
`
`symmetrical folded multi-link multi-stage network Voi4ink (N,d,s) of the network
`
`200C11 shown in FIG. 2C11, having inverse Benes connection topology of one stage
`
`with N = 8, d = 2 and s=2,strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`10
`
`accordance with the invention.
`
`FIG, 2C21 is a diagram 200C21 layoutof the network Voinine(N,d,5) shown in
`
`FIG, 2C12, in one embodiment, illustrating the connection links belonging with in each
`
`block only. FIG. 2C22 is a diagram 200C22 layout of the network Viiining (N.d,5)
`
`shown in FIG. 2C12, in one embodiment, illustrating the connection links ML(1,i) for i =
`
`15
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`[1, 16] and ML(4,i) for i = [1,16]. FIG. 2C23 is a diagram 200C23 layout of the network
`
`Vfold-mine (Nd, 5) shown in FIG. 2C12, in one embodiment, illustrating the connection
`
`links ML(2,i) fori = [1, 16] and ML@,i) for i = [1,16].
`
`FIG, 2D1 is a diagram 200D1 of an exemplary symmetrical multi-link multi-stage
`
`network Visnine (N.d,5) having inverse Benes connection topology of one stage with N
`
`= 16, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention.
`
`FIG, 2D2 is a diagram 200D2 of the equivalent symmetrical folded multi-link
`
`multi-stage network Vpining (N.d,5) of the network 200D1 shownin FIG. 2D1, having
`
`25
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`inverse Benes connection topology of one stage with N = 16, d = 2 and s=2,strictly
`
`nonblocking network for unicast connections and rearrangeably nonblocking network for
`
`arbitrary fan-out multicast connections, in accordance with the invention.
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`FIG, 2D3 is a diagram 200D3 layout of the network V,,fold—mlink (N, d,s) shown in
`
`FIG, 2D2, in one embodiment, illustrating the connection links belonging with in each
`
`block only.
`
`FIG, 2D4 is a diagram 200D4 layout of the network V,,fold—mlink (N, d, s) shown in
`
`FIG, 2D2, in one embodiment,illustrating the connection links ML(1,i) fori = [1, 32] and
`
`ML(6,i) for i = [1,32].
`
`FIG. 2D5 is a diagram 200D5 layout of the network Vigigiine(Nd,s) shown in
`
`FIG. 2D2, in one embodiment, illustrating the connection links ML(2,1) for i = [1, 32] and
`
`ML(5,1) for 1 = [1,32].
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`10
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`FIG, 2D6is a diagram 200D6 layout of the network Via.juin (N.d@,5) shown in
`
`FIG. 2D2, in one embodiment, illustrating the connection links ML(3,1) fori = [1, 32] and
`
`ML(4,i) for i = [1,32].
`
`FIG. 3A is a diagram 300A of an exemplary symmetrical multi-link multi-stage
`
`network V,.,,(N,d,s) having inverse Benes connection topology of nine stages with N =
`
`15
`
`32, d= 2 and s=2, strictly nonblocking network for unicast connections and rearrangeably
`
`nonblocking network for arbitrary fan-out multicast connections, in accordance with the
`
`invention.
`
`FIG. 3B is a diagram 300B of the equivalent symmetrical folded multi-link multi-
`
`cube
`stage network V,_,,(N.d,s) of the network 300A shown in FIG. 3A, having inverse
`
`20
`
`Benes connection topology of five stages with N = 32, d= 2 and s=2,strictly nonblocking
`
`network for unicast connections and rearrangeably nonblocking network for arbitrary fan-
`
`out multicast connections, in accordance with the invention.
`
`cube
`FIG. 3C is a diagram 300C layout of the network V,._,.(N.d,s) shown in FIG.
`
`3B, in one embodiment, illustrating the connection links belonging with in each block
`
`only.
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`cube
`FIG. 3D is a diagram 100D layout of the network Y,_,,.(NV,d,s) shown in FIG.
`
`3B, in one embodiment, illustrating the connection links ML(1.1) for i = [1, 64] and
`
`ML(8,i) for i = [1,64].
`
`cube
`FIG. 3E is a diagram 300E layout of the network V,_,.(N,d,s) shown in FIG.
`
`3B, in one embodiment, illustrating the connection links ML(2,1) for i = [1, 64] and
`
`ML(7,i) for i = [1,64].
`
`cube
`FIG. 3F is a diagram 300F layout of the network V,_,,(V.d,s) shown in FIG.3B,
`
`in one embodiment, illustrating the connection links ML(3,i) for i = [1, 64] and ML(6,1)
`
`for i = [1,64].
`
`10
`
`cube
`FIG. 3G is a diagram 300G layout of the network V,_,,.(NV,d,s) shown in FIG.
`
`3B, in one embodiment, illustrating the connection links ML(4,i) for 1 = [1, 64] and
`
`ML(5,i) for i = [1,64].
`
`cube
`FIG. 3H is a diagram 300H layout of a network V,__,.(N,d,s) where N = 128, d=
`
`2, and s = 2, in one embodiment, illustrating the connection links belonging with in each
`
`15
`
`block only.
`
`FIG. 4A is a diagram 400A layout of the network Vijmin (N.d,5) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links belonging with in each
`
`block only.
`
`0.
`FIG. 4B is a diagram 400B layout of the network V,
`
`td_miine CN >4,8) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links ML(1.i) for 1 = [1, 64] and
`
`ML(8,i) for i = [1,64].
`
`FIG. 4C is a diagram 400C layout of the network Vii4iniin.(N.d,5) shown in FIG.
`
`4C, in one embodiment, illustrating the connection links ML(2,i) for 1 = [1, 64] and
`
`ML(7,i) for i = [1,64].
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`FIG. 4D is a diagram 400D layout of the network V,‘old—mlink (N,d,s) shown in
`
`FIG, 4D, in one embodiment,illustrating the connection links ML(3,1) for i = [1, 64] and
`
`ML(6,i) for i = [1,64].
`
`FIG. 4E is a diagram 400E layoutof the network V,,ntd—miineNV» 4,5) Shown in FIG.
`
`4E, in one embodiment, illustrating the connection links ML(4,1) for i = [1, 64] and
`
`ML(5,i) for i = [1,64].
`
`FIG. 4C1 is a diagram 400C1 layout of the network Vioigomine(N.d@,5) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links belonging with in each
`
`block only.
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`10
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`DETAILED DESCRIPTION OF THE INVENTION
`
`The present invention is concerned with the VLSI layouts of arbitrarily large
`
`switching networks for broadcast, unicast and multicast connections. Particularly
`
`switching networks considered in the current invention include: generalized multi-stage
`
`15
`
`networks V(N,,N,,d,s), generalized folded multi-stage networks Viota (N,,N,,d,5),
`
`generalized butterfly fat tree networks Vo (N,.N,.d,5), generalized multi-link multi-
`
`stage networks V,,,.(N,,N,,d,5), generalized folded multi-link multi-stage networks
`
`Vinta_mline (N,,N>.d,5), generalized multi-link butterfly fat tree networks
`
`m
`V linkbf (N,,N,,d,s), and generalized hypercube networks V,
`
`cube
`
`(N,,N,,d,5) fors =
`
`20
`
`1,2,3 or any numberin general.
`
`Efficient VLSI layout of networks on a semiconductor chip are very important
`
`and greatly influence many important design parameters such as the area taken up bythe
`
`network on the chip, total numberof wires, length of the wires, latency of the signals,
`
`capacitance and hence the maximum clock speed of operation. Some networks maynot
`
`even be implemented practically on a chip due to the lack ofefficient layouts. The
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`different varieties of multi-stage networks described above have not been implemented
`
`previously on the semiconductor chips efficiently. For example in Field Programmable
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`-8-
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`Gate Array (FPGA)designs, multi-stage networks described in the current invention have
`
`not been successfully implemented primarily due to the lack of efficient VLSI layouts.
`
`Current commercial FPGA products such as Xilinx Vertex, Altera’s Stratix implement
`
`island-style architecture using mesh and segmented meshrouting interconnects using
`
`either full crossbars or sparse crossbars. These routing interconnects consumelarge
`
`silicon area for crosspoints, long wires, large signal propagation delay and hence
`
`consumelot of power.
`
`The current invention discloses the VLSI layouts of numerous types of multi-
`
`stage networks which are very efficient. Moreover they can be embedded on to mesh and
`
`10
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`segmented meshrouting interconnects of current commercial FPGA products. The VLSI
`
`layouts disclosed in the current invention are applicable to including the numerous
`
`generalized multi-stage networks disclosed in the following provisional patent
`
`applications, filed concurrently:
`
`1) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`15
`
`unicast for generalized multi-stage networks V(N,, N,.d,s5) with numerous connection
`
`topologies and the scheduling methods are described in detail in U.S. Provisional Patent
`
`Application, Attorney Docket No. M-0037 USthatis incorporated by reference above.
`
`2) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized butterfly fat tree networks V,,(N,,N.,,d,5) with numerous
`
`20
`
`connection topologies and the scheduling methodsare described in detail in U.S.
`
`Provisional Patent Application, Attorney Docket No. M-0038 USthat is incorporated by
`
`reference above.
`
`3) Rearrangeably nonblocking for arbitrary fan-out multicast and unicast, and
`
`strictly nonblocking for unicast for generalized multi-link multi-stage networks
`
`25
`
`Vine (N1»N>,d,5) and generalized folded multi-link multi-stage networks
`
`Vfold—miink (N,,N>,d,8) with numerous connection topologies and the scheduling methods
`
`are described in detail in U.S. Provisional Patent Application, Attorney Docket No. M-
`
`0039 USthatis incorporated by reference above.
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`4) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized multi-link butterflyfat tree networks V,,j..¢(N,,N2,d,5) with
`
`numerous connection topologies and the scheduling methods are described in detail in
`
`U.S. Provisional Patent Application, Attorney Docket No. M-0040 USthatis
`
`incorporated by reference above.
`
`5) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized folded multi-stage networks V,,,,(N,,N,,d,5) with numerous
`
`connection topologies and the scheduling methods are described in detail] in U.S.
`
`Provisional Patent Application, Attorney Docket No. M-0041 USthat is incorporated by
`
`10
`
`reference above.
`
`6) Strictly nonblocking for arbitrary fan-out multicast and unicast for generalized
`multi-link multi-stage networks V,THtine (N,,N.,d,8) and generalized folded multi-link
`
`multi-stage networks V,
`
`ia—_mtine (N,,N,,d,5) with numerous connection topologies and
`
`the scheduling methodsare described in detail in U.S. Provisional Patent Application,
`
`15
`
`Attorney Docket No. M-0042 USthat is incorporated by reference above.
`
`In addition the layouts of the current invention are also applicable to generalized
`
`multi-stage pyramid networks V,(N,,N,,d,s), generalized folded multi-stage pyramid
`
`networks Vfola-p (N,,N,.d,5), generalized butterfly fat pyramid networks
`
`Vip (NN, d,s), generalized multi-link multi-stage pyramid networks
`
`20
`
`Vntint_p (N1.N,,d,5), generalized folded multi-link multi-stage pyramid networks
`
`Vfold—mlink-p (N,,N,,d,5), generalized multi-link butterfly fat pyramid networks
`
`Mn
`V Link-bfp (N,,N,,d,s), and generalized hypercube networks V,
`
`cube
`
`(N,,N,,d,s5) fors=
`
`1,2,3 or any numberin general.
`
`Symmetric RNB generalized multi-link multi-stage network V,,,,,(V,,N>5,.d,5):
`
`25
`
`Referring to diagram 100A in FIG. 1A, in one embodiment, an exemplary
`
`generalized multi-link multi-stage network V,,,,,,(N,,N.,d,5) where N; = No = 32; d=
`
`2; and s = 2 with nine stages of one hundred and forty four switches for satisfying
`-10-
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`communication requests, such as setting up a telephone call or a data call, or a connection
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`between configurable logic blocks, between an input stage 110 and output stage 120 via
`
`middle stages 130, 140, 150, 160, 170, 180 and 190 is shown where input stage 110
`
`consists of sixteen, two by four switches IS1-IS16 and output stage 120 consists of
`
`sixteen, four by two switches OS1-OS16. And all the middle stages namely the middle
`
`stage 130 consists of sixteen, four by four switches MS(1,1) - MS(1,16), middle stage 140
`
`consists of sixteen, four by four switches MS(@,1) - MS(2,16), middle stage 150 consists
`
`of sixteen, four by four switches MS(3,1) - MS(3,16), middle stage 160 consists of
`
`sixteen, four by four switches MS(4,1) - MS(4,16), middle stage 170 consists of sixteen,
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`10
`
`four by four switches MS(5,1) - MS(5,16), middle stage 180 consists of sixteen, four by
`
`four switches MS(6,1) - MS(6,16), and middle stage 190 consists of sixteen, four by four
`
`switches MS(7,1) - MS(7,16).
`
`Asdisclosed in U.S. Provisional Patent Application, Attorney Docket No. M-0039
`
`USthat is incorporated by reference above, such a network can be operated in
`
`15
`
`rearrangeably non-blocking mannerfor arbitrary fan-out multicast connections and also
`
`can be operated in strictly non-blocking mannerfor unicast connections.
`
`In one embodimentof this network each of the input switches IS1-IS$4 and output
`
`switches OS1-OS4 are crossbar switches. The numberof switches of input stage 110 and
`
`of output stage 120 can be denoted in general with the variable = , where WN is the total
`
`numberofinlet links or outlet links. The number of middle switches in each middle stage
`
`is denoted by ] . The size ofeach input switch [S1-IS4 can be denoted in general with
`
`the notation d*2d and each output switch OS1-OS4can be denoted in general with the
`
`notation 2d *d. Likewise, the size of each switch in any of the middle stages can be
`
`denoted as 2d * 2d . A switch as used herein can be either a crossbar switch, or a
`
`25
`
`network of switches each of which in turn maybe a crossbar switch or a network of
`
`switches. A symmetric multi-stage network can be represented with the notation
`
`Vtine (IN, d,S), Where N represents the total numberofinlet links of all input switches
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`(for example the links IL1-IL32), d represents the inlet links of each input switch or
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`outlet links of each output switch, and s is the ratio of number of outgoing links from
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`each input switch to the inlet links of each input switch.
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`Eachofthe - input switches IS1 —IS16 are connected to exactly d switches in
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`middle stage 130 through twolinks each for a total of 2xd_ links (for example input
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`switch IS1 is connected to middle switch MS(1,1) through the links ML(1,1), ML(,2),
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`and also connected to middle switch MS(1,2) through the links ML(1,3) and ML(1,4)).
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`The middle links which connect switches in the same row in two successive middle
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`stages are called hereinafter straight middle links; and the middle links which connect
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`switches in different rows in two successive middle stages are called hereinafter cross
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`10
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`middle links. For example, the middle links ML(1,1) and ML(1,2) connect input switch
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`IS1 and middle switch MS(1,1), so middle links ML(1,1) and ML(1,2) are straight middle
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`links; where as the middle links ML(1,3) and ML(1,4) connect input switch ISI] and
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`middle switch MS(1,2), since input switch IS1 and middle switch MS(1,2) belong to two
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`different rows in diagram 100A of FIG. 1A, middle links ML(1,3) and ML(1,4) are cross
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`15
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`middle links.
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`Eachof the — middle switches MS(1,1) — MS(1,16) in the middle stage 130 are
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`connected from exactly d input switches through twolinks each for a total of 2Xd_ links
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`(for example the links ML(1,1) and ML(1,2) are connected to the middle switch MS(1,1)
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`from input switch IS1, and the links ML(1,7) and ML(1,8) are connected to the middle
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`20
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`switch MS(1,1) from input switch IS2) and also are connected to exactly d switches in
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`middle stage 140 through twolinks each for a total of 2xd_ links (for example the links
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`ML(2,1) and ML(2,2) are connected from middle switch MS(1,1) to middle switch
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`MS(2,1), and the links ML(2,3) and ML(2,4) are connected from middle switch MS(1,1)
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`to middle switch MS(2,3)).
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`25
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`Each of the - middle switches MS(2,1) — MS(2,16) in the middle stage 140 are
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`connected from exactly d input switches through twolinks each for a total of 2xd_ links
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`(for example the links ML(2,1) and ML(2,2) are connected to the middle switch MS(2,1)
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`from input switch MS(1,1), and the links ML(1,11) and ML(1,12) are connected to the
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`middle switch MS(2,1) from input switch MS(1,3)) and also are connected to exactly d
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`switches in middle stage 150 through twolinks each for a total of 2xd_ links (for
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`example the links ML(3,1) and ML(3,2) are connected from middle switch MS(2,1) to
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`middle switch MS(3,1), and the links ML(3,3) and ML(3,4) are connected from middle
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`switch MS(2,1) to middle switch MS(3,5)).
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`Eachof the = middle switches MS(3,1) — MS(3,16) in the middle stage 150 are
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`connected from exactly d input switches through twolinks each for a total of 2xd_ links
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`(for example the links ML(3,1) and ML(3,2) are connected to the middle switch MS(3,1)
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`from input switch MS(2,1), and the links ML(2,19) and ML(2,20) are connected to the
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`10
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`middle switch MS(3,1) from input switch MS(2,5)) and also are connected to exactly d
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`switches in middle stage 160 through twolinks each for a total of 2xd_ links (for
`
`example the links ML(4,1) and ML(4,2) are connected from middle switch MS(3,1) to
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`middle switch MS(4,1), and the links ML(4,3) and ML(4,4) are connected from middle
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`switch MS(3,1) to middle switch MS(4,9)).
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`15
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`Eachof the - middle switches MS(4,1) — MS(4,16) in the middle stage 160 are
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`connected from exactly d input switches through twolinks each for a total of 2xd_ links
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`(for example the links ML(4,1) and ML(4,2) are connected to the middle switch MS(4,1)
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`from input switch MS(3,1), and the links ML(4,35) and ML(4,36) are connected to the
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`middle switch MS(4,1) from input switch MS(3,9)) and also are connected to exactly d
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`switches in middle stage 170 through twolinks each for a total of 2d_links (for
`
`example the links ML(5,1) and ML(5,2) are connected from middle switch MS(4,1) to
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`middle switch MS(5,1), and the links ML(5,3) and ML(5,4) are connected from middle
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`switch MS(4,1) to middle switch MS(5,9)).
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`Eachof the - middle switches MS(5,1) — MS(5,16) in the middle stage 170 are
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`25
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`connected from exactly d input switches through twolinks each for a total of 2xd_ links
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`(for example the links ML(5,1) and ML(5,2) are connected to the middle switch MS(5,1)
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`from input switch MS(4,1), and the links ML(5,35) and ML(5,36) are connected to the
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`middle switch MS(5,1) from input switch MS(4,9)) and also are connected to exactly d
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`switches in middle stage 180 through two links each for a total of 2d_links (for
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`example the links ML(6,1) and ML(6,2) are connected from middle switch MS(5,1) to
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`middle switch MS(6,1), and the links ML(6,3) and ML(6,4) are connected from middle
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`switch MS(5,1) to middle switch MS(6,5)).
`
`Eachof the = middle switches MS(6,1) — MS(6,16) in the middle stage 180 are
`
`connected from exactly d input switches through twolinks each for a total of 2xd_ links
`
`(for example the links ML(6,1) and ML(6,2) are connected to the middle switch MS(6,1)
`
`from input switch MS(5,1), and the links ML(6,19) and ML(6,20) are connected to the
`
`middle switch MS(6,1) from input switch MS(5,5)) and also are connected to exactly d
`
`10
`switches in middle stage 190 through twolinks each for a total of 2d_links (for
`
`example the links ML(7,1) and ML(7,2) are connected from middle switch MS(6,1) to
`
`middle switch MS(7,1), and the links ML(7,3) and ML(7,4) are connected from middle
`
`switch MS(6,1) to middle switch MS(7,3)).
`
`Eachof the - middle switches MS(7,1) — MS(7,16) in the middle stage 190 are
`
`15
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`connected from exactly d input switches through twolinks each for a total of 2xd_ links
`
`(for example the links ML(7,1) and ML(7,2) are connected to the middle switch MS(7,1)
`
`from input switch MS(6,1), and the links ML(7,11) and ML(7,12) are connected to the
`
`middle switch MS(7,1) from input switch MS(6,3)) and also are connected to exactly d
`
`switches in middle stage 120 through twolinks each for a total of 2xd_ links (for
`
`example the links ML(8,1) and ML(8,2) are connected from middle switch MS(7,1) to
`
`middle switch MS(8,1), and the links ML(8,3) and ML(8,4) are connected from middle
`
`switch MS(7,1) to middle switch OS2).
`
`Eachofthe 77 middle switches OS1 — OS16 in the middle stage 120 are
`
`connected from exactly d input switches through twolinks each for a total of 2xd_ links
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`25
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`(for example the links ML(8,1) and ML(8,2) are connected to the output switch OS1 from
`
`input switch MS(7,1), and the links ML(8,7) and ML(7,8) are connected to the output
`
`switch OS1 from input switch MS(7,2)).
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`Finally the connection topology of the network 100A shown in FIG. 1A is known
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`to be back to back inverse Benes connection topology.
`
`Referring to diagram 100B in FIG. 1B, is a folded version of the multi-link multi-
`
`stage network 100A shown in FIG. 1A. The network 100B in FIG. 1B showsinput stage
`
`110 and output stage 120 are placed together. That is input switch IS1 and output switch
`
`OS1 are placed together, input switch IS2 and output switch OS2 are placed together, and
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`similarly input switch IS16 and output switch OS16 are placed together. All the right
`
`going middle links{i.e., inlet links IL1 — IL32 and middle links ML(1,1) - ML(1,64)}
`
`correspond to input switches IS1 - IS16, and all the left going middle links {i.e., middle
`
`10
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`links ML(8,1) - ML(8,64) and outlet links OL1-OL32} correspond to output switches
`
`OS1 - OS16.
`
`Middle stage 130 and middle stage 190 are placed together. That is middle
`
`switches MS(1,1) and MS(7,1) are placed together, middle switches MS(1,2) and
`
`MS(7,2) are placed together, and similarly middle switches MS(1,16) and MS(7,16) are
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`15
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`placed together. All the right going middle links {i.e., middle links ML(1,1) - ML(1,64)
`
`and middle links ML(2,1) - ML(2,64)} correspond to middle switches MS(1,1) —
`
`MS(1,16), and all the left going middle links {1.e., middle links ML(7,1) - ML(7,64) and
`
`middle links ML(8,1) and ML(8,64)} correspond to middle switches MS(7,1) —
`
`MS(7,16).
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`20
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`Middle stage 140 and middle stage 180 are placed together. That is middle
`
`switches MS(2,1) and MS(6,1) are placed together, middle switches MS(2,2) and
`
`MS(6,2) are placed together, and similarly middle switches MS(2,16) and MS(6,16) are
`
`placed together. All the right going middle links {i.e., middle links ML(2,1) - ML(2,64)
`
`and middle links ML(3,1) — ML(3,64)} correspond to middle switches MS(2,1) —
`
`MS(2,16), and all the left going middle links {i.e., middle links ML(6,1) - ML(6,64) and
`
`middle links ML(7,1) and ML(7,64)} correspond to middle switches MS(6,1) —
`
`MS6,16).
`
`Middle stage 150 and middle stage 170 are placed together. That is middle
`
`switches MS(3,1) and MS(5,1) are placed together, middle switches MS(3,2) and
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`30
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`MS(.,72) are placed together, and similarly middle switches MS(3,16) and MS(5,16) are
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`placed together. All the right going middle links {i.e., middle links ML(3,1) - ML(3,64)
`
`and middle links ML(4,1) — ML(4,64)} correspond to middle switches MS(3,1) —
`
`MS(3,16), and all the left going middle links {i.e., middle links ML(5,1) - ML(5,64) and
`
`middle links ML(6,1) and ML(6,64)} correspond to middle switches MS(5,1) —
`
`MSG, 16).
`
`Middle stage 160 is placed alone. All the right going middle links are the middle
`
`links ML(4,1) - ML(4,64) andall the left going middle links are middle links ML(5,1) -
`
`ML(5,64).
`
`In one embodiment, in the network 100B of FIG. 1B, the switches that are placed
`
`10
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`together are implemented as separate switches then the network 100Bis the generalized
`
`folded multi-link multi-stage network Voijuin (N,N,d,5) where N) = No = 32; d= 2;
`
`and s = 2 with nine stages as disclosed in U.S. Provisional Patent Application, Attorney
`
`Docket No. M-0039 USthat is incorporated by reference above. Thatis the switches that
`
`are placed together in input stage 110 and output stage 120 are implemented as a two by
`
`15
`
`four switch and a four by two switch. For example the switch input switch IS1 and output
`
`switch OS1 are placed together; so input switch IS1 is implemented as two by four switch
`
`with the inlet links IL1 and IL2 being the inputs of the input switch IS1 and middle links
`
`ML(1,1) — ML(1,4) being the outputs of the input switch IS1; and output switch OS1 is
`
`implemented as four by two switch with the middle links ML(8,1), ML(8,2), ML(8,7) and
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`20
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`ML(8,8) being the inputs of the output switch OS1 and outlet links OL1 — OL2 being the
`
`outputs of the output switch OS1. Similarly in this embodiment of network 100Ball the
`
`switches that are placed together in each middle stage are implemented as separate
`
`switches.
`
`Hypercube Topology layout schemes:
`
`25
`
`Referring to layout 100C