UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________________
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`FLEX LOGIX TECHNOLOGIES, INC.
`Petitioner
`
`v.
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`KONDA TECHNOLOGIES INC.
`Patent Owner
`
`____________________
`
`Patent No. 8,369,523 B2
`____________________
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`DECLARATION OF R. JACOB BAKER, PH.D., P.E.
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,369,523
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`Page 1 of 151
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`FLEX LOGIX EXHIBIT 1002
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`TABLE OF CONTENTS
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`I.
`INTRODUCTION .............................................................................. 1
`BACKGROUND AND QUALIFICATIONS ......................................... 1
`II.
`III. MATERIALS REVIEWED ................................................................. 5
`IV. PERSON OF ORDINARY SKILL IN THE ART.................................... 6
`V.
`TECHNICAL BACKGROUND ........................................................... 7
`A.
`Field-Programmable Gate Arrays (FPGAs) ................................... 8
`VI. OVERVIEW OF THE ’523 PATENT ................................................. 17
`VII. CLAIM CONSTRUCTION ............................................................... 25
`VIII. OVERVIEW OF THE PRIOR ART .................................................... 25
`A. Wong ..................................................................................... 25
`IX. THE PRIOR ART DISCLOSES Or Suggests ALL OF THE
`FEATURES OF CLAIMS 1, 15-18, 20-22, 32, and 47 OF THE ’523
`PATENT ......................................................................................... 30
`A. Wong Discloses the Features of Claims 1 and 20-22 ..................... 30
`1.
`Claim 1 ......................................................................... 32
`2.
`Claim 20 ..................................................................... 120
`3.
`Claim 21 ..................................................................... 122
`4.
`Claim 22 ..................................................................... 125
`B. Wong Discloses or Suggests the Features of Claims 15-18, 32,
`and 47 .................................................................................. 127
`1.
`Claim 15 ..................................................................... 127
`2.
`Claim 16 ..................................................................... 130
`3.
`Claim 17 ..................................................................... 135
`4.
`Claim 18 ..................................................................... 139
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`Claim 32 ..................................................................... 142
`5.
`Claim 47 ..................................................................... 142
`6.
`X. CONCLUSION .............................................................................. 148
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`I, R. Jacob Baker, Ph.D., P.E., declare as follows:
`
`I.
`
`INTRODUCTION
`I have been retained by Flex Logix, Inc. (“Petitioner”) as an
`1.
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`independent expert consultant in this proceeding before the United States Patent and
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`Trademark Office (“PTO”) regarding U.S. Patent No. 8,269,523 (“the ’523 patent”)
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`(Ex. 1001). 1 I have been asked to consider whether certain references disclose or
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`suggest the features recited in claims 1, 15-18, 20-22, 32, and 47 of the ’523 patent.
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`My opinions are set forth below.
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`2.
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`I am being compensated at a rate of $615/hour for my work in this
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`proceeding. My compensation is in no way contingent on the nature of my findings,
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`the presentation of my findings in testimony, or the outcome of this or any other
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`proceeding. I have no other interest in this proceeding.
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`II. BACKGROUND AND QUALIFICATIONS
`I presently serve as a Professor of Electrical and Computer Engineering
`3.
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`at the University of Nevada, Las Vegas (UNLV). All of my opinions stated in this
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`declaration are based on my own personal knowledge and professional judgment. In
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`1 Where appropriate, I refer to exhibits that I understand are to be attached to the
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`petition for Inter Partes Review of the ’523 patent.
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`1
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`forming my opinions, I have relied on my knowledge and experience in designing,
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`developing, researching, and teaching regarding circuit design and memory devices
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`referenced in this declaration.
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`4.
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`I am over 18 years of age and, if I am called upon to do so, I would be
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`competent to testify as to the matters set forth herein. I understand that a copy of
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`my current curriculum vitae, which details my education and professional and
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`academic experience, is being submitted by Petitioner. The following provides an
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`overview of some of my experience that is relevant to the matters set forth in this
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`declaration.
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`5.
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`I have been teaching electrical engineering at UNLV since 2012. Prior
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`to this position, I was a Professor of Electrical and Computer Engineering at Boise
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`State University from 2000. Prior to my position at Boise State University, I was an
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`Associate Professor Electrical Engineering between 1998 and 2000 and Assistant
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`Professor of Electrical Engineering between 1993 and 1998 at the University of
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`Idaho. I have been teaching electrical engineering since 1991.
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`6.
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`I received my Ph.D. in Electrical Engineering from the University of
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`Nevada, Reno in 1993. I also received a MS and BS in Electrical Engineering from
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`UNLV in 1988 and 1986, respectively.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`As described in my curriculum vitae, which I understand is being
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`7.
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`provided as Exhibit 1003, I am a licensed Professional Engineer in the state of Idaho
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`and have more than 30 years of experience, including extensive experience in circuit
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`designs for networks and communications including the design of modems, driver
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`circuits, phase- and delay-locked loops for PCI, USB, and DDR standard
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`specifications.
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`8.
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`I have taught courses in integrated circuit design (analog, digital,
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`mixed-signal, memory circuit design, etc.), linear circuits, microelectronics,
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`communication systems, and fiber optics. As a professor, I have been the main
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`advisor to nine Doctoral students and 79 Master’s students.
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`9.
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`I am the author of several books covering the area of integrated circuit
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`design including: DRAM Circuit Design: Fundamental and High-Speed Topics (two
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`editions), CMOS Circuit Design, Layout, and Simulation (four editions), and CMOS
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`Mixed-Signal Circuit Design (two editions). I have authored, and coauthored, more
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`than 100 papers and presentations in the areas of solid-state circuit design, the design
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`of field-programmable gate array (FPGA) data converters, and circuits used in
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`standard specification implementations including double data rate (DDR) for
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`communications. I am the named inventor on 151 granted U.S. patents in CMOS
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`integrated circuit designs including array topologies including flash memory and
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`3
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`DRAM. My textbook CMOS Circuit Design, Layout, and Simulation includes,
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`among other things, sections covering digital logic gates as well as phase- and delay-
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`locked loops for networking and communications.
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`10.
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`I have received numerous awards for my work, including the Frederick
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`Emmons Terman (the “Father of Silicon Valley”) Award. The Terman Award is
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`bestowed annually upon an outstanding young electrical/computer engineering
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`educator in recognition of the educator’s contributions to the profession.
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`11.
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`I am a Fellow of the IEEE for contributions to memory circuit design.
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`I have also received the IEEE Circuits and Systems Education Award (2011).
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`12.
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`I have received the President’s Research and Scholarship Award
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`(2005), Honored Faculty Member recognition (2003), and Outstanding Department
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`of Electrical Engineering Faculty recognition (2001), all from Boise State
`
`University. I have also received the Tau Beta Pi Outstanding Electrical and
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`Computer Engineering Professor award during my time at UNLV.
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`13.
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`I am not an attorney and offer no legal opinions, but in the course of
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`my work, I have had experience studying and analyzing patents and patent claims
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`from the perspective of a person skilled in the art.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`III. MATERIALS REVIEWED
`14. The opinions contained in this Declaration are based on the documents
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`I reviewed, my professional judgment, as well as my education, experience, and
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`knowledge regarding integrated circuits, including networks and switches used to
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`implement field-programmable gate arrays (FPGAs).
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`15.
`
`In forming my opinions expressed in this Declaration, I reviewed the
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`’523 patent (Ex. 1001); File History of the ’523 patent (Ex. 1004); PCT Publication
`
`No. WO2008/147928 (Ex. 1005); U.S. Patent No. 10,003,553 (Ex. 1006); Body of
`
`PCT Application No. PCT/US08/64605 As Filed (“the ’605 PCT”) (Ex. 1007); U.S.
`
`Patent No. 6,940,308 (“Wong”) (Ex. 1008); File History of U.S. Provisional
`
`Application No. 60/940,394 (Ex. 1026); U.S. Patent No. 3,358,269 (“Benes”) (Ex.
`
`1040); U.S. Patent No. 5,847,577 (“Trimberger”) (Ex. 1043); U.S. Patent No.
`
`7,558,967 (“Wong-967”) (Ex. 1044); U.S. Patent No. 4,874,971 (“Fletcher”) (Ex.
`
`1045); U.S. Patent No. 10,050,904 (Ex. 1046); and any other materials I refer to in
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`this Declaration in support of my opinions.
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`16. All of the opinions contained in this declaration are based on the
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`documents I reviewed and my knowledge and professional judgment. My opinions
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`have also been guided by my appreciation of how a person of ordinary skill in the
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`art would have understood the claims and the specification of the ’523 patent at the
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`5
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`time of the alleged invention, which I have been asked to initially consider was the
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`mid-to-late-2000s timeframe (including May 25, 2007, the filing date of U.S.
`
`Provisional Patent Application No. 60/940,394, which I understand is the earliest
`
`possible priority date for the ’523 patent.). My opinions reflect how one of ordinary
`
`skill in the art would have understood the ’523 patent, the prior art to the patent, and
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`the state of the art at the time of the alleged invention.
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`17. Based on my experience and expertise, it is my opinion that certain
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`references disclose or suggest the features recited in claims 1, 15-18, 20-22, 32, and
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`47 of the ’523 patent.
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`IV. PERSON OF ORDINARY SKILL IN THE ART
`I am familiar with the level of ordinary skill in the art with respect to
`18.
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`the alleged inventions of the ’523 patent as of what I understand is the earliest
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`possible priority date of May 25, 2007, which is the filing date of U.S. Provisional
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`Patent Application No. 60/940,394 to which the ’523 patent claims priority.
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`Specifically, based on my review of the ’523 patent, the technology, the educational
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`level and experience of active workers in the field, the types of problems faced by
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`workers in the field, the solutions found to those problems, the sophistication of the
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`technology in the field, and drawing on my own experience, I believe a person of
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`ordinary skill in the art would have had would have had a master’s degree in
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`electrical engineering or a similar field, and at least two to three years of experience
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`with integrated circuits and networks. More education can supplement practical
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`experience and vice versa. Depending on the engineering background and level of
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`education of a person, it would have taken a few years for the person to become
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`familiar with the problems encountered in the art and to become familiar with the
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`prior and current solutions to those problems.
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`19. All of my opinions in this declaration are from the perspective of one
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`of ordinary skill in the art, as I have defined it here, during the relevant timeframe,
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`i.e., mid-to-late 2000s.
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`V. TECHNICAL BACKGROUND
`In this section, I present a brief overview of certain aspects of switching
`20.
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`networks and FPGAs at the time of the alleged invention that will assist in better
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`understanding the ’523 patent and the prior art that I discuss in this declaration. For
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`example, the prior art I discuss in this declaration and the ’523 patent generally
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`relates to switching networks that can be used to route signals between logic blocks
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`included on an integrated circuit device. Below, I begin with a description of some
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`fundamental aspects of FPGAs such as those described in the ’523 patent and/or
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`prior art references cited in this declaration.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`A.
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`Field-Programmable Gate Arrays (FPGAs)
`21. Wong (Ex. 1008), which was filed on January 23, 2004 and claims
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`priority to a provisional application filed on August 4, 2000 (i.e., long before the
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`alleged invention in the ’523 patent), and which issued on September 6, 2005,
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`provides a good overview of FPGAs and example networks used in FPGAs. FPGAs
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`are integrated circuits that are designed to allow a user to configure the circuitry of
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`the FPGA to perform a desired function after the FPGA integrated circuit has already
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`been manufactured. (Ex. 1008 at 1:18-21.) As the name implies, FPGAs include an
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`array or arrays of programmable logic blocks (e.g., gates), where the connections
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`between the logic blocks can be set up after manufacturing and therefore are
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`considered to be “field-programmable.” In other words, once manufacturing is
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`complete, the FPGA integrated circuit device includes logic and a network
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`interconnecting the logic, where the user can configure the logic and interconnection
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`network such that the FPGA performs a desired processing function. The
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`interconnection network on the FPGA is used to provide the configurable
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`connections between the programmable logic blocks. (Id. at 1:22-25.)
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`22.
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`In FPGAs such as those discussed in Wong, the interconnection
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`network that connects the logic blocks includes links between programmable
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`switches, where the links provide connections between the switches and also provide
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`U.S. Patent No. 8,269,523
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`connections from the switches to the logic blocks in the FPGA. As such, the links
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`are the inputs to, and outputs from, the switches. Within each switch, the inputs to
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`the switch are programmably routed to particular outputs of the switch. (Id. at 1:61-
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`2:6.) For example, figure 3D of Wong (below) illustrates an interconnection network
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`that includes a plurality of switches 20 (shown as square boxes) that can be used to
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`route any of the inputs to the network on the left to any of the outputs of the network
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`on the right. (Id. at 4:18-26, FIG. 3D.) The arrows between the switches correspond
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`to the “links” in the network. According to Wong, the particular network illustrated
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`in figure 3D is an 8x8 Benes network that has eight inputs and eight outputs. (Id. at
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`2:36-37.)
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`(Id. at FIG. 3D.)
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`23. Each of the switches 20 shown in the network of figure 3D above is a
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`2x2 switch that has two inputs and two outputs. (Id. at 2:31-37, 5:4-6, FIG. 3D.) As
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`shown in figures 2A and 2B of Wong below, each switch can be set up in either a
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`“pass” configuration where the inputs are passed straight through to the outputs (with
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`the upper input passed to the upper output, and the lower input passed to the lower
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`output) or set up in a “cross” configuration where the upper input is routed to the
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`lower output and vice-versa. (Id. at 2:27-29, 5:6-13.) As further disclosed by Wong,
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`“[t]he building block of the described Benes network is the 2x2 (2 input, 2 output)
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`switch 20, having operations illustrated in FIGS. 2A and 2B” (id. at 5:4-6) where
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`“[t]hese 2x2 switches are connected in a specific topology to build a Benes network”
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`(id. at 5:26-27).
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`
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`(Id. at FIGs. 2A, 2B.)
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`24. A controlling configuration bit is used to determine how the inputs to
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`the switch are routed to the outputs of the switch (e.g., whether the switch is in a
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`“pass” or “cross” configuration). (Id. at 3:48-50.) For example, figure 2C of Wong,
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`U.S. Patent No. 8,269,523
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`replicated below, shows how multiplexers are used to implement a 2x2 switch with
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`the functionality of the switches shown in figures 2A and 2B. The multiplexers are
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`controlled by a configuration bit or control bit that is used to determine which
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`outputs are connected to which inputs of the switch.
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`(Ex. 1008 at FIG. 2C (annotated).)
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`25. By controlling the individual switches in the network, the routing of the
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`inputs to the network to selected outputs can be controlled. In the example
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`configuration shown below in figure 3E of Wong, by placing some of the switches
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`in the “pass” configuration and others in the “cross” configuration, the network of
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`switches can be used to route any of the eight inputs to any of the eight outputs. (Id.
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`at 5:65-67.) For example, as shown in figure 3E of Wong below, a particular
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`configuration of the switches reverses the ordering of input signals at the output
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`terminals of the network. (Id. at 2:38-40, 5:67-6:5.) For example, by setting each
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`of the switches to be either “pass” or “cross” as shown below in figure 3E, the top-
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`most input on the left (“000”) is routed such that it comes out at the bottom-most
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`output on the right, whereas the bottom-most input on the left (“111”) is routed to
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`the top-most output on the right. In traversing the network, each of the inputs to the
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`network passes through five switches in the network.
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`(Id. at FIG. 3E.)
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`Declaration of R. Jacob Baker, Ph.D., P.E.
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`26. As demonstrated by Wong, it was well known long before the time of
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`the alleged invention in the ’523 patent to use networks, such as, for example, the
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`one depicted above in figure 3E of Wong, in FPGA devices. Moreover, it was also
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`well known to modify such networks in order to make them more efficient as the
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`interconnection network for an FPGA. For example, because the logic cells used in
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`the FPGA include both inputs and outputs, the network can be folded in half in order
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`to put both the inputs to the network and the outputs from the network adjacent to
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`each other for easy connection to the inputs and outputs of the logic cells. (Id. at
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`6:52-61.) Such folding is illustrated by figure 4A of Wong, where the folding is done
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`along the dotted line 31. (Id. at 6:65-67.)
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`(Id. at FIG. 4A.)
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`27. The resulting folded network is shown in figures 4B and 4C of Wong
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`below, where figure 4C has rearranged the connections between the switches in the
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`network so that the shorter connections are closer to the logic cells, which are placed
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`on the left hand side of the network. (Id. at 7:6-21.) As can be seen in figures 4B
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`and 4C, folding the network puts switches 1.1 and 5.1 together (both of these
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`switches are two stages away from switch 3.1 of figure 4A) and switches 2.1 and 4.1
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`together (both of these switches are one stage away from switch 3.1).
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`(Id. at FIGs. 4B, 4C.)
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`28. A physical layout of the network shown in figure 4C with the
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`accompanying logic cells for an FPGA is shown below in figure 13A of Wong. The
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`physical layout shown in Figure 13A includes the network of switches 82 and
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`associated logic cells 81. (Id. at 13:12-26.)
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`(Id. at FIG. 13A.)
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`29. A person of ordinary skill in the art would have understood that the
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`physical layout corresponds to how the circuitry is physically arranged on the
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`integrated circuit device. In other words, in the integrated circuit FPGA that includes
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`the network shown in figure 13A above, the logic cells 81 would be arranged
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`vertically in a column, and the switches 82 would be arrayed in rows and columns
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`with appropriate connections corresponding to the illustrated links provided on the
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`integrated circuit. The arrows on the right-hand side of figure 13A correspond to
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`the top level connections between the network and primary input/output (I/O) of the
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`FPGA. (Id. at 13:42-43.) A person of ordinary skill in the art would have understood
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`that the signals provided to the FPGA, which the logic cells 81 are used to process,
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`are provided on the primary inputs of the FPGA, whereas the results generated by
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`that processing are provided on the primary outputs of the FPGA.
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`30. As depicted in figure 13A of Wong, logic cells 81 are included in the
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`FPGA along with switch cells 82. (Id. at 13:22-23 (“There are two logic cells 81 per
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`switch cell 82….”).) The logic cells in an FPGA are used to process the inputs
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`provided to the FPGA. The processing functions performed by the logic cells are
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`often configurable by the user. (Id. at 7:32-38, 8:51, 9:10, 14:44-48.) As such, not
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`only the connections between the logic cells are configurable, but the actual
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`processing functions performed by the logic cells are also configurable by the user
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`after manufacturing is complete.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`VI. OVERVIEW OF THE ’523 PATENT
`31. The ’523 patent is entitled “VLSI Layouts of Fully Connected
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`Generalized Networks.” (Ex. 1001 at Title.) The ’523 patent acknowledges that
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`multi-stage hierarchical networks were known and used in many applications at the
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`time of the alleged invention. (Ex. 1001 at 2:25-27 (“Multi-stage interconnection
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`networks such as Benes networks and butterfly fat tree networks are widely useful
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`in
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`telecommunications, parallel and distributed computing.”).) Practical
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`applications where the multi-stage hierarchical networks can be used include
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`FPGAs. (Id. at 2:62-67.)
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`32. The ’523 patent recognizes that VLSI (very large scale integration)
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`layouts for integrated circuits with such networks were known, but states that such
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`layouts are “inefficient and complicated.” (Id. at 2:28-30.) For example, the ’523
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`patent acknowledges that Wong (Ex. 1008) discloses a layout of a Benes network.2
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`(Ex. 1001 at 2:56-61.) However, the ’523 patent contends that prior art network
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`layouts “require large area to implement the switches on the chip, large number of
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`2 Benes networks were originally developed by Vaclav E. Benes at Bell Labs in the
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`mid-1960s. (See, e.g., Ex. 1040 at Cover.)
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`U.S. Patent No. 8,269,523
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`wires, longer wires, with increased power consumption, increased latency of the
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`signal which effect the maximum clock speed of operation.” (Id. at 3:1-6.)
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`33. Evidently in an attempt to address these issues, the ’523 patent alleges
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`to disclose “VLSI layouts of generalized multi-stage networks for broadcast, unicast
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`and multicast connections [] using only horizontal and vertical links” where “[t]he
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`VLSI layouts employ shuffle exchange links where outlet links of cross links from
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`switches in a stage in one sub-integrated circuit block are connected to inlet links of
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`switches in the succeeding stage in another sub-integrated circuit block so that said
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`cross links are either vertical links or horizontal and vice versa.” (Id. at 3:21-29.)
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`The ’523 patent describes using such networks, which are made up of switches, “for
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`satisfying communication requests, such as setting up a telephone call or a data call,
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`or a connection between configurable logic blocks.” (Id. at 8:44-50.)
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`34. For example, figure 1A of the ’523 patent shows an exemplary 32x32
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`(32 inputs and 32 outputs) multi-stage network. (Id. at 8:44-50.) The multi-stage
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`network includes a plurality of stages, where a stage corresponds to a column in the
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`array of switches. The example network in figure 1A of the ’523 patent includes
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`nine stages, including an input stage 110 (left-most column) and output stage 120
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`(right-most column) with middle stages 130, 140, 150, 160, 170, 180, and 190
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`between the input stage 110 and the output stage 120. (Id. at 3:51-57, 8:44-52, FIG.
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`1A.)
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`(Ex. 1001 at FIG. 1A (annotated.))
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`35. The ’523 patent describes the connection topology of the network 100A
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`in figure 1A as “having inverse Benes connection topology of nine stages.” (Id. at
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`3:51-57.) Within the network 100A a number of “links” are provided that
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`interconnect the switches. As highlighted in annotated figure 1A below, inlet links
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`IL1-IL32 provide inputs to the network and outlet links OL1-OL32 provide outputs
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`from the network. (Id. at 9:3-12, FIG. 1A.)
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`(Id. at FIG. 1A (annotated.))
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`36.
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`In addition to the inlet and outlet links on the periphery of the network,
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`the ’523 patent also includes middle links that provide connections between the
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`switches in the different stages of the network. According to the ’523 patent, “[t]he
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`middle links which connect switches in the same row in two successive middle
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`stages are called hereinafter straight middle links; and the middle links which
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`connect switches in different rows in two successive middle stages are called
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`U.S. Patent No. 8,269,523
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`hereinafter cross middle links.” (Id. at 9:45-49 (emphasis added).) Examples of
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`such straight middle links and cross middle links are shown in the annotated
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`excerpt of figure 1A below.
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`For example, the middle links ML(1,1) and ML(1,2)
`connect input switch IS1 and middle switch MS(1,1), so
`middle links ML(1,1) and ML(1,2) are straight middle
`links; where as the middle links ML(1,3) and ML(1,4)
`connect input switch IS1 and middle switch (MS1,2),
`since input switch IS1 and middle switch MS(1,2) belong
`to two different rows in diagram 100A of FIG. 1A, middle
`links ML(1,3) and ML(1,4) are cross middle links.
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`(Id. at 9:49-57; see also id. at 35:65-36:3.)
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`(Id. at FIG. 1A (excerpt, annotated).)
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`37. The ’523 patent further describes folding the network 100A shown in
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`figure 1A to form network 100B shown below in figure 1B. (Id. at 3:58-64, 12:6-
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`8.) This is similar to the folding described above with respect to figures 4A-4C of
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`Wong. (See my discussion in Section V.A above; Ex. 1008 at FIGs. 4A-4C, 6:51-
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`7:22.) The network 100B in figure 1B has five stages, with the inputs and outputs
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`of the network on the left-hand side of the figure. (Id. at 3:58-64, 12:6-53, FIG. 1B.)
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`(Id. at FIG. 1B (annotated).)
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`U.S. Patent No. 8,269,523
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`38. As can be seen in the annotated excerpt of figure 1B below, the folded
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`network includes straight middle links and cross middle links.
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`(Id. at FIG. 1B (excerpt, annotated).)
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,523
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`VII. CLAIM CONSTRUCTION
`I understand that claim terms are typically given their ordinary and
`39.
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`customary meaning, as would have been understood by a person of ordinary skill in
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`the art, at the time of the alleged invention, which I understand is mid-to-late 2000s
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`(including May 25, 2007, the filing date of the ’394 provisional application to which
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`the ’523 patent claims priority). In considering the meaning of the claims, however,
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`I understand that one must consider the language of the claims, the specification, and
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`the prosecution history of record.
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`VIII. OVERVIEW OF THE PRIOR ART
`A. Wong
`40. Wong relates to an “interconnection network architecture which
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`provides an interconnection network which is especially useful for FPGAs.” (Ex.
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`1008 at Abstract.) An example layout of an FPGA that includes Wong’s
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`interconnection network architecture is shown in figure 13A below. (Id. at FIG.
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`13A, 13:12-16.) The FPGA layout includes switches 82 (annotated in green) and
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`associated logic cells 81 (annotated in red). (Id. at FIG. 13A, 13:12-16.)
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`(Id. at FIG. 13A (annotated).)
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`41. The layout shown in figure 13A of Wong includes a single column with
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`four rows of switches. The arrows on the right hand side of figure 13A (annotated
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`in blue above) correspond to the top level connections between the network and
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`primary input/output (I/O) of the FPGA. (Id. at 13:42-43.) A person of ordinary
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`skill in the art would have understood that the signals provided to the FPGA that are
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`processed by the logic blocks 81 are provided on the primary inputs of the FPGA.
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`Similarly, a person of ordinary skill in the art would have understood that the results
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`generated by that processing are provided on the primary outputs of the FPGA.
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`42. The networks used in the FPGAs disclosed in Wong utilize links
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`between switches in successive stages in the same row of switches (annotated in blue
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`below) as well as links between switches in successive stages in different rows
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`(annotated in green below).
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`(Id. at FIG. 13A (annotated).)
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`U.S. Patent No. 8,269,523
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`43. Wong discloses that the single column network shown in figure 13A
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`can be expanded to include multiple columns. (Id. at 13:33-42.) For example, figure
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`13B of Wong shows a network that includes two columns where each column
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`includes four rows.
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`(Id. at FIG. 13B (annotated).)
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`44. According to Wong, “[t]he strength of this column floorplan is that the
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`number of cells in a column can be any power of 2, and the number of rows can also
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`independently be any power of 2,” which “enables the generation of arrays
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`U.S. Patent No. 8,269,523
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`containing numbers of cells that are any power of 2, and with a selection of various
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`aspect ratios.” (Id. at 13:44-49.) In other words, the networks disclosed in Wong
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`are expandable in both the row dimension and the column dimension, and various
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`aspect ratios having different row:column ratios (number of rows vs. number of
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`columns) are contemplated.
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`45. Wong also discloses example implementations of switches that can be
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`used in the networks disclosed. For example, figure 2C shows an example 2x2
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`switch, and figure 7 shows an example 4x4 switch. (Id. at 2:29-30, 2:56-57, 5:14-
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`29, 8:12-34, FIGs. 2C, 7.)
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`(Id. at FIGs. 2C, 7.)
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 8,269,52