Trials@uspto.gov
`571-272-7822
`
`Paper 13
`Entered: September 19, 2019
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`FLEX LOGIX TECHNOLOGIES INC.,
`Petitioner,
`
`v.
`
`VENKAT KONDA,
`Patent Owner.
`____________
`
`Case PGR2019-00037
`Patent 10,003,553 B2
`____________
`
`Before PATRICK M. BOUCHER, CHARLES J. BOUDREAU, and
`NORMAN H. BEAMER, Administrative Patent Judges.
`
`BOUCHER, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Post-Grant Review
`35 U.S.C. § 324
`
`Flex Logix Technologies, Inc. (“Petitioner”) filed a Petition (Paper 1,
`“Pet.”) pursuant to 35 U.S.C. ¶¶ 321–329 to institute a post-grant review of
`claims 1–20 of U.S. Patent No. 10,003,553 B2 (“the ’553 patent”). Venkat
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`Page 1 of 40
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`FLEX LOGIX EXHIBIT 1048
`
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`571-272-7822
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`Paper 13
`Entered: September 19, 2019
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`FLEX LOGIX TECHNOLOGIES INC.,
`Petitioner,
`
`v.
`
`VENKAT KONDA,
`Patent Owner.
`____________
`
`Case PGR2019-00037
`Patent 10,003,553 B2
`____________
`
`Before PATRICK M. BOUCHER, CHARLES J. BOUDREAU, and
`NORMAN H. BEAMER, Administrative Patent Judges.
`
`BOUCHER, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Post-Grant Review
`35 U.S.C. § 324
`
`Flex Logix Technologies, Inc. (“Petitioner”) filed a Petition (Paper 1,
`“Pet.”) pursuant to 35 U.S.C. ¶¶ 321–329 to institute a post-grant review of
`claims 1–20 of U.S. Patent No. 10,003,553 B2 (“the ’553 patent”). Venkat
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`FLEX LOGIX EXHIBIT 1048
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`
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`PGR2019-00037
`Patent 10,003,553
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`Konda (“Patent Owner”)1 filed a Preliminary Response (Paper 5, “Prelim.
`Resp.”). Applying the standard set forth in 35 U.S.C. § 324(a), which
`requires demonstration that it is more likely than not that at least one
`challenged claim is unpatentable, we institute a post-grant review on all
`grounds and challenges set forth in the Petition. The Board has not made a
`final determination on the patentability of any claim.
`
`
`I. BACKGROUND
`A. The ’553 Patent
`The ’553 patent was filed on April 28, 2016, and claims the benefit of
`the following: (1) the March 6, 2014 filing date of U.S. Patent Appl. No.
`14/199,168 (now issued as U.S. Patent No. 9,374,322 (“the ’322 patent”));
`(2) the September 6, 2012 filing date of PCT/US12/53814 (“the ’814 PCT
`application”); and (3) the September 7, 2011 filing date of Provisional Patent
`Appl. No. 61/531,615 (“the ’615 provisional application”). Ex. 1001, 1:8–
`14; Ex. 1004, 1 (Certificate of Correction). A summary drawing provided
`by Petitioner is reproduced below. Pet. 4.
`
`
`1 The Petition identifies the owner of the ’553 patent as Konda
`Technologies, Inc. Pet. 1. This appears to have been correct at the time the
`Petition was filed, on March 18, 2019. But on April 8, 2019, an assignment
`was recorded with the Office at reel/frame 048822/0867 assigning the ’553
`patent to Venkat Konda. This ownership is also reflected in Patent Owner’s
`mandatory notices, filed on April 9, 2019. Paper 4.
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`Petitioner’s drawing summarizes certain claims to earlier filing dates, and is
`similar to a drawing provided by Patent Owner that is in substantial
`agreement. See Prelim. Resp. 7. Although the drawing also refers to U.S.
`Patent Appl. No. 15/984,408, that application is not relevant to this
`proceeding. In addition, the ’553 patent recites that it incorporates the
`“entirety” of several additional patents and applications. Id. at 1:14–2:62.
`The ’553 patent relates to multi-stage interconnection networks that
`find utility in multiple applications. Id. at 2:66–3:1. According to the ’553
`patent, very large scale integration (“VLSI”) layouts for integrated circuits
`with such networks can be “inefficient and complicated.” Id. at 3:2–4. For
`example, prior-art networks of the type identified by the ’553 patent “require
`large area to implement the switches on the chip, large number of wires,
`longer wires, with increased power consumption, increased latency of the
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`signals which [a]ffect the maximum clock speed of operation.” Id. at 3:43–
`48.
`
`Accordingly, the ’553 patent discloses a number of configurations of
`multi-stage hierarchical networks. One example is illustrated in Figure 1A
`of the patent, reproduced below.
`
`
`
`Figure 1A illustrates an exemplary partial multi-stage hierarchical network
`(or “block”) in which each computational block has four inlet links I1, I2, I3,
`I4 and two outlet links O1, O2. Id. at 8:57–62. For each computational
`block, a corresponding partial multi-stage hierarchical network has two
`“rings” 110, 120. Id. at 8:62–9:3. Ring 110 has inlet links Ri(1,1), Ri(1,2)
`and outlet links Bo(1,1), Bo(1,2). Id. at 9:4–6. Ring 120 similarly has inlet
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`links Fi(2,1), Fi(2,2) and outlet links Bo(2,1), Bo(2,2). Id. at 9:5–6. The
`partial multi-stage hierarchical network thus has four inlet links and four
`outlet links corresponding to the two rings 110, 120. Id. at 9:6–9.
`Several connections characterize the specific structure illustrated.
`First, outlet link O1 is connected to inlet link Ri(1,1) of ring 110 and also to
`inlet link Fi(2,1) of ring 120. Id. at 9:9–11. Second, outlet link O2 is
`connected to inlet link Ri(1,2) of ring 110 and also to inlet link Fi(2,2) of
`ring 120. Id. at 9:11–13. Third, outlet link Bo(1,1) of ring 110 is connected
`to inlet link I1. Id. at 9:14–15. Fourth, outlet link Bo(1,2) of ring 110 is
`connected to inlet link I2. Id. at 9:15–16. Fifth, outlet link Bo(2,1) of ring
`120 is connected to inlet link I3. Id. at 9:17–18. Sixth, outlet link Bo(2,2)
`of ring 120 is connected to inlet link I4. Id. at 9:18–20. Because outlet link
`O1 is connected to both inlet link Ri(1,1) of ring 110 and inlet link Fi(2,1) of
`ring 120, and outlet link O2 is connected to both inlet link Ri(1,2) of ring
`110 and inlet link Fi(2,2) of ring 120, the partial multi-stage hierarchical
`network has two inlet links and four outlet links. Id. at 9:20–26.
`The drawing also illustrates multiple “stages.” Ring 110 (i.e., ring 1)
`consists of m+1 stages, and ring 120 (i.e., ring 2) consists of n+1 stages. Id.
`at 8:65–9:1. For example, “ring 1, stage 0” has four inputs Ri(1,1), Ri(1,2),
`Ui(1,1), Ui(1,2) and four outputs Bo(1,1), Bo(1,2), Fo(1,1), Fo(1,2). Id. at
`9:62–66. That stage also has eight 2:1 multiplexers R(1,1), R(1,2), F(1,1),
`F(1,2), U(1,1), U(1,2), B(1,1), B(1,2). Id. at 9:66–10:2. Multiplexer R(1,1)
`has two inputs Ri(1,1), Bo(1,1) and one output Ro(1,1). Id. at 10:2–3.
`Multiplexer R(1,2) has two inputs Ri(1,2), Bo(1,2) and one output Ro(1,2).
`Id. at 10:3–6. Multiplexer F(1,1) has two inputs Ro(1,1), Ro(1,2) and one
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`output Fo(1,1). Id. at 10:5–6. Multiplexer F(1,2) has two inputs Ro(1,1),
`Ro(1,2) and one output Fo(1,2). Id. at 10:6–8. Multiplexer U(1,1) has two
`inputs Ui(1,1), Fo(1,1) and one output Uo(1,1). Id. at 10:9–10. Multiplexer
`U(1,2) has two inputs Ui(1,2), Fo(1,2) and one output Uo(1,2). Id. at 10:10–
`12. Multiplexer B(1,1) has two inputs Uo(1,1), Uo(1,2) and one output
`Bo(1,1). Id. at 10:12–13. Multiplexer B(1,2) has two inputs Uo(1,1),
`Uo(1,2) and one output Bo(1,2). Id. at 10:13–15. The patent also details the
`connections of other stages that appear in the drawing, some of which also
`have eight multiplexers and others of which have only six multiplexers. Id.
`at 10:16–12:59.
`As illustrated by Figure 8 of the ’553 patent (not reproduced here),
`multiple blocks like those shown in Figure 1A may be arranged in a two-
`dimensional grid. Id. at 9:27–35. In such an arrangement, each block of the
`grid is part of the die area of a semiconductor integrated circuit so that the
`complete two-dimensional grid represents the complete die of the
`semiconductor integrated circuit. Id. at 9:36–39.
`Figure 3 of the ’553 patent is reproduced below.
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`Figure 3A illustrates connections between successive stages of a ring “x”
`and two successive stages of another ring “y.” Id. at 20:42–48. Of
`particular relevance are the “hop” connections between the distinct rings:
`Hop(1,1) connects output Fo(x,2p+2) to input Ri(y,2q+4), Hop(1,2)
`connects output Bo(x,2p+4) to input Ui(y,2q+2), Hop(2,1) connects output
`Fo(y,2q+2) to input Ri(x,2p+4), and Hop(2,2) connects output Bo(y,2q+4) to
`input Ui(x,2p+2). Id. at 22:15–26. The ’553 patent explains that rings x and
`y “may or may not belong to the same block of the complete multi-stage
`hierarchical network.” Id. at 22:29–30. If the rings belong to the same
`block, the hop connections are referred to as “internal hop wires”;
`conversely, if the rings belong to different blocks, they are referred to as
`“external hop wires.” Id. at 22:29–40. External hop wires may be
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`“horizontal wires or vertical wires,” and the length of external hop wires,
`referred to as “hop length,” is the “manhattan distance between the
`corresponding blocks,” i.e. the sum of the vertical and horizontal differences
`separating the blocks. Id. at 22:40–63. Hop lengths are “positive
`integer[s].” Id. at 29:40–41, 32:18–19.
`
`
`B. Illustrative Claim
`Independent claim 1 of the ’553 patent is illustrative of the challenged
`claims, and is reproduced below.
`1. A network implemented in a non-transitory medium
`comprising a plurality of subnetworks and a plurality of inlet
`links and a plurality of outlet links,
`said plurality of subnetworks arranged in a two-
`dimensional grid of rows and columns; and
`each subnetwork comprising y stages, where y ≥ 1; and
`each stage comprising a switch of size di × do, where di ≥
`2 and do ≥ 2 and each switch of size di × do having di incoming
`links and do outgoing links; and
`Said inlet links are connected to one or more of said
`incoming links of a said switch of a said stage of a said
`subnetwork, and said outlet links are connected to one of said
`outgoing links of a said switch of a said stage of a said
`subnetwork; and
`each subnetwork of the plurality of subnetworks may or
`may not be comprising the same number of said inlet links and
`may or may not be comprising the same number of said outlet
`links; each subnetwork of the plurality of subnetworks may or
`may not be comprising the same number of said stages; each
`stage may or may not be comprising the same number of
`switches; and each switch in each stage may or may not be of
`the same size, each multiplexer in each stage may or may not be
`of the same size and
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`Said incoming links and outgoing links in each switch in
`each stage of each subnetwork comprising a plurality of
`forward connecting links connected from switches in a stage to
`switches in another stage in same said subnetwork or another
`said subnetwork, and also comprising a plurality of backward
`connecting links connected from switches in a stage to switches
`in another stage in same subnetwork or another said
`subnetwork; and
`Said forward connecting links comprising zero or more
`straight links connected from a switch in a stage in a
`subnetwork to a switch in another stage in the same subnetwork
`and also comprising zero or more cross links connected from a
`switch in a stage in a subnetwork to a switch in the same
`numbered stage in one or more other subnetworks, and
`Said backward connecting links comprising zero or more
`straight links connected from a switch in a stage in a
`subnetwork to a switch in another stage in the same
`subnetwork; and also comprising zero or more cross links
`connected from a switch in a stage in a subnetwork to a switch
`in the same numbered stage in one or more other subnetworks.
`
`Ex. 1001, 48:62–49:40.
`
`
`C. Asserted Grounds of Unpatentability
`Petitioner challenges claims 1–20 on the following grounds:
`Claims Challenged
`Statutory basis
`References
`1–20
`§ 112(b)
`None
`1–20
`§ 112(a) (written description)
`None
`1–20
`§ 112(a) (enablement)
`None
`
`
`Petitioner supports its challenges with a Declaration by R. Jacob Baker,
`Ph.D., P.E. Ex. 1002.
`
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`D. Real Parties in Interest
`The parties identify only themselves as real parties in interest. Pet. 3;
`Paper 4, 2.
`
`
`E. Related Proceedings
`The ’553 patent was involved in Konda Technologies Inc. v. Flex
`Logix Technologies, Inc., No. 5:18-cv-07581-LHK (N.D. Cal.). See Pet. 3.
`Subsequent to filing of the Petition, this action has apparently been
`dismissed without prejudice. Paper 10, 2. The ’553 patent is also the
`subject of concurrently filed petitions in PGR2019-00040 and PGR2019-
`00042. Pet. 3–4; Prelim. Resp. 2.
`
`
`II. ANALYSIS
`A. Level of Skill in the Art
`Petitioner contends that the relevant level of skill in the art is that
`possessed by a person who “would have had a master’s degree in electrical
`engineering or a similar field, and at least two to three years of experience
`with integrated circuits and networks.” Pet. 6 (citing Ex. 1002 ¶ 18).
`Petitioner asserts that “[m]ore education can supplement practical
`experience and vice versa.” Id. Patent Owner does not advocate for a
`particular level of skill in the art at this time.
`At this stage of the proceeding, we find Petitioner’s proposal
`consistent with the level of ordinary skill in the art reflected by the prior art
`of record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001);
`In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995). Therefore, for
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`purposes of this Decision, we adopt Petitioner’s unopposed position as to the
`level of ordinary skill in the art.
`
`
`B. Claim Construction
`For petitions filed after November 13, 2018, the Board uses “the same
`claim construction standard that would be used to construe the claim in a
`civil action under 35 U.S.C. 282(b), including construing the claim in
`accordance with the ordinary and customary meaning of such claim as
`understood by one of ordinary skill in the art and the prosecution history
`pertaining to the patent.” 37 C.F.R. § 100(b); see Phillips v. AWH Corp.,
`415 F.3d 1303, 1312–13 (Fed. Cir. 2005) (en banc). Petitioner “submits that
`for purposes of this proceeding, no term requires construction.” Pet. 31
`(citing Ex. 1002 ¶ 51). Patent Owner also declines at this time to take a
`position regarding construction of the challenged claims. Prelim. Resp. 44.
`Because only those claim terms that are in controversy need to be
`construed, and only to the extent necessary to resolve the controversy, we do
`not expressly construe any claim term for purposes of this Decision. Nidec
`Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017
`(Fed. Cir. 2017)
`
`
`C. Eligibility for Post-Grant Review
`The post-grant review provisions of the Leahy-Smith America Invents
`Act, Pub. L. No. 112-29, 125 Stat. 284 (2011) (“AIA”) apply only to patents
`subject to the first-inventor-to-file provisions of the AIA. AIA § 6(f)(2)(A).
`Specifically, the first-inventor-to-file provisions apply “to any application
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`for patent, and to any patent issuing thereon, that contains or contained at
`any time . . . a claim to a claimed invention that has an effective filing
`date . . . that is on or after the effective date [of March 16, 2013].” AIA
`§ 3(n)(1)(A).
`Petitioner contends that “[t]he ’553 patent is eligible for PGR because
`it has at least one claim that is not entitled to the filing date of either the ’615
`provisional application or the ’814 PCT application,” which Petitioner and
`we refer to collectively as “the two pre-AIA applications.” Pet. 17.
`According to Petitioner, “at least claims 1, 2, 4, 9, 11, 12, and 14 of the ’553
`patent include subject matter that is not disclosed in the two pre-AIA
`applications.” Id. (citing PowerOasis, Inc. v. T-Mobile USA, Inc., 522 F.3d
`1299, 1306 (Fed. Cir. 2008); In re Gosteli, 872 F.2d 1008, 1010–11 (Fed.
`Cir. 1989)).
`
`
`1. Claim 9: “flip-flop”
`Petitioner contends that claim 9, which recites “each switch
`configurable by an SRAM Cell or a Flash Cell or a flip-flop,” Ex. 1001,
`50:31–32, is not entitled to a pre-AIA filing date because “[a] ‘flip-flop’ is
`never mentioned in the two pre-AIA applications.” Pet. 18. Patent Owner
`does not dispute that the two pre-AIA applications lack explicit disclosure of
`a “flip-flop,” and quotes the same language from the ’814 PCT application
`as Petitioner. See id. at 18–19; Prelim. Resp. 17–18. Specifically, the ’814
`PCT application discloses:
`In volatile programmable integrated circuit embodiments the
`programmable cell may be an SRAM (Static Random Address
`Memory) cell. In non-volatile programmable integrated circuit
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`embodiments the programmable cell may be a Flash memory
`cell.
`
`Ex. 1006, 75:23–25.
`
`
`In other embodiments all the d * d switches described in the
`current invention are also implemented using muxes of
`different sizes controlled by SRAM cells or flash cells etc.
`
`Id. at 76:4–6.
`According to Patent Owner, the open-ended use of “etc.” in the
`second of these passages “provides information to a [person of ordinary skill
`in the art] that SRAM Cells and Flash Cells are only two ways of controlling
`switches or multiplexers and guiding a [person of ordinary skill in the art]
`that there are more ways of controlling switches or multiplexers in the ‘prior
`art.’” Prelim. Resp. 19. Citing a textbook authored by Petitioner’s expert,
`Dr. Jacob, Ex. 2001, Patent Owner asserts that a “[f]lip-flop is an obvious
`circuit that a digital engineering student learns even before SRAM cell and
`Flash Memory cell.” Id. Patent Owner accordingly argues that addition of
`the term “flip-flop” to claim 9 “did not add any new subject matter to the
`‘553 patent.” Id. at 20.
`Even crediting Patent Owner’s contention that use of a flip-flop would
`have been an obvious variation of the expressly disclosed SRAM and Flash
`Memory cells, Patent Owner’s argument is untenable. “Entitlement to a
`filing date does not extend to subject matter which is not disclosed, but
`would be obvious over what is expressly disclosed.” In re Huston, 308 F.3d
`1267, 1277 (Fed. Cir. 2002). Rather, “the missing descriptive matter must
`necessarily be present in the [earlier] application’s specification such that
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`one skilled in the art would recognize such a disclosure.” Tronzo v. Biomet,
`Inc., 156 F.3d 1154, 1159 (Fed. Cir. 1998) (emphasis added); see also
`Martin v. Mayer, 823 F.2d 500, 505 (Fed. Cir. 1987) (holding that the
`written description requirement is “not a question of whether one skilled in
`the art might be able to construct the patentee’s device from the teachings of
`the disclosure. . . . Rather, it is a question whether the application
`necessarily discloses that particular device”).
`
`2. Claims 1, 11: “cross links connected . . . to a switch in the same
`numbered stage”
`Petitioner contends that certain aspects of the “cross links” recited in
`independent claims 1 and 11, and further narrowed by dependent claims 2, 4,
`12, and 14, are not supported by the two pre-AIA applications. Pet. 20–30.
`Independent claim 1 recites (1) “forward connecting links . . . comprising
`zero or more cross links connected from a switch in a stage in a subnetwork
`to a switch in the same numbered stage in one or more other subnetworks,”
`Ex. 1001, 49:27–33; and (2) “backward connecting links . . . comprising
`zero or more cross links connected from a switch in a stage in a subnetwork
`to a switch in the same numbered stage in one or more other subnetworks,”
`id. at 49:34–40. Independent claim 11 similarly recites (1) “incoming
`links . . . comprising zero or more cross links connected from a switch in a
`stage in a subnetwork to a switch in the same numbered stage in one or more
`other subnetworks,” id. at 51:11–17; and (2) “outgoing links . . . comprising
`zero or more cross links connected from a switch in a stage in a subnetwork
`to a switch in the same numbered stage in one or more other subnetworks,”
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`id. at 51:22–28. Hereinafter we refer to these claim limitations as the “same
`stage” limitations.
`Petitioner contends that “[t]he first appearance of a ‘cross link’
`‘connected from a switch in a stage in a subnetwork to a switch in the same
`numbered stage in one or more other subnetworks’ was on January 8, 2018
`when claim 21 (which eventually issued as claim 1) was added during
`prosecution of the [’553 patent].” Pet. 22. According to Petitioner, the “two
`pre-AIA applications do not provide written description support for the
`‘cross links’ features of claim 1.” Id. Specifically, Petitioner observes that
`(outside the material purportedly incorporated by reference) the written
`description of the ’814 PCT application makes limited reference to cross
`links, referring only to cross links from switches in a stage to switches in
`“another stage.” Id. at 22–23 (citing, inter alia, Ex. 1006, Abstr., 5:3–8).
`Petitioner makes a similar observation with respect to the claims of the ’814
`PCT application:
`The same is true with respect to the “cross links” recited in the
`claims of the ’814 PCT application, i.e., they recite “cross links
`connecting from a switch in a stage . . . to a switch in another
`stage,” where the cross links in the ’814 PCT application are
`included in forward and backward connecting links that connect
`“from switches in lower stage to switches in the immediate
`succeeding higher stage” and “from switches in higher stage to
`switches in the immediate preceding lower stage,” respectively.
`
`Id. at 23–242 (emphases by Petitioner). As far as the ’615 provisional
`application, Petitioner makes the further observation that (again, outside the
`
`
`2 Petitioner’s citation for this quotation (Ex. 1006, at p. 80:4–13) is
`incomplete. The full citation is Ex. 1006, 79:25–80:13.
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`material purportedly incorporated by reference) “the ’615 provisional
`application does not include any disclosure relating to a ‘cross link.’” Id.
`(citing Ex. 1007; Ex. 1002 ¶ 65). Based on our independent review of the
`pre-AIA applications, we agree that these observations are accurate.
`In contending that the “same stage” limitations include adequate
`support that predates the AIA, Patent Owner directs our attention to U.S.
`Patent No. 8,898,611 (“the ’611 patent”), which is purportedly incorporated
`by reference into the ’553 patent. Ex. 1001, 2:33–38; Prelim. Resp. 30
`(“Since ‘611 patent is incorporated by reference in the ‘553 patent, the ‘cross
`links’ are supported in the ‘553 patent.”). Patent Owner ties the disclosure
`of the ’611 patent to the claim language by further contending that
`“connections between same number stages or between any two arbitrary
`stages are disclosed in the ‘611 patent.” Prelim. Resp. 30 (citing Ex. 1027,
`44:46–52, 57:8–19).
`Petitioner observes that “[t]he ’553 patent attempts to incorporate by
`reference a list of more than 20 patents and applications.” Pet. 12 (citing Ex.
`1001, 1:8–2:62; Ex. 1002 ¶ 37). Petitioner contends that such attempted
`incorporations are ineffective because “the incorporations by reference of
`these patents and applications provide no ‘detailed particularity [regarding]
`what specific material’ they incorporate and do not ‘clearly indicate where
`that material is found’ in the patents and applications.” Id. (quoting Cook
`Biotech Inc. v. Acell, Inc., 460 F.3d 1365, 1376 (Fed. Cir. 2006); citing
`Paice LLC v. Ford Motor Co., 881 F.3d 894, 906–07 (Fed. Cir. 2018)).
`According to Petitioner, “[t]he ’553 patent simply identifies several patents
`and applications and states that the material is incorporated in its entirety
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`
`without specifying any particular portions of the documents as being
`relevant.” Id. at 13. Patent Owner does not respond in its Preliminary
`Response to Petitioner’s legal argument that the attempted incorporations by
`reference are ineffective.
`“Incorporation by reference provides a method for integrating material
`from various documents into a host document . . . by citing such material in
`a manner that makes clear that the material is effectively part of the host
`document as if it were explicitly contained therein.” Advanced Display Sys.,
`Inc. v. Kent State Univ., 212 F.3d 1272, 1282 (Fed. Cir. 2000) (citations
`omitted). Whether, and to what extent, material has been incorporated by
`reference is a question of law. Cook Biotech, 460 F.3d at 1376.
`In Paice, 881 F.3d at 906–07 (cited by Petitioner), the Federal Circuit
`held that incorporation by reference of an entire patent (“Severinsky”) into a
`priority application was effective in providing written-description support
`for priority purposes if properly done:
`Incorporation by reference provides “a method for
`integrating material from various documents into a host
`document[ ] ... by citing such material in a manner that makes
`clear that the material is effectively part of the host document as
`if it were explicitly contained therein.” Advanced Display Sys.,
`Inc. v. Kent State Univ., 212 F.3d 1272, 1282 (Fed. Cir. 2000).
`“To incorporate material by reference, the host document must
`identify with detailed particularity what specific material it
`incorporates and clearly indicate where that material is found in
`the various documents.” Id. Whether and to what extent
`material has been incorporated by reference is a question of law
`that we review de novo. Harari v. Lee, 656 F.3d 1331, 1334
`(Fed. Cir. 2011). . . .
`The [priority] application expressly incorporates
`Severinsky. . . .
`
`17
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`* * *
`. . . . The . . . passage is broad and unambiguous. It states that
`Severinsky “is,” without qualification, incorporated into the
`[priority] application “by this reference”—i.e., the reference
`contained in the sentence. The sentence identifies with detailed
`particularity the specific material subject to incorporation
`(Severinsky, and not just particular portions thereof) and where
`that material can be found (U.S. Patent No. 5,343,970). Such
`language is plainly sufficient to incorporate Severinsky in its
`entirety. See Harari, 656 F.3d at 1335–36 (finding that prior
`art applications were incorporated in their entirety based on the
`following “broad and unequivocal language”: “‘The disclosures
`of the two applications are hereby incorporate[d] by
`reference’”); Advanced Display, 212 F.3d at 1282.
`As in Paice, the ’611 patent, on which Patent Owner relies, is
`incorporated by reference in its entirety, and therefore is available in
`determining whether the ’553 patent contains sufficient written-description
`support for its claims. As a threshold matter, however, we point out that the
`patents and applications that are incorporated by reference in the ’553 patent
`are not relevant to the issue of post-grant eligibility. Rather, the focus is on
`the disclosures of the pre-AIA applications. Nevertheless, the disclosure of
`the ’611 patent is also disclosed in PCT/US10/52984, filed October 16, 2010
`(“the ’984 PCT application”), which is incorporated by reference in its
`entirety in the pre-AIA ’814 PCT application. Ex. 1006, 2:25–29; Ex. 1028,
`75:17–21, 96:4–12. Therefore, for purposes of this Decision, we instead
`consider whether this identical disclosure, incorporated by reference in that
`pre-AIA application, supports the “same stage” limitations.
`We conclude that it does not. The closest definition of “cross links”
`in the ’984 PCT application refers to “cross middle links,” which are defined
`
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`as “middle links which connect switches in different rows in two successive
`middle stages.” Ex. 1028, 16:20–22. A connection between “successive”
`stages cannot support a requirement for a connection to the same stage.
`Also, the claims of the ’984 PCT application are directed to “cross links
`connecting from a switch in a stage in a block to a switch in another stage in
`a different block”—again, inconsistent with the “same stage” limitations of
`the ’553 claims. Id. at 109:22–23, 110:3–4.
`As alluded to above, we recognize that Patent Owner instead relies on
`a different embodiment, pertaining to “pyramid links,” which are described
`as being capable of connecting “between the switches in the same stage.”
`Prelim. Resp. 30 (citing Ex. 1027, 44:46–52, 57:8–19).3 But there is nothing
`in the ’984 PCT application that would associate the disclosure of “pyramid
`links” to the disclosure of cross links. Patent Owner’s contention effectively
`requires that we “look at the different embodiments disclosed in the various
`patents and make unspecified combinations of elements without any
`guidance as to what should be combined or how such combinations should
`be accomplished.” Pet. 14 (citing D Three Enters., LLC v. Sunmodo Corp.,
`890 F.3d 1042, 1050 (Fed. Cir. 2018)).
`As a separate argument for written-description support for the “same
`stage” limitations, Patent Owner contends that the ’553 patent’s disclosure
`of hop connections is generic, i.e. “between two arbitrary successive stages
`in two different rings of the same block or two different rings of different
`
`
`3 Again, although Patent Owner relies on the disclosure in the ’611 patent,
`the more applicable citation would be to the corresponding portions of the
`’984 PCT application, at Ex. 1028, 75:17–21, 96:4–12.
`19
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`blocks.” Prelim. Resp. 34 (quoting Ex. 1001, 20:37–41). Patent Owner
`reasons that, using the labelling that appears in Figure 3A, reproduced
`above, when q = p + 1, the hop connections are between “same numbered
`stages.” See id. at 36. Again, rather than considering the disclosure of the
`’553 patent, we consider the corresponding disclosure in the pre-AIA ’814
`PCT application. See Ex. 1006, Fig. 3A, 32:6-13. When the ’814 PCT
`application is considered as a whole, Patent Owner’s argument is
`unpersuasive, because the arbitrary stages are “successive,” cross links are
`described as links from switches in a stage to switches in “another stage,”
`and cross links are claimed as connecting “from switches in lower stage to
`switches in the immediate succeeding higher stage” or “from switches in
`higher stage to switches in the immediate preceding lower stage.” Id. at
`5:3–8, 32:6–13, 79:25–80:13 (emphases added).
`Accordingly, in light of these considerations, we find that the “same
`stage” limitations recited in claims 1 and 11 are not supported by the two
`pre-AIA applications.
`This deficiency also extends to the additional limitations recited in
`claims 2 and 12, i.e., that “said cross links between switches of stages in any
`two said subnetworks are connected as either vertical links only, or
`horizontal links only, or both vertical links and horizontal links.” Ex. 1001,
`49:41–45, 51:32–36. As Petitioner asserts, “assuming the recitation of ‘said
`cross links’ in claim 2 modifies the ‘zero or more cross links’ recited in
`claim 1,” including the “same stage” limitations, it logically follows that
`
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`these pre-AIA applications cannot support the limitations of claims 2 and 12.
`Pet. 25.
`
`
`3. Claims 4, 14: hop lengths equal to zero
`With respect to the limitations of claims 4 and 14, particularly that
`“said horizontal links between switches in two said stages are substantially
`of a hop length h and said vertical links between switches in two said stages
`are substantially of a hop length v where h ≥ 0 and v ≥ 0,” we agree with
`Petitioner that the disclosure of the ’553 patent does not support zero hop
`lengths See id. at 27–29; Ex. 1001, 49:60–50:2, 52:4–7. The specification
`limits its disclosure of the vertical and horizontal hop lengths to being
`“positive integer[s].” Ex. 1001, 29:35–41, 32:11–19. Based on our
`independent review, we also agree with Petitioner that “[t]he same
`description of hop lengths being limited to positive [integers] is present in
`the ’814 PCT application . . . and the ’615 provisional application.” Pet. 28–
`29 (citing Ex. 1006, 47:1–5, 49:26–30, 52:23–25; Ex. 1007, 31:9–13, 34:5–
`9, 37:3–5).
`Patent Owner asserts, “[f]or an internal hop wire, hop length is zero.”
`Prelim. Resp. 34. There is no support for this statement in the ’553 patent or
`in any other patent or application of record. Hop length is only defined for
`external hop wires. See Ex. 1001, 22:31–63.
`Accordingly, we further find that the ho
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