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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
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`FLEX LOGIX TECHNOLOGIES INC.,
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`Petitioner
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`V.
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`VENKAT KONDA,
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`Patent Owner
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`____________
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`Case PGR2020-00261
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`Patent 8,269,523 B2
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`_________
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`
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`DECLARATION OF VIPIN CHAUDHARY, PH.D., IN SUPPORT OF
`PATENT OWNER (cid:57)E(cid:49)KA(cid:55) K(cid:50)(cid:49)DA(cid:182)(cid:54) REQUEST FOR REHEARING
`UNDER 37 C.F.R. § 42.71(c)
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`IPR2020-00261
`Patent 8,269,523
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`Exhibit 2025
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`Declaration of Vipin Chaudhary, Ph.D.
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ......................................................................................... 1
`
`BACKGROUND AND QUALIFICATIONS .............................................. 2
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`III. MATERIALS CONSIDERED ..................................................................... 5
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`IV. THE LEVEL OF SKILL IN (cid:55)HE A(cid:53)(cid:55) (cid:55)(cid:50) (cid:58)HICH (cid:55)HE (cid:181)523
`PATENT PERTAINS AND THE TECHNICAL BACKGROUND
`FROM THE VIEWPOINT OF A POSITA AT THE TIME OF THE
`INVENTION .................................................................................................. 7
`
`V.
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`(cid:55)HE (cid:181)523 (cid:51)A(cid:55)E(cid:49)(cid:55) ....................................................................................... 9
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`VI. (cid:51)A(cid:55)E(cid:49)(cid:55)ABILI(cid:55)(cid:60) (cid:50)F (cid:55)HE (cid:181)523 (cid:51)A(cid:55)E(cid:49)(cid:55): (cid:51)A(cid:53)(cid:55)IC(cid:56)LA(cid:53)L(cid:60) (cid:55)HE
`EA(cid:53)LIE(cid:54)(cid:55) EFFEC(cid:55)I(cid:57)E FILI(cid:49)G DA(cid:55)E (cid:50)F (cid:55)HE (cid:181)523 (cid:51)A(cid:55)E(cid:49)(cid:55) ...... 10
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`VII. CONCLUSION ............................................................................................ 16
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`Page ii of 18
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`I, Vipin Chaudhary, Ph.D., hereby declare and state as follows:
`
`I.
`
`INTRODUCTION
`1. My name is Vipin Chaudhary. I am submitting this declaration on
`
`behalf of Patent Owner Venkat Konda ((cid:179)Patent Owner(cid:180)) in support of Patent
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`Owner(cid:182)s Request for Rehearing Under 37 C.F.R. § 42.71(c) in the inter partes
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`Review instituted in Case PGR2020-00261 filed by Petitioner Flex Logix
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`Technologies Inc. ((cid:179)Petitioner(cid:180)) regarding claims 2-7 and 11 (the (cid:179)Challenged
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`Claims(cid:180)) of U.S. Patent No. 8,269,523 (Ex. 1001, (cid:179)the (cid:181)523 Patent(cid:180))
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`2.
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`I have reviewed the (cid:181)523 patent and its claims. I am a technical expert
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`in the subject matter areas relevant to the (cid:181)523 patent, including the field of
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`integrated circuits and interconnection networks. I have been asked to consider the
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`validity of the claims of the (cid:181)523 patent. I have read and understood the content of
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`each of the publications referenced in the Petition filed by Petitioner on December
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`16, 2019 ((cid:179)Petition(cid:180)). I have read and understood the (cid:181)523 Patent and claims 1-48 of
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`the (cid:181)523 patent. This declaration provides my expert opinion regarding the subject
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`matter addressed below.
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`3.
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`This declaration is based on the information currently available to me.
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`To the extent that additional information becomes available, I reserve the right to
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`continue my investigation and study, which may include review of documents and
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`Page 1 of 18
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`information that may be produced, as well as testimony from depositions that have
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`not yet been taken.
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`II. BACKGROUND AND QUALIFICATIONS
`4.
`A copy of my curriculum vitae ((cid:179)CV(cid:180)), which fully describes my
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`qualifications as an expert in this matter, is found at Exhibit 2026. In addition, I
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`have set forth some of my qualifications in the paragraphs below that may be
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`particularly relevant here. I am over 18 years of age and, if I am called upon to
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`do so, I would be competent to testify as to the matters set forth herein.
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`5.
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`I hold a Bachelor Degree (Hons.) in Computer Science and
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`Engineering from the Indian Institute of Technology, Kharagpur, India awarded in
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`1986, and the MS degree in Computer Science in 1989 and the Ph.D. degree in
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`Electrical and Computer Engineering in 1992, both from The University of Texas
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`at Austin.
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`6.
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`Currently I am the Endowed Kranzusch Professor and Inaugural
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`Chair, Department of Computer and Data Sciences, Case School of Engineering,
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`Case Western Reserve University, Cleveland, Ohio. Prior to this position, I was a
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`SUNY Empire Innovation Professor between 2011 and 2020 and SUNY
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`Empire Innovation Associate Professor between 2006 and 2011, Computer
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`Science and Engineering at University at Buffalo, The State University of New
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`Page 2 of 18
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`York. Between June 2016 and June 2020, I was also a Program Director at the
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`Office of Advanced Cyber Infrastructure, Directorate for Computer and
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`Information Science and Engineering, National Science Foundation, Alexandria,
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`Virginia. Prior to the University at Buffalo, I was an Associate Professor,
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`Department of Computer Science, and an Associate Professor, Department of
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`Electrical and Computer Engineering at Wayne State University, Detroit, Michigan
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`between 1998 and 2006, and an Assistant Professor, Department of Electrical and
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`Computer Engineering, Wayne State University between 1992 and 1998.
`
`7.
`
`I have been active in the field of integrated circuits and
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`interconnection networks for over 30 years, since my Ph.D. Dissertation, awarded
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`in 1992, in the area of parallel and distributed computing where interconnection
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`networks is a major part of my dissertation.
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`8.
`
`I have received numerous awards for my work, including the 2019
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`National Science Foundation Director(cid:182)s Superior Accomplishment Award for my
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`contributions where as a Program Director I co-led the National Strategic
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`Computing Initiative from NSF for the United States and in the working groups of
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`the Quantum Leap Initiative, National Quantum Initiative, National Artificial
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`Intelligence Research Institutes, Cyber, and the I-Corps Program. I-Corps program
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`is now part of (cid:179)The American Innovation and Competitiveness Act(cid:180) that enables
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`commercialization of research and venture startups. The U.S. National Strategic
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`Computing Initiative incorporates many aspects of interconnection networks to
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`make large computer systems.
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`9.
`
`I was co-founder of several startups, including as a Senior Director of
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`Advanced Development at Cradle Technologies, Inc., where I was responsible for
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`advanced programming tools development for multi-processor chips where
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`interconnection networks is a key component. In Scalable Informatics, we
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`designed and built some of the highest performance storage and analytics systems.
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`As the CEO of Computational Research Laboratories, we built the fourth largest
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`supercomputer system in the world with a unique interconnection network that
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`enabled fast performance at a fraction of the cost. This company was sold to Tata
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`Consulting Services. Prior to this, I was the Chief Architect at Corio, that is known
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`as one of companies that really started the Software-as-a-Service revolution and
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`had a successful IPO in 2000.
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`10.
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`In Section V, I have disclosed most of my further qualifications
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`particularly relevant to integrated circuits and interconnection networks needed by
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`one of ordinary skill in the art to understand the disclosure of the (cid:181)523 patent at the
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`time of the invention which is about May 25, 2007, the filing date of U.S.
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`Provisional Patent Application No. 60/940,394 ((cid:179)the (cid:181)394 Provisional(cid:180)).
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`Page 4 of 18
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`11. All of my opinions stated in this declaration are based on my own
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`personal knowledge and professional judgment and do not reflect the
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`opinions of my employers. In forming my opinions, I have relied on my
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`knowledge and experience in designing, developing, researching, and
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`teaching related to integrated circuits and interconnection networks
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`referenced in this declaration.
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`12.
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`I am not an attorney and offer no legal opinions.
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`III. MATERIALS CONSIDERED
`13.
`I have considered the following materials in preparing the opinions set
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`forth in this declaration: the (cid:181)523 patent, including the specification and claims
`
`(Ex. 1001); the prosecution history of the (cid:181)523 patent in the United States Patent
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`& Trademark Office ((cid:179)the PTO(cid:180)) (Ex. 1004); Patent Owner(cid:182)s Preliminary
`
`Response (Paper No. 9); Decision Granting Institution of Post-Grant Review
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`(Paper No. 22); Declaration of Jacob Baker, Ph.D., P.E. (Ex. 1002); Curriculum
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`Vitae of Jacob Baker, Ph.D., P.E. (Ex. 1003); File History of U.S. Patent No.
`
`8,269,523 (Ex. 1004); PCT Publication No. WO2008/147928 (Ex. 1005); U.S.
`
`Patent No. 10,003,553 (Ex. 1006); Body of PCT Application No.
`
`PCT/US08/64605 as filed ((cid:179)the (cid:182)605 PCT(cid:180)) (Ex. 1007); U.S. Patent No.
`
`6,940,308 ((cid:179)Wong(cid:180)) (Ex. 1008); PCT Publication No. WO 2008/109756 A1
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`((cid:179)Konda ‘756 PCT(cid:180)) (Ex. 1009); As-filed Disclosure of U.S. Provisional
`
`Application 60/984,724 (Excerpt from File History of U.S. Provisional
`
`Application No. 60/984,724 (Ex. 1039)) (Ex. 1010); U.S. Patent No.
`
`8,270,400 (Ex. 1011); PCT Application No. PCT/US08/56064 (Ex. 1012);
`
`File History of U.S. Provisional Application No. 60/905,526 (Ex. 1013); File
`
`History of U.S. Provisional Application No. 60/940,383 (Ex. 1014); U.S.
`
`Patent No. 8,170,040 (Ex. 1015); PCT Application No. PCT/US08/64603
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`(Ex. 1016); File History of U.S. Provisional Application No. 60/940,387 (Ex.
`
`1017); File History of U.S. Provisional Application No. 60/940,390 (Ex.
`
`1018); U.S. Patent No. 8,363,649 (Ex. 1019); PCT Application No.
`
`PCT/US08/64604 (Ex. 1020); File History of U.S. Provisional Application
`
`No. 60/940,389 (Ex. 1021); File History of U.S. Provisional Application No.
`
`60/940,391 (Ex. 1022); File History of U.S. Provisional Application No.
`
`60/940,392 (Ex. 1023); File History of U.S. Provisional Application No.
`
`60/940,394 (Ex. 1026); File History of U.S. Provisional Application No.
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`61/252,603 (Ex. 1029); File History of U.S. Provisional Application No.
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`61/252,609 (Ex. 1030); File History of U.S. Provisional Application No.
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`60/984,724 (Ex. 1039); and all documents cited in this declaration.
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`Page 6 of 18
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`14.
`I also relied on my own training, knowledge, and experience in the
`
`field to which the (cid:181)523 patent is directed, along with my understanding of how one
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`of ordinary skill in the art would have understood the disclosure of the (cid:181)523 patent
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`at the time of the invention which is about May 25, 2007, the filing date of
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`the (cid:181)394 Provisional. My opinions reflect how one of ordinary skill in the art
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`would have understood the (cid:181)523 patent, the alleged prior art to the patent, and
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`the state of the art at the time of the invention.
`
`IV. THE LEVEL OF SKILL IN THE ART TO WHICH THE (cid:181)523
`PATENT PERTAINS AND THE TECHNICAL BACKGROUND
`FROM THE VIEWPOINT OF A POSITA AT THE TIME OF THE
`INVENTION
`15.
`
`It is my understanding that I must address the issues set forth in this
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`declaration from the viewpoint of a POSITA to which the (cid:181)523 patent pertains at
`
`the time of the invention.
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`16.
`
`In my opinion, one of ordinary skill in the art to which the (cid:181)523 patent
`
`pertains would have had a master(cid:182)s degree in electrical/computer engineering or a
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`similar field, and at least two to three years of experience with integrated circuits,
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`interconnection networks and Field Programmable Gate Arrays. In the pertinent
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`field of the invention, more education can supplement practical experience and
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`vice versa.
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`Page 7 of 18
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`17.
`I will now list some of my qualifications from the viewpoint of a
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`POSITA to which the (cid:181)523 patent pertains at the time of the invention.
`
`18.
`
`I served as associate Guest Editor, Special Issue of IEICE
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`Transactions on Information and Systems on Hardware/Software Support for High
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`Performance Scientific and Engineering Computing, July 2004. I served as
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`Conference or Symposium Chair in six of the relevant conferences and as
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`workshop chair in more than twenty workshops in the area of interconnection
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`networks. I served as program committee member in more than forty conferences.
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`19.
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`I taught two undergraduate courses and more than ten graduate
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`courses where integrated circuits and interconnection networks is an integral part
`
`of the subject matter. I also have created more than five courses where integrated
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`circuits and interconnection networks is an integral part.
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`20.
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`I have supervised more than five doctoral dissertations and more than
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`five Master(cid:182)s theses.
`
`21.
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`I have contributed to more than eight book chapters and published
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`more than fifteen papers in refereed journal papers, more than fifty papers in
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`refereed conference papers and more than ten refereed workshops related to
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`integrated circuits and interconnection networks.
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`22.
`I have given more than thirty invited talks at Academic Institutions,
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`Industries, Research Laboratories, conferences and workshops related to integrated
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`circuits and interconnection networks.
`
`V. THE (cid:181)523 (cid:51)ATENT
`23.
`I have read and analyzed the (cid:181)523 patent and its prosecution history. I
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`understand that the (cid:181)523 patent titled (cid:179)VLSI Layouts of Fully Connected
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`Generalized Networks(cid:180) pertains to Very Large Scale Integration ((cid:179)VLSI(cid:180)) layouts
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`in an integrated circuit based on a two-dimensional grid comprising only horizontal
`
`and vertical tracks (Ex. 1001). The (cid:181)523 patent describes VLSI layouts of
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`generalized multi-stage networks for broadcast, unicast, and multicast connections
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`using only horizontal and vertical links. Id. at 3:21(cid:177)24. The VLSI layouts employ
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`shuffle exchange links, where outlet links of cross links from switches in a stage in
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`one sub-integrated circuit block are connected to inlet links of switches in the
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`succeeding stage in another sub-integrated circuit block. Id. at 3:24(cid:177)28. The cross
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`links are either vertical links or horizontal links, and vice versa. Id. at 3:28(cid:177)29.
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`24.
`
` In one embodiment, the sub-integrated circuit blocks are arranged in
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`a hypercube arrangement in a two-dimensional plane. Id. at 3:29(cid:177)31. The VLSI
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`layouts exploit the benefits of significantly lower cross points, lower signal
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`latency, lower power, and full connectivity with significantly fast compilation. Id.
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`at 3:31(cid:177)34.
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`25.
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`26.
`
` The (cid:181)523 patent includes a single independent claim, i.e., claim 1.
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` I am informed and understand that a dependent claim is narrower
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`than the claims from which it depends because it includes additional limitations.
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`Thus, claims 2 - 48, which depend, either directly, or ultimately, from independent
`
`claim 1, are narrower in scope than claim 1.
`
`VI. PATENTABILITY OF THE (cid:181)523 PATENT: PARTICULARLY THE
`EARLIEST EFFECTIVE FILING DATE OF THE (cid:181)523 (cid:51)A(cid:55)E(cid:49)(cid:55)
`27. The (cid:181)523 Patent (Ex. 1001) issued from patent application No.
`
`12/601,275 ((cid:179)the (cid:181)275 application(cid:180), Ex. 1004) filed on November 22, 2009. (As
`
`noted above, the (cid:181)523 Patent has only one independent claim, i.e., claim 1.) The
`
`(cid:181)523 Patent is a national stage application of international application PCT
`
`Application No. PCT/US2008/064605 ((cid:179)the (cid:181)605 PCT application(cid:180)), (Ex. 1007),
`
`filed May 22, 2008 which in turn is a continuation-in-part and claims priority to the
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`(cid:181)394 Provisional, filed May 25, 2007. No new subject matter was added to the
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`specification of the (cid:181)275 application which issued as the (cid:181)523 Patent. Thus, the
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`effective filing date of the (cid:181)523 Patent is the earliest application for which priority
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`was claimed, namely, May 25, 2007.
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`28. Petitioner argued that the (cid:181)605 PCT and the (cid:182)394 Provisional
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`(collectively, (cid:179)the priority applications(cid:180)) do not provide support for an integrated
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`circuit device that includes a routing network comprising a plurality of stages y
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`that also includes the other limitations of claim 1 such as pluralities of forward
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`connecting links and pluralities of backward connecting links, when there is only
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`one stage (y=1). (Petition at 6(cid:177)20.)
`
`29. Relying on Dr. Baker(cid:182)s declaration (Ex. 1002), I understand that the
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`Board agreed with Petitioner(cid:182)s position that the (cid:179)said routing network comprising a
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`plurality of stages y, in each said sub-integrated circuit block, starting from the
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`lowest stage of 1 to the highest stage of y, where y≧1(cid:180) limitation of claim 1 lacks
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`written description support in the priority applications when y=1.
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`30.
`
`I have been asked by Patent Owner, to consider whether a
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`POSITA would have understood that the named inventor of the (cid:181)523 patent
`
`was in possession of the subject matter recited in claim 1 of the (cid:181)523 patent
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`with written description support in the disclosures of the (cid:181)605 PCT and the
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`(cid:182)394 Provisional. In my opinion, a POSITA reviewing the (cid:181)605 PCT and the
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`(cid:181)394 Provisional would in fact understand that the named inventor was in
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`possession of the subject matter recited in claim 1 particularly with respect to
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`(cid:179)said routing network comprising a plurality of stages y, in each said sub-
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`integrated circuit block, starting from the lowest stage of 1 to the highest stage of
`
`y, where y≧1(cid:180) as described below, in view of the following figures on the (cid:181)523
`
`Patent.
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`
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`31. The (cid:181)523 patent discloses VLSI layouts of fully connected generalized
`
`multi-stage networks, including a butterfly fat tree network, for broadcast, unicast,
`
`and multicast connections using only horizontal and vertical links. In my opinion,
`
`a POSITA would have understood a fully connected butterfly fat tree network, as
`
`also disclosed in the (cid:181)523 patent, (cid:11)
`log
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`
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`(cid:12)N2
` stages in a row (or block), where N is the
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`number of inputs or outputs. Accordingly, for example, there will be one stage
`
`when there is one block as illustrated in FIG. 2A1-3 of the priority applications Ex.
`
`1007, 7:10-21; Ex. 1026, 4:4-15. In my opinion, a POSITA would have
`
`understood that when there is one block there are no forward connecting links and
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`no backward connecting links as illustrated in FIG. 2A3 of the (cid:181)523 patent, which
`
`is the smallest butterfly fat tree network.
`
`32. Claim 1 of the (cid:181)523 patent first recites stages and switches as follows:
`
`Said routing network comprising of a plurality of stages y, in each said sub-
`integrated circuit block, starting from the lowest stage of 1 to the highest
`
`Said routing network comprising a plurality of switches of size d×d, where
`
`stage of y, where y≧1; and
`d≧2, in each said stage and each said switch of size d×d having d inlet links
`
`and d outlet links;
`
`33.
`
` Claim 1 subsequently recites forward connecting links and backward
`
`connecting links as follows:
`
`(cid:179)Said each sub-integrated circuit block comprising a plurality of
`forward connecting links connecting from switches in lower stage to
`switches in the immediate succeeding higher stage, and also comprising a
`plurality of backward connecting links connecting from switches in higher
`stage to switches in the immediate preceding lower stage;(cid:180)
`
`In my opinion, a POSITA would understand that a plurality of
`
`34.
`
`forward connecting links are connected from a stage when there is an immediate
`
`succeeding stage and a plurality of backward connecting links are connected from
`
`a stage when there is an immediate preceding stage. That is, a POSITA would
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`Page 13 of 18
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`Exhibit 2025
`Patent 8,269,523
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`Declaration of Vipin Chaudhary, Ph.D.
`understand that a plurality of forward connecting links are not connected from a
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`stage when there is no immediate succeeding stage and a plurality of backward
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`connecting links are not connected from a stage when there is no immediate
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`preceding stage.
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`35. Accordingly, for example, referring to FIG. 1B below, as disclosed in
`
`the priority applications Ex. 1007, 5:17-21; Ex. 1026, 2:12-16, the stage denoted
`
`by 160 ((cid:179)Stage 5(cid:180)) has a preceding stage denoted by 150 & 170 ((cid:179)Stage 4(cid:180)), and so
`
`backward connecting links denoted by ML(5,1) - ML(5,64), etc. are connected
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`from Stage 5 and Stage 4. However, Stage 5 has no succeeding stage and so no
`
`forward connecting links are connected from Stage 5 as illustrated by FIG. 1B.
`
`Similarly the stage denoted by 110 & 120 ((cid:179)Stage 1(cid:180)) has a succeeding stage
`
`denoted by 130 & 190 ((cid:179)Stage 2(cid:180)), and so forward connecting links denoted by
`
`ML(1,1) - ML(1,64), etc. are connected from Stage 1 and Stage 2. However, Stage
`
`1 has no preceding stage, and so no backward connecting links are connected from
`
`Stage 1 as illustrated in FIG. 1B.
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`36. Similarly, in my opinion, a POSITA would understand that,
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`referring to FIG. 2A3, above, there is one stage ((cid:179)Stage 1(cid:180)) in Block 1_2. Since
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`Stage 1 has no succeeding stage, no forward connecting links are connected from
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`Stage 1. Also, since Stage 1 has no preceding stage, no backward connecting links
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`are connected from Stage 1.
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`Page 14 of 18
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`IPR2020-00261
`Patent 8,269,523
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`Exhibit 2025
`Declaration of Vipin Chaudhary, Ph.D.
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`37. Essentially, in my opinion, a POSITA would understand that the
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`first stage of a butterfly fat tree network has no preceding stage, and so no
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`backward connecting links are connected from the first stage. Also the last stage of
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`a butterfly fat tree network has no succeeding stage, and so no forward connecting
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`links are connected from the last stage. In my opinion, a POSITA would
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`understand that when there is one stage in a butterfly fat tree network as illustrated
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`in FIG. 2A1-3 of the priority applications, it is the first stage as well as the last
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`stage. Furthermore, the one stage has neither a preceding stage nor a succeeding
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`stage, and so no forward connecting links are connected from the stage and no
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`backward connecting links are connected from the stage. In my opinion, for a
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`Page 15 of 18
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`IPR2020-00261
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`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`POSITA this is straight forward to understand. Accordingly, no experimentation is
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`needed to understand it, let alone undue experimentation.
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`38. Accordingly, in my opinion, a POSITA reviewing the (cid:182)605 PCT
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`and the (cid:182)394 Provisional would have in fact understood that the named
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`inventor was in possession of the subject matter recited in claim 1 of the (cid:181)523
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`patent, particularly with respect to (cid:179)said routing network comprising a plurality of
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`stages y, in each said sub-integrated circuit block, starting from the lowest stage of
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`1 to the highest stage of y, where y≧1(cid:180) and that the (cid:181)523 patent is entitled to the
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`benefit of the May 25, 2007 filing date of the (cid:181)394 Provisional.
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`VII. CONCLUSION
`39. For the reasons stated above, it is my opinion that the (cid:181)523 patent is
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`entitled to the benefit of the May 25, 2007 filing date of the (cid:181)394 Provisional.
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`40.
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`I hereby declare that all statements made herein of my own
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`knowledge are true and that all statements made on information and belief are
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`believed to be true; that these statements were made with knowledge that willful
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`false statements and the like so made are punishable by fine or imprisonment, or
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`both, under Section 1001 of Title 18 of the United States Code.
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`Dated: August 10, 2020
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`Respectfully submitted,
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`Vipin Chaudhary, Ph.D
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`Page 16 of 18
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