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`Exhibit 2011
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
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`FLEX LOGIX TECHNOLOGIES INC,
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`Petitioner
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`V.
`
`VENKAT KONDA,
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`Patent Owner
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`____________
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`Case PGR2019-00037
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`Patent 10,003,553 B2
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`_________
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`
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`DECLARATION OF VENKAT KONDA IN SUPPORT OF PATENT
`OWNER’S REPLY TO PETITIONER’S OPPOSITION TO PATENT
`OWNER’S MOTION TO EXCLUDE PURSUANT TO 37 C.F.R. § 42.64
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`Page 1 of 6 IPR2020-00260
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`VENKAT KONDA EXHIBIT 2023
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`
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`Exhibit 2011
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`PGR2019-00037
`Patent 10,003,553 Declaration of Venkat Konda in Support of Reply
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`I, Venkat Konda, make this declaration in connection with the proceedings
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`identified above.
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`1.
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`I am the sole inventor of U.S. Patent No. 10,003,553 (“the ‘553
`
`Patent”). I submit this declaration in support of Patent Owner’s reply to Petitioner’s
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`opposition to Patent Owner’s Motion to Exclude Dr. Baker’s Declaration in the
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`Petition of the Post Grant Review instituted in Case PGR2019-00037 filed by
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`Petitioner Flex Logix Technologies Inc. (“Petitioner”) challenging claims 1-20
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`(the “Challenged Claims”) of the ’553 Patent.
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`2.
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`I earned a Bachelor of Technology in Electronics and
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`Communications Engineering from Nagarjuna University in Vijayawada, India
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`in1986, a Master of Technology in Electrical Engineering from the Indian Institute
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`of Technology in Kharagpur, India in 1988, and a Ph.D. in Computer Science and
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`Engineering from the University of Louisville, Kentucky in 1992.
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`3.
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`I have over 25 years of Research and Development and Management
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`experience in various semiconductor integrated circuit and systems companies
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`with extensive experience in interconnection networks including nCube
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`Corporation from March 1992 to March 1995, Mitsubishi Electric Research Labs
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`and VSIS Inc. from April 1995 to July 1998, Infineon Technologies from July
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`1998 to December 2000, and Velio Communications from December 2000 to June
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`
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`Page 2 of 6
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`Page 2 of 6 IPR2020-00260
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`VENKAT KONDA EXHIBIT 2023
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`
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`Exhibit 2011
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`PGR2019-00037
`Patent 10,003,553 Declaration of Venkat Konda in Support of Reply
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`2001. I was the founder of Teak Networks Inc. in August 2001 and CEO from
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`August 2001 until March 2007. I was also co-founder of Teak Technologies Inc.
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`founded in February 2005 and CTO from February 2005 until April 2006.
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`4.
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`In 1994-95, I taught graduate courses related to interconnection
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`networks as an adjunct faculty member in the department of Computer Science
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`and Engineering, Santa Clara University, Santa Clara, CA.
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`5.
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`I founded Teak Networks Inc. after solving an approximately 60-year-
`
`old research problem by inventing strictly and rearrangeably non-blocking multi-
`
`cast solutions for Clos Networks. I have been granted several related patents for
`
`that technology including U.S. Patents No. 6,885,669, 6,868,084, 7,424,010,
`
`7,424,011 and 7,378,938 by the United States Patent and Trademark Office
`
`(“USPTO”).
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`6.
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`I founded Konda Technologies, Inc. (“Konda Tech”), in 2007, after
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`solving approximately 30-year-old open research problems by inventing strictly
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`and rearrangeably non-blocking multi-cast solutions for Benes and Butterfly Fat
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`Tree Networks and the seminal 2D-layouts to implement those networks using
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`only vertical and horizontal wires. I am a pioneer in multi-stage based field-
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`programmable gate array (“FPGA”) routing fabric and interconnection networks
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`technology. Konda Tech was founded to commercialize semiconductor integrated
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`circuits and system level interconnection technology solutions based on my work.
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`
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`Page 3 of 6
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`Page 3 of 6 IPR2020-00260
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`VENKAT KONDA EXHIBIT 2023
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`
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`Exhibit 2011
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`PGR2019-00037
`Patent 10,003,553 Declaration of Venkat Konda in Support of Reply
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`7.
`
`Konda Tech licenses chip and system level interconnection
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`technology solutions to the commercial semiconductor industry. To date, Konda
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`Tech has fifteen patents relating to the technology. Konda Tech has licensed
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`FPGA interconnection architecture patents to two FPGA chip vendors, the first of
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`which has made and sold three generations of chips using the 2D-layouts disclosed
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`in the ‘553 Patent.
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`8.
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`A selected list of some of my publications is attached in Appendix A.
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`I hereby declare under penalty of perjury under the laws of the United States of
`
`America that all statements made herein of my own knowledge are true and that all
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`statements made herein on information and belief are believed to be true, and that
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`these statements were made with the knowledge that willful false statements and
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`the like so made are punishable by fine or imprisonment, or both, under Section
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`1001 of Title 18 of the United States Code.
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`Dated: August 3, 2020
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`Respectfully submitted,
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` /Venkat Konda/
`Venkat Konda
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`Page 4 of 6
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`Page 4 of 6 IPR2020-00260
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`VENKAT KONDA EXHIBIT 2023
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`
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`Exhibit 2011
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`PGR2019-00037
`Patent 10,003,553 Appendix A of Declaration of PO in support of Reply
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`PARTIAL LIST OF SOME SELECTED PUBLICATATIONS
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`
`
`1) Rearrangeably nonblocking multicast multi-stage networks
` Priority Date: September 27, 2001
` US Patent Application Number: 09/967,815
` US Patent Number: US 6,885,669
` Date of Patent: April 26, 2005
`2) Strictly nonblocking multicast multi-stage networks
` Priority Date: September 27, 2001
` US Patent Application Number: 09/967,106
` US Patent Number: US 6,868,084
` Date of Patent: March 15, 2005
`3) Strictly non-blocking Multicast Multi-split Linear-time Multi-stage
`Networks
` Priority Date: September 6, 2003
` US Patent Application Number: 10/933,900
` US Patent Number: US 7,424,010
` Date of Patent: September 9, 2008
`4) Rearrangeably nonblocking multicast multi-stage networks
` Priority Date: September 27, 2001
` US Patent Application Number: 10/999,757
` US Patent Number: US 7,424,011
` Date of Patent: September 9, 2008
`5) Strictly nonblocking multicast multi-stage networks
` Priority Date: September 27, 2001
` US Patent Application Number: 10/999,649
` US Patent Number: US 7,378,938
` Date of Patent: March 27, 2008
`6) Fully Connected Generalized Multi-stage Networks
` Priority Date: March 6, 2007
` US Patent Application Number: 12/530,207
` US Patent Number: US 8,270,400
` Date of Patent: September 18, 2012
`7) Fully Connected Generalized Butterfly Fat Tree Networks
` Priority Date: March 25, 2007
` US Patent Application Number: 12/601,273
` US Patent Number: US 8,170,040
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`Page 5 of 6
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`Page 5 of 6 IPR2020-00260
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`VENKAT KONDA EXHIBIT 2023
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`
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`Exhibit 2011
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`PGR2019-00037
`Patent 10,003,553 Appendix A of Declaration of PO in support of Reply
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` Date of Patent: May 1, 2012
`8) Fully Connected Generalized Multi-link Multi-stage Networks
` Priority Date: March 25, 2007
` US Patent Application Number: 12/601,274
` US Patent Number: US 8,363,649
` Date of Patent: January 29, 2013
`9) VLSI Layouts of Fully Connected Generalized Networks
` Priority Date: March 25, 2007
` US Patent Application Number: 12/601,275
` US Patent Number: US 8,269,523
` Date of Patent: September 18, 2012
`10) VLSI Layouts of Fully Connected Generalized and Pyramid Networks
`with Locality Exploitation
` Priority Date: October 16, 2009
` US Patent Application Number: 13/502,207
` US Patent Number: US 8,898,611
` Date of Patent: November 25, 2014
`11) VLSI Layouts of Fully Connected Generalized and Pyramid Networks
`with Locality Exploitation
` Priority Date: October 16, 2009
` US Patent Application Number: 14/522,599
` US Patent Number: US 9,529,958
` Date of Patent: December 27, 2016
`12) VLSI Layouts of Fully Connected Generalized and Pyramid Networks
`with Locality Exploitation
` Priority Date: October 16, 2009
` US Patent Application Number: 15/351,453
` US Patent Number: US 10,050,904
` Date of Patent: August 14, 2018
`13) VLSI Layouts of Fully Connected Generalized and Pyramid Networks
`with Locality Exploitation
` Priority Date: October 16, 2009
` US Patent Application Number: 16/029,645
` US Patent Number: 10,554,583
` Date of Patent: February 4, 2020
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`Page 6 of 6
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`Page 6 of 6 IPR2020-00260
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`VENKAT KONDA EXHIBIT 2023
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