Paper 22
`Trials@uspto.gov
`571-272-7822 Entered: August 3, 2020
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`
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`FLEX LOGIX TECHNOLOGIES, INC.,
`Petitioner,
`
`v.
`
`VENKAT KONDA,
`Patent Owner.
`____________
`
`
`IPR2020-00260
`Patent 8,269,523 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, THOMAS L. GIANNETTI, and
`JO-ANNE M. KOKOSKI, Administrative Patent Judges.
`
`KOKOSKI, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`Trials@uspto.gov
`571-272-7822 Entered: August 3, 2020
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`FLEX LOGIX TECHNOLOGIES, INC.,
`Petitioner,
`
`v.
`
`VENKAT KONDA,
`Patent Owner.
`____________
`
`
`IPR2020-00260
`Patent 8,269,523 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, THOMAS L. GIANNETTI, and
`JO-ANNE M. KOKOSKI, Administrative Patent Judges.
`
`KOKOSKI, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`IPR2020-00260
`Patent 8,269,523 B2
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`
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`I. INTRODUCTION
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`Flex Logic Technologies, Inc., (“Petitioner”) filed a Petition to
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`institute an inter partes review of claims 1, 15–18, 20–22, 32, and 47 (the
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`“challenged claims”) of U.S. Patent No. 8,269,523 B2 (“the ’523 patent,”
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`Ex. 1001). Paper 1 (“Pet.”). Patent Owner Venkat Konda filed a
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`Preliminary Response. Paper 8 (“Prelim. Resp.”). With Board
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`authorization, Petitioner filed a reply addressing certain issues raised in the
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`Preliminary Response (“Reply,” Paper 12), and Patent Owner filed a Sur-
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`reply (“Sur-Reply,” Paper 15). At the Board’s direction (Paper 11),
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`Petitioner filed a Notice explaining its reasons for filing multiple petitions
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`challenging the claims of the ’523 patent. Paper 14 (“Notice”). Patent
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`Owner filed a Reply to Petitioner’s Notice. Paper 18 (“Notice Reply”).
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`Institution of an inter partes review is authorized by statute when “the
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`information presented in the petition . . . and any response . . . shows that
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`there is a reasonable likelihood that the petitioner would prevail with respect
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`to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314
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`(2018); see 37 C.F.R. § 42.4 (2019). Upon consideration of the Petition, the
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`Preliminary Response, the Reply, the Sur-Reply, the Notice, the Notice
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`Reply, and the evidence of record, we determine that Petitioner has
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`established a reasonable likelihood of prevailing with respect to the
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`unpatentability of at least 1 claim of the ’523 patent. Accordingly, for the
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`reasons that follow, we institute an inter partes review of claims 1, 15–18,
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`20–22, 32, and 47 of the ’523 patent.
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`A. Related Proceedings
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`Petitioner identifies the following district court proceedings involving
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`the ’523 patent: Konda Technologies Inc. v. Flex Logix Technologies, Inc.,
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`No. 5:18-cv-07581 (N.D. Cal.). Pet. 1.
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`The ’523 patent is the subject of two other inter partes review
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`proceedings filed by Petitioner: IPR2020-00261 (“261 IPR”) and IPR2020-
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`00262 (“262 IPR”). Prelim. Resp. 1, n.1. Also, two post grant proceedings
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`brought by the Petitioner challenging a related patent are pending:
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`PGR2019-00037, and PGR2019-00042. Pet. 1. A third petition for post
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`grant review of that related patent (PGR2019-00040) was denied. Id. at 1–2.
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`Patent Owner additionally identifies a pending application to reissue
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`the ’523 patent: U.S. Patent Application No. 16/202,067, filed November 27,
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`2018 (“the ’067 reissue application”). Paper 5, 2.
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`B. Real Parties-in-Interest
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`Petitioner identifies Flex Logix Technologies, Inc. as the real party-in-
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`interest. Pet. 1. Patent Owner identifies himself, Venkat Konda, as the real
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`party-in-interest. Paper 5, 1.
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`C. The ’523 Patent
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`
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`The ’523 patent is titled “VLSI Layouts of Fully Connected
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`Generalized Networks.” Ex. 1001, code (54). The most commonly used
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`VLSI (Very Large Scale Integration) layout in an integrated circuit is based
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`on a two-dimensional grid model comprising only horizontal and vertical
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`tracks. Id. at 2:40–42. The ’523 patent describes VLSI layouts of
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`generalized multi-stage networks for broadcast, unicast, and multicast
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`connections using only horizontal and vertical links. Id. at 3:21–24. The
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`VLSI layouts employ shuffle exchange links, where outlet links of cross
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`links from switches in a stage in one sub-integrated circuit block are
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`connected to inlet links of switches in the succeeding stage in another sub-
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`integrated circuit block. Id. at 3:24–28. The cross links are either vertical
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`links or horizontal, and vice versa. Id. at 3:28–29.
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`
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`In one embodiment, the sub-integrated circuit blocks are arranged in a
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`hypercube arrangement in a two-dimensional plane. Id. at 3:29–31. The
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`VLSI layouts exploit the benefits of significantly lower cross points, lower
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`signal latency, lower power, and full connectivity with significantly fast
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`compilation. Id. at 3:31–34.
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`D. Illustrative Claim
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`Petitioner challenges claims 1, 15–18, 20–22, 32, and 47 of the ’523
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`patent. Pet. 1, 3–4. Claim 1 is the only independent claim, and is
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`reproduced below.
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`1. An integrated circuit device comprising a plurality of
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`sub-integrated circuit blocks and a routing network, and
`Said each plurality of sub-integrated circuit blocks comprising a
`plurality of inlet links and a plurality of outlet links; and
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`Said routing network comprising of a plurality of stages y,
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`in each said sub-integrated circuit block, starting from the lowest
`stage of 1 to the highest stage of y, where y≧1; and
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`Said routing network comprising a plurality of switches of
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`size d×d, where d≧2, in each said stage and each said switch of
`size d×d having d inlet links and d outlet links; and
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`Said plurality of outlet links of said each sub-integrated
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`circuit block are directly connected to said inlet links of said
`switches of its corresponding said lowest stage of 1, and said
`plurality of inlet links of said each sub-integrated circuit block
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`are directly connected from said outlet links of said switches of
`its corresponding said lowest stage of 1; and
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`Said each sub-integrated circuit block comprising a
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`plurality of forward connecting links connecting from switches
`in a lower stage to switches in its immediate succeeding higher
`stage, and also comprising a plurality of backward connecting
`links connecting from switches in a higher stage to switches in
`its immediate preceding lower stage; and
`
`Said each sub-integrated circuit block comprising a
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`plurality straight links in said forward connecting links from
`switches in said each lower stage to switches in its immediate
`succeeding higher stage and a plurality cross links in said
`forward connecting links from switches in said each lower stage
`to switches in its immediate succeeding higher stage, and further
`comprising a plurality of straight links in said backward
`connecting links from switches in said each higher stage to
`switches in its immediate preceding lower stage and a plurality
`of cross links in said backward connecting links from switches
`in said each higher stage to switches in its immediate preceding
`lower stage,
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`said plurality of sub-integrated circuit blocks arranged in
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`a two-dimensional grid of rows and columns, and
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`said all straight links are connecting from switches in each
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`said sub-integrated circuit block are connecting to switches in the
`same said sub-integrated circuit block; and said all cross links are
`connecting as either vertical or horizontal links between switches
`in two different said sub-integrated circuit blocks which are
`either placed vertically above or below, or placed horizontally to
`the left or to the right,
`
`
`each said plurality of sub-integrated circuit blocks
`comprising same number of said stages and said switches in each
`said stage, regardless of the size of said two-dimensional grid so
`that each said plurality of sub-integrated circuit block with its
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`corresponding said stages and said switches in each stage is
`replicable in both vertical direction or horizontal direction of said
`two-dimensional grid.
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`Ex. 1001, 35:23–36:14.
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`E. The Asserted Grounds of Unpatentability
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`Petitioner asserts the challenged claims are unpatentable on the
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`following grounds.
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`Claims Challenged Statutory Basis
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`1, 16, 20–22, 32
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`15, 17
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`18, 47
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`References
`Published PCT Application
`No. WO 2008/109756
`(“the ’756 PCT,” Ex. 1009)
`35 U.S.C. § 103 The ’756 PCT
`The ’756 PCT and U.S. Patent
`No. 6,940,308 B2 (“Wong,”
`Ex. 1008)
`
`35 U.S.C. § 102
`
`35 U.S.C. § 103
`
`Pet. 3–4. Petitioner relies on the Declaration of Jacob Baker, Ph.D., P.E.,
`
`(“the Baker Declaration,” Ex. 1002) in support of its contentions.
`
`A. Level of Ordinary Skill in the Art
`
`II. ANALYSIS
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`Petitioner contends that a person having ordinary skill in the art
`
`(“POSITA”) “would have had a master’s degree in electrical engineering or
`
`a similar field, and at least two to three years of experience with integrated
`
`circuits and networks,” and that “[m]ore education can supplement practical
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`experience and vice versa.” Pet. 23 (citing Ex. 1002 ¶¶ 18–19). Patent
`
`Owner agrees that a POSITA would have had a master’s degree in electrical
`
`engineering or a similar field, but argues that a POSITA would also have
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`had “at least two to three years of experience with integrated circuits,
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`interconnection networks and Field Programmable Gate Arrays.” Prelim.
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`Resp. 8 (emphasis omitted). According to Patent Owner, “interconnection
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`networks used in Field Programmable Gate Arrays (‘FPGAs’) is a separate
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`field requiring VLSI layouts and multicast solutions,” and “some of the key
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`requirements for the FPGA interconnects are not known in academia unless
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`[a] POSITA has worked in the industry.” Id. at 8–9.
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`We agree with the parties that a POSITA would have had a master’s
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`degree in electrical engineering or a similar field, and experience in the field
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`of integrated networks, which is consistent with the level of skill in the art at
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`the time of the invention as reflected in the prior art in this proceeding. See
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`Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (explaining that
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`specific findings regarding ordinary skill level are not required “where the
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`prior art itself reflects an appropriate level and a need for testimony is not
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`shown” (quoting Litton Indus. Prods., Inc. v. Solid State Sys. Corp., 755
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`F.2d 158, 168 (Fed. Cir. 1985))). Our determination regarding Petitioner’s
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`challenge does not turn on the differences between Petitioner’s and Patent
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`Owner’s definitions, and we note that our conclusion would be the same
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`under either definition.
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`We note that Patent Owner argues that Petitioner’s declarant,
`
`Dr. Baker, is not qualified to testify in this proceeding because he is neither
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`a person of ordinary skill, nor an expert, in the relevant art. Prelim. Resp. 6–
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`11; Notice Reply 5. There is no requirement, however, that the expert’s
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`experience perfectly match the relevant field, or that that the expert is a
`
`person of ordinary skill in the art. The August 13, 2018, update to our Trial
`
`Practice Guide states:
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`An expert witness must be qualified as an expert by
`knowledge, skill, experience, training, or education to testify in
`the form of an opinion. Fed. R. Evid. 702. There is, however, no
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`requirement of a perfect match between the expert’s experience
`and the relevant field. SEB S.A. v. Montgomery Ward & Co., 594
`F.3d 1360, 1373 (Fed. Cir. 2010). A person may not need to be
`a person of ordinary skill in the art in order to testify as an expert
`under Rule 702, but rather must be “qualified in the pertinent
`art.” Sundance, Inc. v. DeMonte Fabricating Ltd., 550 F.3d 1356,
`1363–64 (Fed. Cir. 2008).
`
`See Notice of Update to Office Patent Trial Practice Guide, 83 Fed. Reg.
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`156, (Aug. 13, 2018) (text of update available at
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`https://www.uspto.gov/sites/default/files/documents/2018_Revised_Trial_Pr
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`actice_Guide.pdf).
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`Dr. Baker testifies as to his education and qualifications and provides
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`his curriculum vitae. See Ex. 1002 ¶¶ 3–12; Ex. 1003. At this preliminary
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`stage, we cannot say that Dr. Baker’s scientific, technical, and other
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`specialized knowledge will not be helpful in understanding the evidence.
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`See Fed. R. Evid. 702(a). On this record, we are not persuaded that
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`Dr. Baker’s testimony should be disregarded.
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`B. Claim Construction
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`We construe each claim “in accordance with the ordinary and
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`customary meaning of such claim as understood by one of ordinary skill in
`
`the art and the prosecution history pertaining to the patent.” 37 C.F.R.
`
`§ 42.100(b). Under this standard, claim terms are generally given their plain
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`and ordinary meaning as would have been understood by a person of
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`ordinary skill in the art at the time of the invention and in the context of the
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`entire patent disclosure. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed.
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`Cir. 2005) (en banc). Only those terms in controversy need to be construed,
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`and only to the extent necessary to resolve the controversy. See Nidec
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`Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017
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`(Fed. Cir. 2017) (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200
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`F.3d 795, 803 (Fed. Cir. 1999)).
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`Petitioner “submits that for purposes of this proceeding no term
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`requires construction.” Pet. 25 (citing Ex. 1002 ¶ 39). Patent Owner
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`declines at this time to take a position regarding construction of the
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`challenged claims. Prelim. Resp. 55. For purposes of this Decision, based
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`on the record before us, we determine that none of the claim terms requires
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`an explicit construction.
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`C. Earliest Effective Filing Date of the ’523 Patent
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`The ’523 patent issued from U.S. Patent Application Serial
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`No. 12/601,275 (“the ’275 application”), which was filed on
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`November 22, 2009 as the national phase entry of PCT Application
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`No. PCT/US2008/064605 (“the ’605 PCT”), filed on May 22, 2008.
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`Ex. 1001, code (21), (22); Ex. 1004, 150. The ’275 application claims
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`priority to Provisional Application No. 60/940,394 (“the ’394 provisional”),
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`filed on May 25, 2007. Ex. 1001, code (60). Petitioner contends that
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`“the ’523 patent is not entitled to claim priority to May 25, 2007 or to May
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`22, 2008, because . . . the claims of the ’523 patent are not fully supported,
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`and also are not enabled, by the ’394 provisional or the ‘605 PCT
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`(collectively, ‘the priority applications’).” Pet. 4. Instead, Petitioner
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`contends that the earliest effective filing date for the ’523 patent is the
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`November 22, 2009 filing date of the ’275 application. Id. at 4–5.
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`Petitioner’s contentions are based on the limitation of claim 1
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`requiring “said routing network comprising a plurality of stages y, in each
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`said sub-integrated circuit block, starting from the lowest stage of 1 to the
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`highest stage of y, where y≧1.” Pet. 7–8. Specifically, Petitioner argues
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`that the ’605 PCT and the ’394 provisional (collectively, “the priority
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`applications”) do not provide support for an integrated circuit device that
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`includes a routing network comprising a plurality of stages y that also
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`includes the other limitations of claim 1 (such as the recited pluralities of
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`forward connecting links, backward connecting links, straight links, and
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`cross links) when there is only one stage (y=1). Id. at 8; see generally id.
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`at 6–20.
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`“It is elementary patent law that a patent application is entitled to the
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`benefit of the filing date of an earlier filed application only if the disclosure
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`of the earlier application provides support for the claims of the later
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`application, as required by 35 U.S.C. § 112.” PowerOasis, Inc. v. T-Mobile
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`USA, Inc., 522 F.3d 1299, 1306 (Fed. Cir. 2008) (citations omitted); see also
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`Research Corps. Techs. v. Microsoft Corp., 627 F.3d 859, 871–72 (Fed. Cir.
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`2010) (holding the later-filed application, with claims that were not limited
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`to a “blue noise mask,” was not entitled to the priority filing date of the
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`parent application, which was “limited to a blue noise mask”); ICU Med.,
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`Inc. v. Alaris Med. Sys., 558 F.3d 1368, 1377–78 (Fed. Cir. 2009) (holding
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`that “spikeless” claims “added years later during prosecution” were not
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`supported by the specification which “describe[d] only medical valves with
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`spikes”); Tronzo v. Biomet, Inc., 156 F.3d 1154, 1158–60 (Fed. Cir. 1998)
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`(holding the generic shaped cup claims of the later-filed child application
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`were not entitled to the filing date of the parent application that “disclosed
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`only a trapezoidal cup and nothing more”). “To satisfy the written
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`description requirement the disclosure of the prior application must convey
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`with reasonable clarity to those skilled in the art that, as of the filing date
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`sought, [the inventor] was in possession of the invention.” PowerOasis,
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`522 F.3d at 1306 (citations omitted). The sufficiency of written description
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`support is based on “an objective inquiry into the four corners of the
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`specification from the perspective of a person of ordinary skill in the art.”
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`Ariad Pharm., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010)
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`(en banc).
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`Petitioner has the burden to persuade us that the ’756 PCT is qualified
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`as prior art. We make our decision on institution based on whether the
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`information presented in the Petition and the Preliminary Response “shows
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`that there is a reasonable likelihood that the petitioner would prevail with
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`respect to at least 1 of the claims challenged in the petition.” 35 U.S.C.
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`§ 314(a). “In an inter partes review, the burden of persuasion is on the
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`petitioner to prove ‘unpatentability by a preponderance of the evidence,’ . . .
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`and that burden never shifts to the patentee.” Dynamic Drinkware, LLC v.
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`Nat’l Graphics, Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015) (quoting 35
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`U.S.C. § 316(e)). The burden of production can shift to the patent owner,
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`however. See id. at 1379. This shift happens where it is “warranted because
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`the patentee affirmatively seeks to establish a proposition not relied on by
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`the patent challenger and not a necessary predicate for the unpatentability
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`claim asserted—effectively an affirmative defense.” In re Magnum Oil
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`Tools Int’l, Ltd., 829 F.3d 1364, 1376 (Fed. Cir. 2016). Here, Petitioner
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`asserts that the ’756 PCT (either alone or in combination with Wong)
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`discloses each limitation of claims 1, 15–18, 20–22, 32, and 47, and the ’394
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`provisional and the ’605 PCT do not provide written description support for
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`those same claims. Thus, Petitioner has the burden of persuasion, based on
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`all of the evidence, on both of these assertions. See Dynamic Drinkware,
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`800 F.3d at 1378.
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`Petitioner argues that the priority applications do not disclose any sub-
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`integrated circuit blocks that have only one stage and pluralities of forward
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`and backward connecting links as required by claim 1. Pet. 13–14 (citing
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`Ex. 1002 ¶ 56). Petitioner recognizes that the priority applications illustrate
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`a network with one stage in Figures 2A1–2A3, but argues that the only links
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`shown therein are inlet and outlet links. Id. at 9–10 (citing Ex. 1007, 7:19–
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`21, Figs. 2A1–2A3; Ex. 1026, 4:13–15, Figs. 2A1–2A3; Ex. 1002 ¶ 50)
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`(emphasis omitted). Relying on Dr. Baker’s testimony, Petitioner argues
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`that a POSITA would have recognized that these inlet and outlet links are
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`different than “forward connecting links” and “backward connecting links,”
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`at least because claim 1 “recites ‘inlet links’ and ‘outlet links’ separately
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`from ‘forward connecting links’ and ‘backward connecting links.’” Id. at 10
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`(citing Ex. 1001, 35:25–27, 35:43–49; Ex. 1002 ¶ 51). Petitioner further
`
`argues that a POSITA would have understood that there cannot be a plurality
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`of forward connecting links that connect switches in a lower stage to
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`switches in its immediate preceding stage, or a plurality of backward
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`connecting links that connect switches in a higher stage to switches in the
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`immediate preceding lower stage, when there is only one stage in the
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`network. Id. (citing Ex. 1002 ¶ 52).
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`Upon review of the disclosures of the priority applications, and based
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`on the preliminary record, we agree with Petitioner’s position that the
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`priority applications do not provide sufficient written description support for
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`the claims. More specifically, the priority applications do not reasonably
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`convey to a POSITA that the inventor was in possession of the claimed
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`routing network comprising a plurality of stages y when y=1 that also meets
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`the additional limitations of claim 1.
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`Figure 2A3 of the priority applications is reproduced below.
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`
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`Figure 2A3 depicts the VLSI layout of an example network described in the
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`provisional applications, with Block 1_2 comprising switch 1. Ex. 1007,
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`26:26–28; Ex. 1026, 22:23–25. Switch 1 consists of input switches IL1 and
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`IL2, and output switches OL1 and OL2. Ex. 1007, 26:28–29; Ex. 1026,
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`22:25–26. The priority applications state that Figure 2A3 illustrates all of
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`the connection links. Ex. 1007, 7:19–21; Ex. 1026, 4:13–15. Dr. Baker
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`testifies that the only links shown in Figure 2A3 are the inlet and outlet
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`links, and a POSITA “would have recognized that [there] are no forward
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`connecting links and no backward connecting links that connect switches in
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`higher and lower stages to each other.” Ex. 1002 ¶ 51 (emphasis omitted).
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`Dr. Baker further testifies that a POSITA
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`would have understood that there cannot be “a plurality of
`forward connecting links connecting from switches in a lower
`stage to switches in its immediate succeeding higher stage” if
`there is only one stage in the network. If there is only one stage,
`there is no “immediate succeeding higher stage.” Similarly, if
`there is only one stage, a person of ordinary skill in the art would
`have understood that there cannot be “a plurality of backward
`connecting links connecting from switches in a higher stage to
`switches in its immediate preceding lower stage.” If there is only
`one stage, there is no “immediate preceding lower stage.”
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`Ex. 1002 ¶ 52 (emphases added).
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`Patent Owner agrees that “FIG. 2A3 illustrates the 2D-layout for a
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`multistage network for N=2 wherein there is only one block . . . comprising
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`one stage.” Prelim. Resp. 18–19; see also id. at 33 (“[I]t is clear to a
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`POSITA that there is only one stage in the 2D-layout of a multi-stage
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`network disclosed in the ’523 Patent when there is only one block in the
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`network with N=2 as illustrated in FIG. 2A3.”). Patent Owner contends that
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`a POSITA would have understood that “there is only one stage when there is
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`only one block.” Id. at 22. Patent Owner’s arguments, as we understand
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`them, are directed only to the disclosure of a network with only one stage
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`(y=1). Id. at 15–39. Patent Owner does not address the other limitations of
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`claim 1, and does not point to any disclosures in the priority applications that
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`describe a sub-integrated circuit block with only one stage that also
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`comprises pluralities of forward connecting links and backward connecting
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`links as required by claim 1.
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`On the present record, we agree with Petitioner’s position that the
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`“said routing network comprising a plurality of stages y, in each said sub-
`
`integrated circuit block, starting from the lowest stage of 1 to the highest
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`stage of y, where y≧1” limitation of claim 1 lacks written description
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`support in the priority applications when y=1. Accordingly, we determine
`
`that Petitioner has established a reasonable likelihood that it would prevail in
`
`showing that the challenged claims in the ’523 patent are not entitled to the
`
`benefit of the May 25, 2007 filing date of the ’394 provisional, or the May
`
`22, 2008 filing date of the ’605 PCT.
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`D. Anticipation by the ’756 PCT
`
`Petitioner contends that the subject matter of claims 1, 16, 20–22, and
`
`32 of the ’523 patent is unpatentable under 35 U.S.C. § 102(b) as anticipated
`
`by the ’756 PCT. Pet. 26–76. Petitioner relies on the Baker Declaration in
`
`support of its contentions. Id.
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`The ’756 PCT was published on September 12, 2008. Ex. 1009,
`
`code (43). Petitioner’s challenge actually relies on the disclosure of the ’394
`
`provisional, which is incorporated by reference in its entirety into the ’756
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`PCT. Pet. 20–21; Ex. 1009, 2:14–17. Petitioner argues that the ’394
`
`provisional became publicly available as of the date the ’756 PCT was
`
`published. Pet. 21. We agree. 37 C.F.R. § 1.14(a)(1)(vi) provides, in
`
`relevant part, that if an unpublished application is incorporated by reference
`
`in an international publication of an international application (such as
`
`the ’756 PCT), a copy of “the unpublished pending application may be
`
`provided to any person, upon written request and payment of the appropriate
`
`fee.” Accordingly, once the ’756 PCT published, the ’394 provisional that is
`
`incorporated by reference therein became open to the public for inspection.
`
`The ’394 provisional therefore is prior art by virtue of the fact that it became
`
`publicly available due to its incorporation into the ’756 PCT, and in addition
`
`is prior art because it is part of the ’756 PCT itself. For purposes of this
`
`15
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`IPR2020-00260
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`Decision, we treat the disclosure of the ’394 provisional as prior art entitled
`
`to an effective date of September 12, 2008, when the ’756 PCT published.1
`
`Petitioner asserts, with supporting testimony from Dr. Baker, that
`
`the ’756 PCT, by way of its incorporation of the ’394 provisional, discloses
`
`all of the elements of independent claim 1. Pet. 26–64. For example,
`
`Petitioner contends that the ’394 provisional discloses “said routing network
`
`comprising a plurality of stages y, in each said sub-integrated circuit block,
`
`starting from the lowest stage of 1 to the highest stage of y, where y≧1”
`
`because “it discloses a network with a number of stages (y) equal to five,
`
`and 5 ≥1.” Pet. 35 (citing Ex. 1002 ¶ 92). Petitioner uses an annotated
`
`version of Figure 1B of the ’394 provisional, shown below, to depict its
`
`contentions.
`
`
`
`
`1 Patent Owner contends that, because 37 C.F.R. § 1.14(a)(1)(vi) also
`provides that “[t]he Office will not provide access to the paper file of a
`pending application, except as provided in paragraph (c) or (i) of this
`section,” the ’394 provisional was not available to the public when the ’756
`PCT published. Prelim. Resp. 40–44. This sentence, however, is directed to
`the entire file history of the unpublished application. It does not preclude
`access to the application alone.
`
`16
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`IPR2020-00260
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`Figure 1B is a diagram of a symmetrical folded multi-link routing network,
`
`with Petitioner’s annotations highlighting the five stages in the top-most
`
`sub-integrated circuit block. Id. (citing Ex. 1026, 2:12–14; Ex. 1002 ¶ 92).
`
`Petitioner further contends that the ’756 PCT, by way of its
`
`incorporation of the ’394 provisional, discloses “said each sub-integrated
`
`circuit block comprising a plurality of forward connecting links connecting
`
`from switches in a lower stage to switches in its immediate succeeding
`
`higher stage, and also comprising a plurality of backward connecting links
`
`connecting from switches in a higher stage to switches in its immediate
`
`preceding lower stage.” Pet. 41–45. Petitioner provides two annotated
`
`versions of Fig. 1K1 of the ’394 provisional, shown below, to illustrate its
`
`contentions.
`
`
`
`17
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`IPR2020-00260
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`
`
`Figure 1K1 shows the detailed connections of one block in a routing
`
`network described in the ’394 provisional (Ex. 1026, 3:19–21), with
`
`Petitioner’s annotations highlighting a plurality of forward connecting links
`
`in blue in the top figure, and a plurality of backward connecting links in
`
`green in the bottom figure. Pet. 42–44 (citing Ex. 1002 ¶¶ 104–108).
`
`Although Patent Owner generally states that “for each proposed
`
`ground, at least one claim element is missing from the references” (Prelim.
`
`Resp. 2), Patent Owner does not present arguments in the Preliminary
`
`Response addressing the specific merits of Petitioner’s contentions. See
`
`generally Prelim. Resp. Having reviewed all of Petitioner’s assertions
`
`regarding claim 1, as well as the supporting evidence, we determine on this
`
`record that Petitioner has established a reasonable likelihood of establishing
`
`that claim 1 is anticipated by the ’756 PCT by way of its incorporation of the
`
`’394 provisional. Pet. 26–64. We have also reviewed Petitioner’s
`
`arguments and evidence with respect to claims 16, 20–22, and 32 that
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`18
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`directly depend from claim 1. Id. at 64–76. Based on the record before us,
`
`we also find Petitioner’s arguments and evidence are sufficient to show a
`
`reasonable likelihood that Petitioner would prevail in proving the
`
`unpatentability of claim 16, 20–22, and 32.
`
`E. Obviousness over the ’756 PCT
`
`Petitioner contends that the subject matter of claims 15 and 17 of
`
`the ’523 patent would have been obvious over the teachings in the ’756
`
`PCT. Pet. 76–82. Petitioner relies on the Baker Declaration in support of its
`
`contentions. Id.
`
`Claim 15 depends from claim 1 and further recites “wherein said
`
`horizontal and vertical links are implemented in two or more metal layers.”
`
`Ex. 1001, 37:56–58. Petitioner contends that, although the ’756 PCT “does
`
`not explicitly disclose that the inlet links and outlet links, which include
`
`horizontal and vertical cross links, are routed using one or more metal
`
`layers, this feature would have been obvious.” Pet. 77 (citing Ex. 1002
`
`¶¶ 156–160). Petitioner contends, with supporting testimony from
`
`Dr. Baker, that “a POSITA would have known that metal layers are typically
`
`used to provide electrical connections on an integrated circuit.” Id. (citing
`
`Ex. 1002 ¶ 156). Petitioner also contends that the ’756 PCT “describes
`
`using ‘vias’ to connect inlet links and outlet links (Ex. 1009, 70:14–16), and
`
`a POSITA would have known that vias are commonly used to interconnect
`
`two different metal layers in an integrated circuit device.” Pet. 77 (citing
`
`Ex. 1002 ¶ 157). According to Petitioner, implementing the inlet links in a
`
`different metal layer than the outlet links “would have been a mere
`
`combination of known components and technologies, according to known
`
`19
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`methods, to produce predictable results.” Id. at 79 (citing Ex. 1002 ¶¶ 159–
`
`160).
`
`Claim 17 also depends directly from claim 1, and further recites
`
`“wherein said sub-integrated circuit blocks are of equal die size.” Ex. 1001,
`
`37:63–64. Relying on Dr. Baker’s testimony, Petitioner argues that although
`
`“the ’394 provisional does not explicitly disclose that the ‘sub-integrated
`
`circuit blocks are of equal size,’ it would have been obvious to configure the
`
`integrated circuit device of [the ’756 PCT] to use the same layout for each of
`
`the sub-integrated circuit blocks on the integrated device.” Pet. 81 (citing
`
`Ex. 1002 ¶ 162). Petitioner argues that using “equal (as opposed to unequal)
`
`die size would have been recognized as being a mere choice among a finite
`
`number of known alternatives, each having predictable outcomes.” Id. at 82
`
`(citing Ex. 1002 ¶ 162). Petitioner further argues that reusing the same
`
`layout in each of the blocks “would have been recognized as a more efficient
`
`from a design standpoint and would have ensured uniformity in placing the
`
`blocks in the two-dimensional grid and uniformity in block operation
`
`(delays, drive strength, etc.).” Id. (citing Ex. 1002 ¶ 162).
`
`At this stage of the proceeding, Patent Owner does not specifically
`
`address the merits of Petitioner’s arguments in the Preliminary Response.
`
`See generally Prelim. Resp. Having reviewed Petitioner’s assertions
`
`regarding claims 15 and 17, as well as the supporting evidence, we
`
`determine on this record that Petitioner has demonstrated a reasonable
`
`likelihood o
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