`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________
`
`FLEX LOGIX TECHNOLOGIES INC.,
`
`Petitioner
`
`V.
`
`VENKAT KONDA,
`
`Patent Owner
`
`____________
`
`Case PGR2020-00260
`
`Patent 8,269,523 B2
`
`_________
`
`
`
`
`DECLARATION OF VIPIN CHAUDHARY, PH.D., IN SUPPORT OF
`PATENT OWNER (cid:57)E(cid:49)KA(cid:55) K(cid:50)(cid:49)DA(cid:182)(cid:54) REQUEST FOR REHEARING
`UNDER 37 C.F.R. § 42.71(c)
`
`
`
`
`
`
`
`
`
`
`
`IPR2020-00260
`Patent 8,269,523
`
`
`Exhibit 2025
`
`Declaration of Vipin Chaudhary, Ph.D.
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ......................................................................................... 1
`
`BACKGROUND AND QUALIFICATIONS .............................................. 2
`
`III. MATERIALS CONSIDERED ..................................................................... 5
`
`IV. THE LEVEL OF SKILL IN (cid:55)HE A(cid:53)(cid:55) (cid:55)(cid:50) (cid:58)HICH (cid:55)HE (cid:181)523
`PATENT PERTAINS AND THE TECHNICAL BACKGROUND
`FROM THE VIEWPOINT OF A POSITA AT THE TIME OF THE
`INVENTION .................................................................................................. 7
`
`V.
`
`(cid:55)HE (cid:181)523 (cid:51)A(cid:55)E(cid:49)(cid:55) ....................................................................................... 9
`
`VI. (cid:51)A(cid:55)E(cid:49)(cid:55)ABILI(cid:55)(cid:60) (cid:50)F (cid:55)HE (cid:181)523 (cid:51)A(cid:55)E(cid:49)(cid:55): (cid:51)A(cid:53)(cid:55)IC(cid:56)LA(cid:53)L(cid:60) (cid:55)HE
`EA(cid:53)LIE(cid:54)(cid:55) EFFEC(cid:55)I(cid:57)E FILI(cid:49)G DA(cid:55)E (cid:50)F (cid:55)HE (cid:181)523 (cid:51)A(cid:55)E(cid:49)(cid:55) ...... 10
`
`VII. CONCLUSION ............................................................................................ 16
`
`
`
`
`
`
`
`
`
`Page ii of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`I, Vipin Chaudhary, Ph.D., hereby declare and state as follows:
`
`I.
`
`INTRODUCTION
`1. My name is Vipin Chaudhary. I am submitting this declaration on
`
`behalf of Patent Owner Venkat Konda ((cid:179)Patent Owner(cid:180)) in support of Patent
`
`Owner(cid:182)s Request for Rehearing Under 37 C.F.R. § 42.71(c) in the inter partes
`
`Review instituted in Case PGR2020-00260 filed by Petitioner Flex Logix
`
`Technologies Inc. ((cid:179)Petitioner(cid:180)) regarding claims 1, 15-18, 20-22, 32 and 47 (the
`
`(cid:179)Challenged Claims(cid:180)) of U.S. Patent No. 8,269,523 (Ex. 1001, (cid:179)the (cid:181)523 Patent(cid:180))
`
`2.
`
`I have reviewed the (cid:181)523 patent and its claims. I am a technical expert
`
`in the subject matter areas relevant to the (cid:181)523 patent, including the field of
`
`integrated circuits and interconnection networks. I have been asked to consider the
`
`validity of the claims of the (cid:181)523 patent. I have read and understood the content of
`
`each of the publications referenced in the Petition filed by Petitioner on December
`
`16, 2019 ((cid:179)Petition(cid:180)). I have read and understood the (cid:181)523 Patent and claims 1-48 of
`
`the (cid:181)523 patent. This declaration provides my expert opinion regarding the subject
`
`matter addressed below.
`
`3.
`
`This declaration is based on the information currently available to me.
`
`To the extent that additional information becomes available, I reserve the right to
`
`continue my investigation and study, which may include review of documents and
`
`
`
`Page 1 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`information that may be produced, as well as testimony from depositions that have
`
`not yet been taken.
`
`II. BACKGROUND AND QUALIFICATIONS
`4.
`A copy of my curriculum vitae ((cid:179)CV(cid:180)), which fully describes my
`
`qualifications as an expert in this matter, is found at Exhibit 2026. In addition, I
`
`have set forth some of my qualifications in the paragraphs below that may be
`
`particularly relevant here. I am over 18 years of age and, if I am called upon to
`
`do so, I would be competent to testify as to the matters set forth herein.
`
`5.
`
`I hold a Bachelor Degree (Hons.) in Computer Science and
`
`Engineering from the Indian Institute of Technology, Kharagpur, India awarded in
`
`1986, and the MS degree in Computer Science in 1989 and the Ph.D. degree in
`
`Electrical and Computer Engineering in 1992, both from The University of Texas
`
`at Austin.
`
`6.
`
`Currently I am the Endowed Kranzusch Professor and Inaugural
`
`Chair, Department of Computer and Data Sciences, Case School of Engineering,
`
`Case Western Reserve University, Cleveland, Ohio. Prior to this position, I was a
`
`SUNY Empire Innovation Professor between 2011 and 2020 and SUNY
`
`Empire Innovation Associate Professor between 2006 and 2011, Computer
`
`Science and Engineering at University at Buffalo, The State University of New
`
`
`
`Page 2 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`York. Between June 2016 and June 2020, I was also a Program Director at the
`
`Office of Advanced Cyber Infrastructure, Directorate for Computer and
`
`Information Science and Engineering, National Science Foundation, Alexandria,
`
`Virginia. Prior to the University at Buffalo, I was an Associate Professor,
`
`Department of Computer Science, and an Associate Professor, Department of
`
`Electrical and Computer Engineering at Wayne State University, Detroit, Michigan
`
`between 1998 and 2006, and an Assistant Professor, Department of Electrical and
`
`Computer Engineering, Wayne State University between 1992 and 1998.
`
`7.
`
`I have been active in the field of integrated circuits and
`
`interconnection networks for over 30 years, since my Ph.D. Dissertation, awarded
`
`in 1992, in the area of parallel and distributed computing where interconnection
`
`networks is a major part of my dissertation.
`
`8.
`
`I have received numerous awards for my work, including the 2019
`
`National Science Foundation Director(cid:182)s Superior Accomplishment Award for my
`
`contributions where as a Program Director I co-led the National Strategic
`
`Computing Initiative from NSF for the United States and in the working groups of
`
`the Quantum Leap Initiative, National Quantum Initiative, National Artificial
`
`Intelligence Research Institutes, Cyber, and the I-Corps Program. The I-Corps
`
`program is now part of (cid:179)The American Innovation and Competitiveness Act(cid:180) that
`
`enables commercialization of research and venture startups. The U.S. National
`Page 3 of 18
`
`
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`Strategic Computing Initiative incorporates many aspects of interconnection
`
`networks to make large computer systems.
`
`9.
`
`I was co-founder of several startups, including as a Senior Director of
`
`Advanced Development at Cradle Technologies, Inc., where I was responsible for
`
`advanced programming tools development for multi-processor chips where
`
`interconnection networks is a key component. In Scalable Informatics, we
`
`designed and built some of the highest performance storage and analytics systems.
`
`As the CEO of Computational Research Laboratories, we built the fourth largest
`
`supercomputer system in the world with a unique interconnection network that
`
`enabled fast performance at a fraction of the cost. This company was sold to Tata
`
`Consulting Services. Prior to this, I was the Chief Architect at Corio, that is known
`
`as one of companies that really started the Software-as-a-Service revolution and
`
`had a successful IPO in 2000.
`
`10.
`
`In Section V, I have disclosed most of my further qualifications
`
`particularly relevant to integrated circuits and interconnection networks needed by
`
`one of ordinary skill in the art to understand the disclosure of the (cid:181)523 patent at the
`
`time of the invention which is about May 25, 2007, the filing date of U.S.
`
`Provisional Patent Application No. 60/940,394 ((cid:179)the (cid:181)394 Provisional(cid:180)).
`
`
`
`Page 4 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`11. All of my opinions stated in this declaration are based on my own
`
`personal knowledge and professional judgment and do not reflect the
`
`opinions of my employers. In forming my opinions, I have relied on my
`
`knowledge and experience in designing, developing, researching, and
`
`teaching related to integrated circuits and interconnection networks
`
`referenced in this declaration.
`
`12.
`
`I am not an attorney and offer no legal opinions.
`
`III. MATERIALS CONSIDERED
`13.
`I have considered the following materials in preparing the opinions set
`
`forth in this declaration: the (cid:181)523 patent, including the specification and claims
`
`(Ex. 1001); the prosecution history of the (cid:181)523 patent in the United States Patent
`
`& Trademark Office ((cid:179)the PTO(cid:180)) (Ex. 1004); Patent Owner(cid:182)s Preliminary
`
`Response (Paper No. 8); Decision Granting Institution of Post-Grant Review
`
`(Paper No. 22); Declaration of Jacob Baker, Ph.D., P.E. (Ex. 1002); Curriculum
`
`Vitae of Jacob Baker, Ph.D., P.E. (Ex. 1003); File History of U.S. Patent No.
`
`8,269,523 (Ex. 1004); PCT Publication No. WO2008/147928 (Ex. 1005); U.S.
`
`Patent No. 10,003,553 (Ex. 1006); Body of PCT Application No.
`
`PCT/US08/64605 as filed ((cid:179)the (cid:182)605 PCT(cid:180)) (Ex. 1007); U.S. Patent No.
`
`6,940,308 ((cid:179)Wong(cid:180)) (Ex. 1008); PCT Publication No. WO 2008/109756 A1
`Page 5 of 18
`
`
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`((cid:179)Konda ‘756 PCT(cid:180)) (Ex. 1009); As-filed Disclosure of U.S. Provisional
`
`Application 60/984,724 (Excerpt from File History of U.S. Provisional
`
`Application No. 60/984,724 (Ex. 1039)) (Ex. 1010); U.S. Patent No.
`
`8,270,400 (Ex. 1011); PCT Application No. PCT/US08/56064 (Ex. 1012);
`
`File History of U.S. Provisional Application No. 60/905,526 (Ex. 1013); File
`
`History of U.S. Provisional Application No. 60/940,383 (Ex. 1014); U.S.
`
`Patent No. 8,170,040 (Ex. 1015); PCT Application No. PCT/US08/64603
`
`(Ex. 1016); File History of U.S. Provisional Application No. 60/940,387 (Ex.
`
`1017); File History of U.S. Provisional Application No. 60/940,390 (Ex.
`
`1018); U.S. Patent No. 8,363,649 (Ex. 1019); PCT Application No.
`
`PCT/US08/64604 (Ex. 1020); File History of U.S. Provisional Application
`
`No. 60/940,389 (Ex. 1021); File History of U.S. Provisional Application No.
`
`60/940,391 (Ex. 1022); File History of U.S. Provisional Application No.
`
`60/940,392 (Ex. 1023); File History of U.S. Provisional Application No.
`
`60/940,394 (Ex. 1026); File History of U.S. Provisional Application No.
`
`61/252,603 (Ex. 1029); File History of U.S. Provisional Application No.
`
`61/252,609 (Ex. 1030); File History of U.S. Provisional Application No.
`
`60/984,724 (Ex. 1039); and all documents cited in this declaration.
`
`
`
`Page 6 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`14.
`I also relied on my own training, knowledge, and experience in the
`
`field to which the (cid:181)523 patent is directed, along with my understanding of how one
`
`of ordinary skill in the art would have understood the disclosure of the (cid:181)523 patent
`
`at the time of the invention which is about May 25, 2007, the filing date of
`
`the (cid:181)394 Provisional. My opinions reflect how one of ordinary skill in the art
`
`would have understood the (cid:181)523 patent, the alleged prior art to the patent, and
`
`the state of the art at the time of the invention.
`
`IV. THE LEVEL OF SKILL IN THE ART TO WHICH THE (cid:181)523
`PATENT PERTAINS AND THE TECHNICAL BACKGROUND
`FROM THE VIEWPOINT OF A POSITA AT THE TIME OF THE
`INVENTION
`15.
`
`It is my understanding that I must address the issues set forth in this
`
`declaration from the viewpoint of a POSITA to which the (cid:181)523 patent pertains at
`
`the time of the invention.
`
`16.
`
`In my opinion, one of ordinary skill in the art to which the (cid:181)523 patent
`
`pertains would have had a master(cid:182)s degree in electrical/computer engineering or a
`
`similar field, and at least two to three years of experience with integrated circuits,
`
`interconnection networks and Field Programmable Gate Arrays. In the pertinent
`
`field of the invention, more education can supplement practical experience and
`
`vice versa.
`
`
`
`Page 7 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`17.
`I will now list some of my qualifications from the viewpoint of a
`
`POSITA to which the (cid:181)523 patent pertains at the time of the invention.
`
`18.
`
`I served as associate Guest Editor, Special Issue of IEICE
`
`Transactions on Information and Systems on Hardware/Software Support for High
`
`Performance Scientific and Engineering Computing, July 2004. I served as
`
`Conference or Symposium Chair in six of the relevant conferences and as
`
`workshop chair in more than twenty workshops in the area of interconnection
`
`networks. I served as program committee member in more than forty conferences.
`
`19.
`
`I taught two undergraduate courses and more than ten graduate
`
`courses where integrated circuits and interconnection networks is an integral part
`
`of the subject matter. I also have created more than five courses where integrated
`
`circuits and interconnection networks is an integral part.
`
`20.
`
`I have supervised more than five doctoral dissertations and more than
`
`five Master(cid:182)s theses.
`
`21.
`
`I have contributed to more than eight book chapters and published
`
`more than fifteen papers in refereed journal papers, more than fifty papers in
`
`refereed conference papers and more than ten refereed workshops related to
`
`integrated circuits and interconnection networks.
`
`
`
`Page 8 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`22.
`I have given more than thirty invited talks at Academic Institutions,
`
`Industries, Research Laboratories, conferences and workshops related to integrated
`
`circuits and interconnection networks.
`
`V. THE (cid:181)523 (cid:51)ATENT
`23.
`I have read and analyzed the (cid:181)523 patent and its prosecution history. I
`
`understand that the (cid:181)523 patent titled (cid:179)VLSI Layouts of Fully Connected
`
`Generalized Networks(cid:180) pertains to Very Large Scale Integration ((cid:179)VLSI(cid:180)) layouts
`
`in an integrated circuit based on a two-dimensional grid comprising only horizontal
`
`and vertical tracks (Ex. 1001). The (cid:181)523 patent describes VLSI layouts of
`
`generalized multi-stage networks for broadcast, unicast, and multicast connections
`
`using only horizontal and vertical links. Id. at 3:21(cid:177)24. The VLSI layouts employ
`
`shuffle exchange links, where outlet links of cross links from switches in a stage in
`
`one sub-integrated circuit block are connected to inlet links of switches in the
`
`succeeding stage in another sub-integrated circuit block. Id. at 3:24(cid:177)28. The cross
`
`links are either vertical links or horizontal links, and vice versa. Id. at 3:28(cid:177)29.
`
`24.
`
` In one embodiment, the sub-integrated circuit blocks are arranged in
`
`a hypercube arrangement in a two-dimensional plane. Id. at 3:29(cid:177)31. The VLSI
`
`layouts exploit the benefits of significantly lower cross points, lower signal
`
`
`
`Page 9 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`latency, lower power, and full connectivity with significantly fast compilation. Id.
`
`at 3:31(cid:177)34.
`
`25.
`
`26.
`
` The (cid:181)523 patent includes a single independent claim, i.e., claim 1.
`
` I am informed and understand that a dependent claim is narrower
`
`than the claims from which it depends because it includes additional limitations.
`
`Thus, claims 2 - 48, which depend, either directly, or ultimately, from independent
`
`claim 1, are narrower in scope than claim 1.
`
`VI. PATENTABILITY OF THE (cid:181)523 PATENT: PARTICULARLY THE
`EARLIEST EFFECTIVE FILING DATE OF (cid:55)HE (cid:181)523 (cid:51)A(cid:55)E(cid:49)(cid:55)
`27. The (cid:181)523 Patent (Ex. 1001) issued from patent application No.
`
`12/601,275 ((cid:179)the (cid:181)275 application(cid:180), Ex. 1004) filed on November 22, 2009. (As
`
`noted above, the (cid:181)523 Patent has only one independent claim, i.e., claim 1.) The
`
`(cid:181)523 Patent is a national stage application of international application PCT
`
`Application No. PCT/US2008/064605 ((cid:179)the (cid:181)605 PCT application(cid:180)), (Ex. 1007),
`
`filed May 22, 2008 which in turn is a continuation-in-part and claims priority to the
`
`(cid:181)394 Provisional, filed May 25, 2007. No new subject matter was added to the
`
`specification of the (cid:181)275 application which issued as the (cid:181)523 Patent. Thus, the
`
`effective filing date of the (cid:181)523 Patent is the earliest application for which priority
`
`was claimed, namely, May 25, 2007.
`
`
`
`Page 10 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`28. Petitioner argued that the (cid:181)605 PCT and the (cid:182)394 Provisional
`
`(collectively, (cid:179)the priority applications(cid:180)) do not provide support for an integrated
`
`circuit device that includes a routing network comprising a plurality of stages y
`
`that also includes the other limitations of claim 1 such as pluralities of forward
`
`connecting links and pluralities of backward connecting links, when there is only
`
`one stage (y=1). (Petition at 6(cid:177)20.)
`
`29. Relying on Dr. Baker(cid:182)s declaration (Ex. 1002), I understand that the
`
`Board agreed with Petitioner(cid:182)s position that the (cid:179)said routing network comprising a
`
`plurality of stages y, in each said sub-integrated circuit block, starting from the
`
`lowest stage of 1 to the highest stage of y, where y≧1(cid:180) limitation of claim 1 lacks
`
`written description support in the priority applications when y=1.
`
`30.
`
`I have been asked by Patent Owner, to consider whether a
`
`POSITA would have understood that the named inventor of the (cid:181)523 patent
`
`was in possession of the subject matter recited in claim 1 of the (cid:181)523 patent
`
`with written description support in the disclosures of the (cid:181)605 PCT and the
`
`(cid:182)394 Provisional. In my opinion, a POSITA reviewing the (cid:181)605 PCT and the
`
`(cid:181)394 Provisional would in fact understand that the named inventor was in
`
`possession of the subject matter recited in claim 1 particularly with respect to
`
`(cid:179)said routing network comprising a plurality of stages y, in each said sub-
`
`
`
`Page 11 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`integrated circuit block, starting from the lowest stage of 1 to the highest stage of
`
`y, where y≧1(cid:180) as described below, in view of the following figures on the (cid:181)523
`
`Patent.
`
`
`
`31. The (cid:181)523 patent discloses VLSI layouts of fully connected generalized
`
`multi-stage networks, including a butterfly fat tree network, for broadcast, unicast,
`
`and multicast connections using only horizontal and vertical links. In my opinion,
`
`a POSITA would have understood a fully connected butterfly fat tree network, as
`
`also disclosed in the (cid:181)523 patent, (cid:11)
`log
`
`
`
`(cid:12)N2
` stages in a row (or block), where N is the
`Page 12 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`number of inputs or outputs. Accordingly, for example, there will be one stage
`
`when there is one block as illustrated in FIG. 2A1-3 of the priority applications Ex.
`
`1007, 7:10-21; Ex. 1026, 4:4-15. In my opinion, a POSITA would have
`
`understood that when there is one block there are no forward connecting links and
`
`no backward connecting links as illustrated in FIG. 2A3 of the (cid:181)523 patent, which
`
`is the smallest butterfly fat tree network.
`
`32. Claim 1 of the (cid:181)523 patent first recites stages and switches as follows:
`
`Said routing network comprising of a plurality of stages y, in each said sub-
`integrated circuit block, starting from the lowest stage of 1 to the highest
`
`Said routing network comprising a plurality of switches of size d×d, where
`
`stage of y, where y≧1; and
`d≧2, in each said stage and each said switch of size d×d having d inlet links
`
`and d outlet links;
`
`33.
`
` Claim 1 subsequently recites forward connecting links and backward
`
`connecting links as follows:
`
`(cid:179)Said each sub-integrated circuit block comprising a plurality of
`forward connecting links connecting from switches in lower stage to
`switches in the immediate succeeding higher stage, and also comprising a
`plurality of backward connecting links connecting from switches in higher
`stage to switches in the immediate preceding lower stage;(cid:180)
`
`In my opinion, a POSITA would understand that a plurality of
`
`34.
`
`forward connecting links are connected from a stage when there is an immediate
`
`succeeding stage and a plurality of backward connecting links are connected from
`
`a stage when there is an immediate preceding stage. That is, a POSITA would
`
`
`
`Page 13 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`understand that a plurality of forward connecting links are not connected from a
`
`stage when there is no immediate succeeding stage and a plurality of backward
`
`connecting links are not connected from a stage when there is no immediate
`
`preceding stage.
`
`35. Accordingly, for example, referring to FIG. 1B below, as disclosed in
`
`the priority applications Ex. 1007, 5:17-21; Ex. 1026, 2:12-16, the stage denoted
`
`by 160 ((cid:179)Stage 5(cid:180)) has a preceding stage denoted by 150 & 170 ((cid:179)Stage 4(cid:180)), and so
`
`backward connecting links denoted by ML(5,1) - ML(5,64), etc. are connected
`
`from Stage 5 and Stage 4. However, Stage 5 has no succeeding stage and so no
`
`forward connecting links are connected from Stage 5 as illustrated by FIG. 1B.
`
`Similarly the stage denoted by 110 & 120 ((cid:179)Stage 1(cid:180)) has a succeeding stage
`
`denoted by 130 & 190 ((cid:179)Stage 2(cid:180)), and so forward connecting links denoted by
`
`ML(1,1) - ML(1,64), etc. are connected from Stage 1 and Stage 2. However, Stage
`
`1 has no preceding stage, and so no backward connecting links are connected from
`
`Stage 1 as illustrated in FIG. 1B.
`
`36. Similarly, in my opinion, a POSITA would understand that,
`
`referring to FIG. 2A3, above, there is one stage ((cid:179)Stage 1(cid:180)) in Block 1_2. Since
`
`Stage 1 has no succeeding stage, no forward connecting links are connected from
`
`Stage 1. Also, since Stage 1 has no preceding stage, no backward connecting links
`
`are connected from Stage 1.
`
`
`
`Page 14 of 18
`
`
`
`
`IPR2020-00260
`Patent 8,269,523
`
`
`
`
`Exhibit 2025
`Declaration of Vipin Chaudhary, Ph.D.
`
`
`
`37. Essentially, in my opinion, a POSITA would understand that the
`
`first stage of a butterfly fat tree network has no preceding stage, and so no
`
`backward connecting links are connected from the first stage. Also the last stage of
`
`a butterfly fat tree network has no succeeding stage, and so no forward connecting
`
`links are connected from the last stage. In my opinion, a POSITA would
`
`understand that when there is one stage in a butterfly fat tree network as illustrated
`
`in FIG. 2A1-3 of the priority applications, it is the first stage as well as the last
`
`stage. Furthermore, the one stage has neither a preceding stage nor a succeeding
`
`stage, and so no forward connecting links are connected from the stage and no
`
`backward connecting links are connected from the stage. In my opinion, for a
`
`
`
`Page 15 of 18
`
`
`
`
`IPR2020-00260
`
`Exhibit 2025
`Patent 8,269,523
`
`Declaration of Vipin Chaudhary, Ph.D.
`POSITA this is straight forward to understand. Accordingly, no experimentation is
`
`needed to understand it, let alone undue experimentation.
`
`38. Accordingly, in my opinion, a POSITA reviewing the (cid:182)605 PCT
`
`and the (cid:182)394 Provisional would have in fact understood that the named
`
`inventor was in possession of the subject matter recited in claim 1 of the (cid:181)523
`
`patent, particularly with respect to (cid:179)said routing network comprising a plurality of
`
`stages y, in each said sub-integrated circuit block, starting from the lowest stage of
`
`1 to the highest stage of y, where y≧1(cid:180) and that the (cid:181)523 patent is entitled to the
`
`benefit of the May 25, 2007 filing date of the (cid:181)394 Provisional.
`
`VII. CONCLUSION
`39. For the reasons stated above, it is my opinion that the (cid:181)523 patent is
`
`entitled to the benefit of the May 25, 2007 filing date of the (cid:181)394 Provisional.
`
`40.
`
`I hereby declare that all statements made herein of my own
`
`knowledge are true and that all statements made on information and belief are
`
`believed to be true; that these statements were made with knowledge that willful
`
`false statements and the like so made are punishable by fine or imprisonment, or
`
`both, under Section 1001 of Title 18 of the United States Code.
`
`Dated: August 10, 2020
`
`
`
`
`
`
`
`
`
`Respectfully submitted,
`
`
`Vipin Chaudhary, Ph.D
`
`Page 16 of 18
`
`
`
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
