Electronic Thesis and Dissertations
`UCLA
`
`Peer Reviewed
`
`Title:
`Building Efficient, Reconfigurable Hardware using Hierarchical Interconnects
`Author:
`Wang, Chengcheng
`Acceptance Date:
`2013
`Series:
`UCLA Electronic Theses and Dissertations
`Degree:
`Ph.D., Electrical Engineering 0303UCLA
`Advisor(s):
`Markovic, Dejan
`Committee:
`Srivastava, Mani B., Kaiser, William J., Gerla, Mario
`Permalink:
`http://escholarship.org/uc/item/2vt0b5cb
`Abstract:
`
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`UNIVERSITY OF CALIFORNIA
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`Los Angeles
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`Building Efficient, Reconfigurable Hardware using
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`Hierarchical Interconnects
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`A thesis submitted in partial satisfaction
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`of the requirements for the degree
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`Doctor of Philosophy in Electrical Engineering
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`by
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`Chengcheng Wang
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`2013
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`© Copyright by
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`Chengcheng Wang
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`2013
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`ABSTRACT OF THE DISSERTATION
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`Building Efficient, Reconfigurable Hardware using Hierarchical
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`Interconnects
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`by
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`Chengcheng Wang
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`Doctor of Philosophy in Electrical Engineering
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`University of California, Los Angeles, 2013
`
`Professor Dejan Marković, Chair
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`
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`In the semiconductor industry today, ASICs are able to offer 10x-1000x higher energy
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`and area efficiencies than non-dedicated chips, such as programmable DSP processers, field-
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`programmable gate arrays (FPGAs), and microprocessors. Not surprisingly, SoCs today have
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`become an integration of many ASIC blocks, each performing a few dedicated tasks. The
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`growing size of modern SoC chips, accelerated by the increasing demands for functionalities, has
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`exposed the major drawback of ASIC: design cost. These large SoCs are re-designed a few times
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`a year to rectify hardware-bugs and to support new features. Because ASICs are not
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`reconfigurable, even the smallest hardware change would require a re-design. Additionally,
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`design cost is rising exponentially with every technology generation.
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`The rising design cost of ASICs has exposed a huge need today: efficiency and flexibility
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`must co-exist. But among flexible hardware candidates, microprocessors and programmable DSP
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`processors are far too slow to meet the throughput requirements of ASICs. FPGAs do come close
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`in terms of performance, but are extremely inefficient due to its high energy and large area
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`overhead. We must bridge the huge gap in efficiency for FPGA to become a viable contender to
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`ASICs.
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`The primary culprit for FPGA inefficiency is interconnect, which accounts for over 75%
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`of area and delay. For over 20 years, 2D-mesh network has been the back-bone of FPGA
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`interconnects, but full connectivity in a 2D-mesh require O(N2) switches, requiring interconnects
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`to grow much faster than Moore‟s Law. As a result, various heuristics are used to simplify
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`switch-box arrays at the cost of resource utilization, but interconnect area of modern FPGA is
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`still around 80%. This work builds FPGA using hierarchical interconnects based on Beneš
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`networks,
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`requiring O(N∙log∙N)
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`switches. Although Beneš
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`is commonly used
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`in
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`telecommunication, this work is its first silicon realization of a FPGA. To realize a highly
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`efficient interconnect architecture, significant pruning of the network is required. Novel
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`techniques such as fast-path U-turns and unbalanced branching are also implemented. A custom
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`place-and-route software is developed to map benchmark designs on a variety of interconnect
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`candidates. From mapping results, the architecture is updated based on network utilization until
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`an optimized design is converged. The large area of FPGA chip requires aggressive power gating
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`(PG), but interconnect signals often lack spatial locality, make it block-level PG difficult. A
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`novel PG circuit technique is developed to power-gate individual interconnect switches with very
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`small overhead in area and performance. Such technique requires fundamental circuit changes,
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`even modifying the CMOS inverter.
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`With
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`innovations
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`in chip architecture, circuit design, and extensive software
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`development, this work has demonstrated 5 user-mappable FPGAs (from 1K–16K LUTs) all
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`with around 50% interconnect area: a 3–4x reduction from commercial FPGAs while preserving
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`connectivity. An energy efficiency of 1.1 GOPS/mW is the highest among reported FPGAs, and
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`is 22x more efficient than the most efficient commercial FPGA today, significantly bridging the
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`efficiency gap between FPGA and ASIC.
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`The dissertation of Chengcheng Wang is approved.
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`
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`Mani B. Srivastava
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`William J. Kaiser
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`Mario Gerla
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`Dejan Marković, Committee Chair
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`University of California, Los Angeles
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`2013
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`TABLE OF CONTENTS
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`I
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`Introduction ............................................................................................................1
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`1.1
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`The Drive Towards Efficiency.....................................................................1
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`1.2 What is Efficiency? ......................................................................................2
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`1.3
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`The Efficiency Tradeoff ...............................................................................3
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`1.4
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`Efficiency and Flexibility – Current Solutions ............................................5
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`1.5
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`Keeping Up with the Standards ...................................................................7
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`1.6
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`The Cost of Chip Design..............................................................................8
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`1.7
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`Candidates for Reconfigurable Hardware ....................................................9
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`1.8
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`Thesis Outline ............................................................................................11
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`II
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`FPGA Interconnects: the Source of its Inefficiency ..........................................12
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`2.1
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`Brief History of FPGAs .............................................................................12
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`2.2
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`Interconnects: the Backbone of an FPGA ..................................................18
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`2.3
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`Scaling a 2D-mesh Network ......................................................................21
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`2.4
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`Hierarchical Network – A Scalable Solution .............................................23
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`2.5
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`Prior Attempts at Hierarchical FPGAs ......................................................28
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`2.6
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`Our Challenges...........................................................................................31
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`III
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`Architecture Design of Hierarchical FPGAs .....................................................33
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`3.1
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`Realizing Large-Scale Beneš Networks.....................................................33
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`3.2
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`Implementing a 2048-LUT FPGA Interconnect ........................................36
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`3.3
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`Radix-3 Boundary-less Interconnect ..........................................................38
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`3.4
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`Fast-Path Interconnect ...............................................................................44
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`3.5
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`Interconnect Cost vs. Gate Cost .................................................................47
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`3.6
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`Local Interconnect vs. Branch Interconnect ..............................................48
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`3.7 Micro-architecture of a Switch Matrix ......................................................50
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`3.8
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`Implementing a 16K-LUT FPGA Interconnect .........................................52
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`IV
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`Interconnect Circuit Design ................................................................................58
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`4.1
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`Key Building Blocks in Interconnect Circuits ...........................................58
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`4.2
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`Static Multiplexers and Area-Performance Tradeoff .................................59
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`4.3
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`Strategies for Interconnect Buffering.........................................................63
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`4.4
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`Designing Configuration Bit-Cells ............................................................66
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`4.5
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`Power-gating Switch Matrices ...................................................................68
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`4.6
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`Power-On Sequence of the Interconnect Network .....................................73
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`V
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`Configurable Logic Block Design and Chip Integration ..................................79
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`5.1
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`Configurable Logic Blocks for the 2048-LUT FPGA ...............................79
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`5.2 Macro-based Chip Integration for the 2048-LUT FPGA ..........................86
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`5.3
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`Fine-Grained CLBs for the 16K-LUT FPGA ............................................91
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`5.4 Medium-Grained CLBs for the 16K-LUT FPGA ......................................98
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`5.5
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`Coarse-Grained CLBs for the 16K-LUT FPGA ......................................102
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`5.6 Macro-based Chip Integration for the 16K-LUT FPGA ..........................105
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`VI
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`Software Flow and Design Mapping ................................................................113
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`6.1
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`Overview of FPGA Software Mapping Flow ..........................................113
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`6.2
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`FPGA Synthesis and LUT Packing..........................................................116
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`6.3
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`FPGA Partitioning and Placement ...........................................................120
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`6.4
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`FPGA Routing .........................................................................................124
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`6.5
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`Bitstream Generation ...............................................................................129
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`VII Test Infrastructure and Measurement Results ...............................................130
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`6.1 Matlab Simulink-based Testing Infrastructure ........................................130
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`6.2 Measurement Results of our 2048-LUT FPGA .......................................134
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`6.3
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`Updated Testing Infrastructure ................................................................138
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`6.4 Measurement Results of our 16K-LUT FPGA ........................................140
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`6.5
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`Chips Summary and Die Photos ..............................................................142
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`VIII Conclusion and Future Outlook .......................................................................147
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`References .......................................................................................................................150
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`LIST OF FIGURES
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`1-1
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`Energy and area efficiency of the ISSCC/VLSI chips from the past decade. ..........4
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`1-2
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`Block diagram of an NVIDIA Tegra 2 SoC for smartphones. ................................5
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`1-3
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`Evolution of common multimedia and radio standards. ..........................................7
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`1-4
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`Cost of chip design with every technology node. ....................................................8
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`2-1
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`Schematic diagram from a Xilinx XC2000 of CLB and interconnects. ................12
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`2-2
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`Illustration of Stacked-Silicon Technology in Xilinx Virtex-7. ............................14
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`2-3
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`CLB diagram of Xilinx XC3000, XC4000, and XC5200. .....................................16
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`2-4
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`CLB diagram of Xilinx a Virtex-6 and 7 series FPGA. .........................................17
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`2-5 A sample 2D-mesh architecture with I/O connections and switch boxes. .............19
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`2-6
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`Interconnect architecture of a Xilinx XC4000 FPGA............................................20
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`2-7 Area, delay and power breakdown of a modern 2D-mesh FPGA .........................21
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`2-8
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`Interconnect resources per CLB for Xilinx Virtex-4 vs. Virtex-5 .........................22
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`2-9 A simple 3-stage Beneš network connecting 2 LUTs ............................................24
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`2-10 A 5-stage Beneš network merged into a 3-stage using 2-bit 2x2 switches ............25
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`2-11 A 5-stage Beneš network connecting 8 LUTs .......................................................26
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`2-12 A 3-stage folded Beneš network connecting 8 LUTs ............................................27
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`2-13 A hierarchical Beneš interconnect architecture using alternated x-y routing ........28
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`2-14 A 5-stage Beneš network merged into a 3-stage using 2-bit 2x2 switches ............29
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`2-15 The HSRA architecture without and with wiring shortcuts ...................................30
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`2-16 The multilevel hierarchical FPGA architecture .....................................................31
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`3-1 A hierarchical macro-based implementation of a 2D-Beneš network ...................35
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`3-2
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`Interconnect architecture for our 2048-LUT FPGA, one quadrant shown ............36
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`3-3
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`Interconnect architecture for our 2048-LUT FPGA, one quadrant shown ............37
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`3-4 An original 16-LUT Beneš network, with isomorphic transformation to shorten
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`nearest-neighbor lengths, and with boundary-less radix-3 switches in stage 1 .....39
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`3-5 A 16-LUT Beneš network with boundary-less radix-3 switches in stage 1, and
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`with boundary-less radix-3 switches in stages 1 and 2 ..........................................40
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`3-6 A 16-LUT Beneš network, with boundary-less radix-3 switches in stages 1 and
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`2, with boundary-less radix-3 switches in stage 1-3, and rearranged for
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`distributed routing ..................................................................................................43
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`3-8 An original radix-4 16-LUT Beneš network and with boundary-less radix-6
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`switches in stage 1 .................................................................................................44
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`3-9 A routing example from LUT 2 to 16 without fast path and with fast path ..........45
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`3-10 A routing example with routing obstruction that still allows a slower fast-path
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`and allowing no fast-path .......................................................................................46
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`3-11 Two SM design with same gate cost, but a) with more wiring than b) .................47
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`3-12 An example where traditional-Beneš based SM experiences local interconnect
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`congestion, whereas a SM design with more local interconnects can utilize the
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`fast path ..................................................................................................................49
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`3-13 A switch-matrix example with more
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`local
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`interconnects
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`than branch
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`interconnects ..........................................................................................................50
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`3-14
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`Internal mux interconnect of an example radix-3 switch matrix ...........................51
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`3-15 1-D SM architecture of the 16K-LUT FPGA, showing the lower 10 SM stages ..55
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`3-16 2-D SM architecture of the 16K-LUT FPGA, showing the top 5 stages of
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`wiring .....................................................................................................................56
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`4-1 An example switch matrix with its internal circuitry .............................................58
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`4-2 A static pass-transistor mux with high VDD for the bit-cells ................................60
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`4-3 A 10-input static pass-transistor mux with 2 critical-path inputs and 8 non-
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`critical-path inputs, requiring 8 bit-cells ................................................................62
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`4-4
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`Illustration of input-buffer sharing inside a switch matrix ....................................64
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`4-5
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`Illustration of signal buffer across interconnects of a non-inverting mux, an
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`inverting mux with input inverters, and an inverting mux with output inverters ..65
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`4-6
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`Physical design of the configuration bit-cells in 5T SRAM and 6T SRAM .........68
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`4-7 A 4-input static mux with output inverter and traditional power gating ................69
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`4-8 A 4-input static mux with output inverter and our proposed power gating ...........71
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`4-9 A 4-input static mux with output inverter and our proposed, tri-state PG .............72
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`4-10 An example of an unconfigured mux where s0 and s3 are both conducting .........73
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`4-11 An example of an unconfigured mux where VDDL is „0‟, no current flows ........74
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`4-12 An example of an unconfigured mux from Figure 4.8, where VDDL is „0‟ but
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`PG is „1‟, causing current flow ..............................................................................75
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`4-13 An example of an unconfigured mux from Figure 4.9, where VDDL is „0‟ but
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`PG is „1‟, causing current flow ..............................................................................75
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`4-14 Example illustration with an updated design that uses VDDL signals, applied on
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`a) the design from Figure 4.8 and b) the design from Figure 4.9 ..........................76
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`4-15 Example illustration with an updated design that uses VDDH,LATE signals,
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`applied on the design from Figure 4.8 and the design from Figure 4.9 .................77
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`5-1
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`Resource allocation for interconnects and CLBs ...................................................80
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`5-2
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`Block diagram of a Logic CLB and a DSP CLB ...................................................81
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`5-3
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`Block diagram of a Logic CLB and a DSP CLB ...................................................82
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`5-4
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`The 6 BRAM modes: dual 8-bit read, 16-bit read, 8-bit masked write, 16-bit
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`read, 16-bit masked write, 8-bit write, dual 8-bit read, and 16-bit write, 16-bit
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`read .........................................................................................................................84
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`5-5 Write-logic architecture of the 1Kb reconfigurable dual-port BRAM ..................85
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`5-6
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`Read-logic architecture of the 1Kb reconfigurable dual-port BRAM ...................86
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`5-7 Design of a bit-cell (BC) array with its bit-line (BL) and word-line (WL)
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`controls ...................................................................................................................87
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`5-8
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`Layout of a CLB-SM macro with 4 SMs, a BC array, and BL and WL controls ..88
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`5-9
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`Top-level layout floorplan of the 2048-LUT FPGA with 512 CLBs ....................90
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`5-10 Area impact of our work: a 1:1 logic-to-interconnect ratio ...................................90
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`5-11 Micro-architecture of a Slice L/M CLB with dual-edged clocking .......................93
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`5-12 Slice M microarchitecture of the memory and shift-register logic ........................97
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`5-13 Architecture of a commercial FPGA DSP accelerator ..........................................99
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`5-14 A commercial dual-port block RAM and its block architecture and datapath ....101
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`5-15 Core schematic and interconnect architecture of a 16-core DSP processor ........102
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`5-16 Example communication applications of the DSP processor ..............................103
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`5-17 The FFT architecture and radix factorizations of different FFT resolutions .......105
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`5-18 An example physical design of a SM macro .......................................................106
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`5-19
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`Illustration of the hierarchical design methodology used for chip integration ....108
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`5-20 Layout examples of a) Slice L, b) Slice M, c) DSP, and d) BRAM CLBs and
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`SMs ......................................................................................................................109
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`5-21 Top level CLB and SM architecture, illustrating scan chain for BL and WL .....111
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`5-22 Area impact of our two FPGAs: a 1:1 logic-to-interconnect ratio.......................112
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`6-1
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`Software mapping flow of commercial FPGA tools and our flow ......................115
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`6-2 A snapshot of a synthesized netlist using our custom standard-cell library ........117
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`6-3
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`The updated software mapping flow for our new FPGA .....................................119
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`6-4 Hierarchical partitioning performed on top-level, and one quadrant ...................121
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`6-5 A routing-preference example for a point-to-point connection, LUT to LUT ....125
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`7-1 A IBOB platform use for Matlab Simulink-based testing infrastructure .............131
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`7-2 An example IBOB Simulink testbench for chip configuration and testing .........132
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`7-3
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`Energy efficiency and power ratio at maximum frequency and minimum energy
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`..............................................................................................................................136
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`7-4
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`Comparison of energy efficiencies against state-of-the-art reconfigurable
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`hardware ...............................................................................................................137
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`7-5 Xilinx evaluation platforms – Kintex-7 KC705 and Virtex-7 KC707 .................139
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`7-6
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`Board layout of the chip-on-board testboard with two FMC connectors ............140
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`7-7
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`Chip photo and summary our 2048-LUT FPGA and our 16K-LUT FPGA ........143
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`8-1
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`Energy and area efficiency from modern VLSI chips and our chips ...................146
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`8-2 NEM relays as PMOS and NMOS-equivalent devices, a static switch, and
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`a SRAM bit-cell ...................................................................................................148
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`8-3 A relay-interconnect concept with CMOS logic on the bottom and NEM-
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`interconnects on the top 2 metal layers ................................................................149
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`LIST OF TABLES
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`I-I
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`ASIC vs. FPGA – efficiency vs. flexibility ........................................................10
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`VI-I
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`Routing time of our original router vs. PathFinder-based router ......................126
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`VII-I
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`Key measurement results from our 2048-LUT FPGA chip ..............................135
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`VII-1I Chip performance comparison against commercial FPGA and ASIC
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`implementations, based on design mapping and conservative
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`timing
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`estimations
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`...........................................................................................................................141
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`VII-III Coarse-grain
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`accelerator
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`performance
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`against
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`commercial FPGA
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`implementations ................................................................................................142
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`ACKNOWLEDGEMENTS
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`
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`It has been six years since I started my graduate life at UCLA, and it has certainly been
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`the best six years of my life so far. First of all, I am wholeheartedly thankful to my advisor,
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`Dejan Marković, for his patience, knowledge, and sheer passion for this work. Additionally, I‟ve
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`also learned a great lot from him about presentation and communication skills.
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`I wish to thank Professor Mani Srivastava, William Kaiser, and Mario Gerla for being on
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`my dissertation committee. Their helpful and thoughtful comments are definitely appreciated.
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`
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`I am also grateful for having the best group members, especially Fang-Li Yuan and
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`Tsung-Han Yu, who have endurance endless nights with me during tape-out madness and chip
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`testing. They are the hardest working colleagues I‟ve ever had, and yet also exert such positive
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`energy. I would also like to acknowledge other lab members, especially Vaibhav Karkare and
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`Yuta Toriyama for incessant discussions in the cubicles, technical or not. It is really difficult to
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`find a group so diverse, and yet so unified; so technically strong, and yet so pleasant and
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`interesting to be around.
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`I sincerely thank my parents for their never-ending care, and for always being my closest
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`teacher and counselor. They shaped me the way I am today, and I am forever indebted to them. I
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`also wish to thank my (soon-to-be-wife) Helen for her daily support and for being the biggest
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`blessing in my life. Above all, I thank my God and Savior. His patience, grace, and love have
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`been my greatest strength.
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`CURRICULUM VITAE
`
`
`EDUCATION
`(GPA 3.76)
`M.S., Electrical Engineering, University of California, Los Angeles,
`2007-2009
`
`B.S., Electrical Engineering and Computer Sciences, University of California, Berkeley,
`
`(GPA 3.8)
`
`2003-2005
`
`Fall 2007 – Spring 2013
`
`
`EMPLOYMENT HISTORY
`Graduate Student Researcher – UCLA Electrical Engineering:
`Design and Optimization of Low-Power ASIC and FPGA
` Developing FPGA with a novel interconnect architecture that significantly reduces
`interconnect area and power by 3-4x compared to existing FPGA architectures. Chips
`fabricated using IBM90, ST65, TSMC65, IBM45SOI, and TSMC40 processes. Single-
`handedly performing all aspects of the project, from chip architecture, circuit design, to
`software tool design. The most recent test chip is by far the largest VLSI chip made in
`UCLA, and is one of the most complex chips made by any academic institution.
` Extensive experience in high-performance, low-power digital circuit design. Developed
`novel circuits for low-leakage power gating and high-speed interconnect performance.
`Also developed a more accurate delay model to compensate for the lack of accuracy in
`logical effort models under low-power optimizations.
`Nano-electro-mechanical Relays
` Designing circuits using nano-electro-mechanical relays, which have infinite off-
`impedance, low on-impedance, and low threshold voltage, making them attractive for
`digital-circuit, power-gating, and especially FPGA applications.
`Word-length Optimization
` Developed and maintained a word-length optimization too to automatically determines
`the optimal word-lengths of every logic block given a quantization-error requirement.
`Very effective for power-performance optimization in the system level, especially when
`combined with architectural optimizations.
`Fall 2005 - Fall 2007
`VLSI Design Engineer - Zoran Corporation, Sunnyvale, CA:
`Designed numerous blocks for HDTV applications, including H*264 decoding, HD video
`capture (component and HDMI), histogram computation, MPEG post-processing, and
`others.
`Involved with the entire design flow, including RTL design, verification, synthesis, timing-
`closure, place & route, ECO, FIB, driver design, SIMD microcode design, and chip-
`testing (using ATPG and FPGA).
`Summer 2005 - Fall 2005
`HDTV Intern - Zoran Corporation, Sunnyvale, CA:
`Developed and maintained a co-simulation environment that runs the RTL testbench in
`parallel with a software model
`Developed Specmen code to randomly generate SIMD instructions for the co-simulation
`testbench.
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`Co-developed a complete set of microcode for H*264 that runs on the SIMD processor,
`including all modes of intra-/inter- prediction and reconstruction, for Luma and Chroma
`modes.
`
`
`HONORS AND AWARDS
`Outstand Dissertation Award, UCLA Electrical Engineering,
`Broadcom Fellowship (co-recipient),
`Jack Raper Award for Outstanding Technology Directions (co-recipient), ISSCC
`Department Fellowship, UCLA,
`High Honors, UC Berkeley,
`
`2013
`2012
`2010
`2007-2009
`2003-2005
`
`
`PUBLICATIONS:
`Journals:
`C. C. Wang, C. Shi, R. W. Brodersen, and D. Markovic, "An Automated Fixed-Point
`Optimization Tool in MATLAB XSG/SynDSP Enviornment," ISRN Signal Processing,
`Volume 2011
`M. Spencer, F. Chen, C. C. Wang, R. Nathanael, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J.
`Jeon, T-J. K. Liu, D. Markovic, E. Alon, V. Stojanovic, "Demonstration of Integrated Micro-
`Electro-Mechanical Relay Circuits for VLSI Applications," IEEE Journal of Solid State
`Circuits, Jan. 2011
`C. C. Wang and D. Markovic, “Delay Estimation and Sizing of CMOS Logic Using Logical
`Effort with Slope Correction,” IEEE Trans. of Circuits and Systems-II, vol. 56, issue 8, pp.
`634-638, August 2009
`
`
`Conferences:
`C. C. Wang, F.-L. Yuan, H. Chen, D. Marković, "A 1.1 GOPS/mW FPGA Chip with
`Hierarchical Interconnect Fabric," in Proc. Int. Symposium on VLSI Circuits (VLSI'11), pp.
`136-137, June 2011
`F. Chen, M. Spencer, R. Nathanael, C. C. Wang, H. Fariborzi, A. Gupta, H. Kam, V. Pott, J.
`Jeon, T-J. K. Liu, D. Markovic, V. Stojanovic, E. Alon, "Demonstration of Integrated Micro-
`Electro-Mechanical Switch Circuits for VLSI Applications," in Proc. IEEE Int. Solid-State
`Conference (ISSCC'10), pp. 26-27, Feb. 2010
`
`
`Magazine Articles:
`D. Markovic, C. C. Wang, L. Alarcon, T.-T. Liu, and J. Rabaey, "Ultralow-Power Design in
`Near-Threshold Region," Proceedings of the IEEE, vol. 98, no. 2, pp. 237-252, Feb. 2010
`
`
`Book Chapters:
`D. Marković and R. W. Brodersen, DSP Architecture Design Essentials (Book Chapter 10 on
`Word-length Optimization), Springer, July 2012
`
`
`Patents:
`C. C. Wang, D. Markovic, “A Radix-3 Network Architecture For Boundary-Less
`Hierarchical Interconnects”, March 2013, Application No. 61/786,676
`C. C. Wang, D. Markovic, “Fine-Grained Power Gating in FPGA Interconnects”, March
`2013, Application No. 61/791,243
`
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`CHAPTER I
`
`Introduction
`
`1.1 The Drive Towards Efficiency
`
`For 50 years, Moore‟s law has driven the rapid scaling in transistor count and feature
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`size. Transistor performance also increased at this pace, essentially doubling its operation
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`frequency with every generation. Few seemed to care that doubling the performance also doubles
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`the power consumption, and by the early 2000s, consumer CPUs have reached over 3 GHz,
`
`consuming around 100 watts of power. It then became clear that frequency scaling is reaching
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`the end of the road: power, thermal, and physical constraints became just as important as circuit
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`performance.
`
`“I don‟t want a kilowatt in my laptop,” said Gordon Moore at the International Solid-
`
`Sates Circuits Conference (ISSCC) Keynote in 2003 [Moore03]. The industry was recognizing a
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`turning point towards efficiency: design tradeoffs that balance performance, power, and area
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`requirements. Often times, obtaining efficiency requires fundamental hardware changes.
`
`“General-purpose hardware is generally not power-efficient," said Shekhar Borkar of Intel at the
`
`same conference. Over the past 10 years, the industry has shifted from high-frequency, single-
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`core CPUS, to a heterogeneous integration of multi-core CPUs and dedicated accelerators.
`
`In 2003, many were concerned to maintain the 100W power budget. But in just a few
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`years, the industry has commercialized sub-10W processors that fit in thin ultra-books, and even
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`sub-1W processors for smartphones. Dictated by the changes in the scaling trend, these products
`
`are designed with efficiency in mind.
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`1
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`1.2 What is Efficiency?
`
`Efficiency, unlike many traditional criteria, requires a combination of metrics. Energy
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`efficiency (or power efficiency) is arguably the most common efficiency metric. It quantifies
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`work per unit energy, and is generally measured in billions of operations per second (GOPS) per
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`milliwatt (GOPS/mW). In VLSI circuits, this translates directly to battery life, thermal limit, and
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`reliability.
`
`One may wonder, for example, how energy efficiency differs from just low power. The
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`difference is in operations. In an extreme case, any chip can consume 0 watts if it‟s off! But that
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`is trivial because it is not performing not performing any operations. A similar analogy applies
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`for performance: many smartphone processors today include 4 or 8 cores, but delivering peak
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`performance in all cores will drain the battery very q