Paper No. 43
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`___________
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`SAMSUNG DISPLAY CO. LTD., and APPLE, INC.,
`Petitioner,
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`v.
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`SOLAS OLED LTD.,
`Patent Owner.
`___________
`
`IPR2020-00140
`Patent 6,072,450
`___________
`
`Record of Oral Hearing
`Held: February 9, 2021
`_____________
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`Trials@uspto.gov
`571-272-7822
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`Before SALLY C. MEDLEY, JESSICA C. KAISER, and
`JULIE HEANEY, Administrative Patent Judges.
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`___________
`
`SAMSUNG DISPLAY CO. LTD., and APPLE, INC.,
`Petitioner,
`
`v.
`
`SOLAS OLED LTD.,
`Patent Owner.
`___________
`
`IPR2020-00140
`Patent 6,072,450
`___________
`
`Record of Oral Hearing
`Held: February 9, 2021
`_____________
`
`Trials@uspto.gov
`571-272-7822
`
`
`
`
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`
`
`Before SALLY C. MEDLEY, JESSICA C. KAISER, and
`JULIE HEANEY, Administrative Patent Judges.
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`IPR2020-00140
`Patent 6,072,450
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`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
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`
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`DAVID A. GARR, ESQUIRE
`
`DAVID CHO, ESQUIRE
`PETER CHEN, ESQUIRE
`JEFF LERNER, ESQUIRE
`JARED FRISCH, ESQUIRE
`Covington & Burling LLP
`One City Center
`850 Tenth Street, N.W.
`Washington, D.C. 20001
`
`DANIEL GIRDWOOD
`Samsung Electronics America, Inc.
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`ON BEHALF OF PATENT OWNER:
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`NEIL A. RUBIN, ESQUIRE
`MARC A. FENSTER, ESQUIRE
`REZA MIRZAIE, ESQUIRE
`Russ August & Kabat
`12424 Wilshire Blvd.
`12th Floor
`Los Angeles, CA 90025
`
`
`The above-entitled matter came on for hearing on Tuesday, February
`9, 2021, commencing at 1:00 p.m., EDT, at the U.S. Patent and Trademark
`Office, by video/by telephone.
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`IPR2020-00140
`Patent 6,072,450
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`P R O C E E D I N G S
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`JUDGE HEANEY: All right. Good afternoon, counsel. I
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`only see one attorney present. Is that because we're in the
`speaker mode?
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`TECHNICAL STAFF: That is correct, Judge.
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`JUDGE HEANEY: Okay. Thank you Alex. This is the
`hearing for IPR 2020- 00140, Samsung Display Co., v. Solas Oled,
`Ltd. Would the parties please introduce counsel beginning with
`Petitioner's counsel.
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`MR. GARR: Yes. Good afternoon, Your Honors. Can you
`see and hear me?
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`JUDGE HEANEY: We can.
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`MR. GARR: Oh, great. I'm David Garr from the law firm
`of Covington & Burling here in D.C., lead counsel for Petitioner.
`I'm joined on video by my Covington colleague and back-up
`counsel, David Cho and with our thanks to the Board, he's
`participating in this hearing as a LEAP practitioner and he and I
`plan to split the argument if that's acceptable.
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`JUDGE HEANEY: Yes. The --
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`MR. GARR: Also with me on the audio line is --
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`JUDGE HEANEY: Go ahead.
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`MR. GARR: Okay, are my Covington colleagues Peter
`Chen, Jeff Lerner and Jared Frisch and also on the phone line
`from real party in interest Samsung Electronics America, Inc., is
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`Daniel Girdwood who's VP and head of ITC Litigation at SEA.
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`JUDGE HEANEY: Thank you. And Patent Owner?
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`MR. RUBIN: Good afternoon, Your Honors. Can you hear
`me?
`JUDGE HEANEY: Yes.
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`MR. RUBIN: Thank you. My name is Neil Rubin with the
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`law firm of Russ August & Kabat. With me are my colleagues
`from Russ August & Kabat, Marc Fenster and Reza Mirzaie, and
`we represent the Patent Owner. Mr. Fenster will be arguing
`today.
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`JUDGE HEANEY: Thank you. And Mr. Garr, have you --
`could you tell us how you and your colleague, Mr. Cho, are
`going to be splitting the argument?
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`MR. GARR: Yes. There are four main disputes. I'll do the
`first two and he will do the second two.
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`JUDGE HEANEY: Great. Thank you. All right. So we
`have approved Petitioner's LEAP practitioner application and
`because of that Petitioner will have 60 minutes to present
`argument today. Patent Owner will have 45 minutes to present
`argument. Petitioner will proceed first to present its case with
`respect to the challenged claims and grounds for which the Board
`instituted trial and may reserve some of its argument time to
`respond to arguments presented by Patent Owner. After that
`Patent Owner will respond to Petitioner's presentation and may
`reserve argument time for surrebuttal. Petitioner, do you want to
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`reserve time for rebuttal?
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`MR. GARR: Yes. We'd like to reserve 20 minutes for
`rebuttal, please.
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`JUDGE HEANEY: And that's on all issues?
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`MR. GARR: Yes.
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`JUDGE HEANEY: Okay. And Patent Owner, would you
`like to reserve time for surrebuttal?
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`MR. FENSTER: Yes, Your Honors. This is Marc Fenster
`for the Patent Owner and we'll reserve 15 minutes for rebuttal,
`please.
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`JUDGE HEANEY: Great. Okay. A couple of other items
`I'd like to clarify about remote hearings before we begin. First,
`our primary concern is your right to be heard. If at any time
`during the proceeding you encounter technical or other
`difficulties that you feel will fundamentally undermine your
`ability to adequately represent your client please let us know
`immediately, for example by contacting the team members who
`provided you with connection information.
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`Second, in order to create the best record for everybody,
`when you're not speaking please mute. Third, each time you
`speak, before you begin speaking please identify yourself. This
`will help the court reporter who is on the audio line to prepare an
`accurate transcript. Fourth, we do have the entire record
`including the demonstratives that were filed yesterday and today
`and when referring to your demonstratives or any paper or
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`IPR2020-00140
`Patent 6,072,450
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`exhibit, please do so clearly and explicitly by providing the slide
`for the demonstratives, the slide number or the page number for
`any other documents and after you've provided the identification
`it would be helpful if you can just pause to give us time to find it
`and to allow the court reporter to give us an accurate transcript
`of the hearing. Finally, we'd like to remind everybody that this
`hearing is open to the public and the transcript will be entered
`into the public record of this proceeding. Are there any
`questions about what we've just covered?
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`MR. FENSTER: Not for Patent Owner, Your Honor.
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`MR. GARR: And none for Petitioner. Thank you.
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`JUDGE HEANEY: All right. So with that I'm going to set
`40 minutes for Petitioner and you may proceed.
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`MR. GARR: Thank you very much. May it please the
`Board again, David Garr for Petitioner. I'd like to note that we
`are presenting argument today on behalf of Petitioner Samsung
`Display Co. Ltd., and it's my understanding that the other
`Petitioners are in the process of withdrawing. During our
`presentation we'll be referring to our slides which have been
`filed as Exhibit 1018 and with that I would ask the Board to
`please begin on slide 2 of our demonstratives and I'll begin
`Petitioner's presentation there.
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`So the petition in this case presented four grounds of
`unpatentability all based on the Utsugi reference either alone or
`in combination with other references but the disputes between
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`Patent 6,072,450
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`the parties that we'll be discussing today relate only to Utsugi.
`There are no disputes on the other references.
`
`Turning to slide 3, please. We have an overview of the
`issues that are in dispute. Before I get into these I'd like to just
`zoom out for a quick moment and say a word about how targeted
`we think the disputes are, especially given the length of some of
`the patent claims in this patent. At a high level, the '450 patent
`generally aims to increase the light emitting area of a pixel by
`having the electroluminescent structure formed to cover the pair
`of transistors that were typically used for each pixel in active
`matrix displays. That's from our petition at page 8 and there's no
`dispute that the Utsugi reference discloses these four aspects of
`the claimed invention.
`
`Turning to what is disputed, we have bullets here on slide
`3. The first and second -- so there are four disputed issues as we
`see them. The first and second issues pertaining to limitations
`requiring an insulation film formed to cover either a selection
`transistor or address lines. I will address those, and the third
`and fourth limitations concern driver circuit and constant voltage
`limitations. Those will be addressed by my colleague, Mr. Cho.
`
`With that, I will turn to the first dispute and ask the Board
`to please turn to slide 5.
`JUDGE KAISER: (Indiscernible) problems hearing?
`MR. GARR: Yes. I am getting a little -- it's a blotchy on
`the display now?
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`Patent 6,072,450
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`JUDGE KAISER: Can you hear me?
`MR. GARR: I can hear you. It looks like I am getting
`some congestion.
`JUDGE KAISER: Judge Heaney has dropped out. I'm also
`having trouble hearing. Oh, it might have resolved now. Can
`you hear me still?
`MR. GARR: I can. Does it appear that I'm the only one
`with the network issue?
`JUDGE KAISER: No. I have one as well though I think it
`may have just resolved. Let's hold for a minute and see if it
`resolves, see if Judge Heaney is able to join again. I apologize
`for some technical difficulties. We'll obviously restore your
`time to make sure that you're heard, so let's take a pause for a
`minute.
`(Pause, due to technical difficulties.)
`
`JUDGE HEANEY: We have Patent Owner's counsel on?
`MR. FENSTER: Yes, Your Honor. I'm still here.
`JUDGE HEANEY: Okay. All right. So I think we're ready
`to start again. Mr. Garr, I did pause the timer so you're at 37 and
`a half minutes.
`MR. GARR: Great.
`JUDGE HEANEY: If you want to resume.
`MR. GARR: Thank you. Thanks for that. I will resume by
`beginning the discussion about element 1[c] and ask the Board to
`please turn back to slide 5 of our demonstratives. The dispute on
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`IPR2020-00140
`Patent 6,072,450
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`this limitation is whether Utsugi teaches an insulation film that
`covers the selection transistor which it calls switching transistor
`Qs and we have a couple of annotated figures here illustrating
`the display structure of Utsugi. On the left figure 4 shows a plan
`view of one pixel from the top and it has two transistors, QI near
`the top and Qs near the bottom. On the right of Utsugi shows a
`cross-section of a pixel. As you can see in purple it includes a
`silicon dioxide insulation film which is shown here as covering
`transistor QI. Now this figure doesn't depict the transistor Qs
`but that's s imply an artifact of the fact that it was where the
`cross-section was taken, that is it's displaying a cross-section
`along the red line AA.
`Now both sides agree that it would be necessary to have
`insulation above the other transistor Qs in order to avoid a short
`circuit and indeed if I can skip ahead please two slides down to
`slide 7, Utsugi teaches a manufacturing process that results, as
`we've explained, in the silicon dioxide insulation layer being
`formed to cover transistor Qs just as it covers transistor QI. This
`process is recited in column 7 through 8 of the reference and we
`have slides walking through the steps which I'll go through
`rather quickly if that's possible. But the basic concept is that
`Utsugi teaches a deposition and patterning process in which
`layers are built up and each layer is formed first by deposition
`and then patterned to etch away certain portions of the layer.
`Turning to slide 8. The process in this case begins with a
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`IPR2020-00140
`Patent 6,072,450
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`glass base that's shown in peach. On slide 9 it next deposits and
`etches a metal layer shown in red which is used to form the gate
`electrodes of the two transistors. On slide 10 we have a green
`layer depicting a first silicon dioxide layer that's used for gate
`insulation. It's deposited and etched to open up a contact hole.
`Slide 11 shows the, in amber, the deposition and patterning of
`the amorphous silicon which is used at the active layer of the
`transistors and then slide 12 has another metal layer, blue, shows
`deposition and patterning of the metal elements that form the
`source and drain electrodes of the two transistors.
`And this is what brings us to slide 13. I'll ask you to turn
`there. This is the slide that depicts the formation of the relevant
`silicon dioxide layer shown in purple where the sort of parties
`disputes pertain to and so this layer is formed just after the two
`transistors and as the specification explains on the left, it says
`that a layer of silicon dioxide SiO2 is let grow 200 nanometers
`before an etching to open the second contact hole. Now if you
`grow a layer with the deposition process and etch it to open
`contact holes an artisan will understand that the resulting layer
`will cover everything except where the contact holes are. This is
`what our expert has explained and the conclusion is reinforced
`we believe by figure 5 showing of the silicon dioxide layer as
`uniformly covering everything except for the contact hole. In
`that regard, this purple layer looks a lot like the uppermost
`layers 52 and 54 which are shown as unbroken layers in this
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`IPR2020-00140
`Patent 6,072,450
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`cross-section and described by the reference as being formed
`over the entire region of the display panel, that is the whole
`array of pixels and that you can see in column 6, lines 56
`through 59 about those uppermost layers.
`So the argument, and we'll talk about the counter-argument
`that's been raised, but the basic point we've explained is that a
`skilled artisan would understand that the silicon dioxide layer
`likewise extends across the entire display array except in the
`location of the contact holes where the reference tells you to
`open them up through etching.
`Turning to slide 15, we'll begin addressing Patent Owner's
`counter-arguments. The first as you --
`JUDGE KAISER: Mr. Garr, this is Judge Kaiser. Before
`you do that, so it seems to me that your -- so you have both an
`anticipation ground and an obviousness ground.
`MR. GARR: Yes.
`JUDGE KAISER: But if we focus on your anticipation
`ground for a moment, are you making an assertion that when you
`sort of look at figure 4 and 5 together that that's enough to
`disclose the insulation layer as recited or are you sort of relying
`on your expert to fill in some gaps there?
`MR. GARR: Well I would say that it's figures 4 and 5 and
`the specification in columns 6, 7 and 8 and especially the
`discussion going back to slide 13 that we have excerpted in the
`top left. The point that we've explained for anticipation is that
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`IPR2020-00140
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`the results of this process would be understood by a skilled
`artisan to lead to the silicon dioxide layer being present
`everywhere except where the contact holes are and so while it
`doesn't have a single figure that is showing the location of the --
`it doesn't have a cross-section that sort of gets at where the
`second transistor Qs is but a skilled artisan reading the
`specification would understand this to be describing the
`formation of a structure where that layer is over both transistors
`in view of the figures and the description that Dr. Fontecchio
`cited to in his declaration. So we don't see this as filling gaps,
`we see this as explaining what a skilled artisan would take from
`the specification an d understanding what the results are
`following the disclosed process would be.
`Okay. I would ask that you please turn to slide 15. The
`first counter-argument raised by the other side is that the silicon
`dioxide layer may not be deposited over the transistor Qs in the
`first place because a mask might potentially be used to prevent it
`from being deposited there. But there's nothing in the reference
`however that even suggests use of this mask and I won't read the
`quotes but Solas's expert acknowledged this we think pretty
`clearly at his deposition.
`Similarly slide 16 has the second counter argument that's
`been raised. We see this also as an instance of speculation and
`what they say is even if the silicon dioxide layer, I'm on slide 16
`at the top now, is deposited over transistor Qs. That layer may
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`IPR2020-00140
`Patent 6,072,450
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`be removed by etching. But again while there's no basis in the
`reference for this speculation the reference teaches you it has an
`etching process but it describes the etching as taking place to
`remove the portion over the contact holes and without a
`disclosure or suggestion that you would have additional etching,
`we see both of these arguments as sort of hypotheticals that have
`been raised but which aren't disclosed or even suggested by the
`reference. In other words, we've explained why the process
`that's set forth in the reference results in the layer being above
`the transistor and their counter argument is that it might not
`happen if you read in additional masking or etching that are
`admittedly neither disclosed nor suggested in the reference and
`we don't think that's the right perspective for assessing what a
`reference teaches.
`JUDGE KAISER: Well, Mr. Garr, this is Judge Kaiser
`again. I guess this goes back to the question that I had before
`because, you know, obviously you as the Petitioner have the
`burden here and as I understand what Patent Owner is saying
`they're not saying, you know, they're not speculating that there is
`this step. What they're saying is, you know, that a person of
`ordinary skill in the art might not or would not necessarily see
`the reference in the way that you've suggested because the
`reference doesn't necessarily tell you exactly what happens with
`Q sub s and so --
`MR. GARR: Well --
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`JUDGE KAISER: -- that, you know, I think what Patent
`Owner is trying to do here is undercut what essentially is sort of
`an inherency argument on your part. So how do you respond to
`that?
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`MR. GARR: I certainly think that you're -- I certainly
`agree with how you've characterized the counter -argument but I
`don't think that tracks the proper assessment of the burdens as
`they articulated it. In other words, we believe that we have
`provided evidence and we've cited to that evidence of showing
`that this process would result in this outcome and under a
`preponderance standard looking to the disclosures of the
`specification and the figures we think we've shown under a
`preponderance standard that this process would lead to this result
`and their counters are to read in hypotheticals that aren't
`suggested in the reference. They're speculation about things that
`aren't there and in our view that unsupported speculation can't
`avoid anticipation that's been shown based on the actual
`disclosures and, you know, you raised the comment about
`inherency. That's not the way we've articulated it but, you know,
`certainly the natural result of following this process unless you
`read in things that aren't taught are, you know, that result is that
`you would have the silicon dioxide layer covering both
`transistors which, in fact, would result in insulation being
`present where both sides agree insulation needs to be.
`So we've phrased it in terms of disclosure and based on our
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`expert's testimony we think that a skilled artisan would
`understand this sort of basic deposition process, deposition and
`patterning process, to lead to a result as he's explained it to be
`but if there's a question as to whether it's expressed as certainly
`the natural results of following the process and I don't think it's
`really appropriate to look at the process and read in other steps
`that aren't even suggested. I think that would get away from the
`-- I think being able to read in hypotheticals that aren't disclosed
`or suggested into a process would sort of upend the notion of
`inherent disclosure and the inherent disclosure is what's the
`result of following what's taught, not what's the result of
`following what's taught and then some other stuff that might be
`in there if, or isn't in there but might be undertaken
`hypothetically by someone bringing in extra steps.
`And the other point on that and I think we've really
`addressed this more under the cite of obviousness, but both sides
`do agree that there needs to be an insulation layer between, over
`that transistor Q s, between it an the electrode that's above it so
`that the alternative that's been suggested by the other side would
`both entail removing the silicon dioxide layer that is taught and
`replacing it with another insulation layer. So again, this is a
`series of additional steps that aren't in the reference and we don't
`think unsupported speculation from an expert about hypotheticals
`can undercut or should undercut the showing we made based on
`the actual disclosures.
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`I will turn to the obviousness theory because I just want to
`make sure I address that. I sort of started talking about it but I
`would ask you to please turn to slide 17 and, you know, again we
`think under a preponderance standard we've shown that this
`would be disclosed. If there's any question on that in the Board's
`mind we think we have a very powerful and straightforward
`stand- alone obviousness case. Again, both experts agree that
`insulation needs to be in this location above the Qs transistor so
`the obviousness theory so to speak is simply that you would
`leave that insulation layer in place above the transistor and not
`undertake an undisclosed and unnecessary action of masking or
`patterning the insulation to remove it if, you know, which of
`course would then result in having to add it back in through
`another undisclosed process.
`And as a final point on this limitation I would like to
`address a couple of the Patent Owner's demonstratives since they
`make some representations about the record being unrebutted and
`we think these would benefit from clarification. So I would ask
`the Board if possible to please pull up the Patent Owner
`demonstratives and I'll direct you to slide 8. This slide, for
`example, asserts at the top that the unrebutted post-Institution
`record shows that the cover limitations are not obvious. We
`certainly disagree with that for the reasons we explain in our
`reply, but we didn't feel the need to submit a rebuttal expert
`declaration. We certainly think the record post-Institution
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`continues to show that the limitations are obvious including for
`the reasons I just mentioned.
`I would ask you to turn to slide 9 of the Patent Owner's
`slides as well. This continues to discuss what they call the
`unrebutted post-Institution record and includes an opinion from
`their expert that there are again other ways that one could
`theoretically insulate the transistor Qs; that is if you read in an
`additional step of removing that silicon dioxide insulation film
`you would then need to bring in another alternative type of
`insulation.
`I think the point I would like to just make here is we have
`rebutted this contention as well in our reply where we explain
`that these hypothetical alternatives would require additional
`process steps increasing cost and complexity for no reason.
`That's in our reply at 10 and as we further mention there, Mr.
`Flasck himself shown here in the slide was unable to articulate at
`deposition any reason why a POSA would undertake these
`additional steps when you already have the silicon dioxide layer
`present in the reference. That's cited, his testimony we've cited
`in our reply brief at page 11.
`So unless there are more questions on that I will briefly
`cover element 15[f] which tracks a lot of the issues we've been
`discussing for one today. Okay.
`With that I'll ask you to please turn to our slides and go to
`slide 21 of Petitioner's demonstratives. The dispute for 15[f] is
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`whether Utsugi teaches an insulation film formed to cover its
`scan electrode lines which map to the claimed address lines and
`we've explained in our briefs how this limitation is taught for
`reasons very similar to element [1], that is the manufacturing
`process results in a silicon dioxide layer that extends across the
`entire array except for the location of the contact holes and again
`we think this is sufficient to show disclosure under a
`preponderance standard. Again, the only reason that the layer
`wouldn't be there according to Patent Owner, is if you take some
`sort of masking or etching in the location of the scan lines but
`there's nothing in the reference that contemplates this and again,
`to the extent there are questions in the Board's mind whether we
`have adequately shown anticipation or direct disclosure we have
`what we think is a very powerful and straightforward stand-alone
`obviousness case.
`Briefly turn to slide 23. The obviousness theory again is it
`would have been obvious to just leave the silicon dioxide in
`place above the scan lines which would entail simply not
`undertaking unnecessary steps of masking or unnecessary
`patterning. The Patent Owner hasn't identified any benefit to
`undertaking one of these undisclosed steps, as we discussed in
`the reply at page 20 and we've identified a benefit of actually
`having it there in terms of mitigating a parasitic capacitance.
`So happy to take any further questions. If not, I will invite
`my colleague Mr. Cho to address the other two disputes.
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`JUDGE HEANEY: And I'll note that you have around 17
`minutes left.
`MR. GARR: Thank you.
`MR. CHO: Your Honors, I'm David Cho who is arguing for
`Petitioner. May I proceed?
`JUDGE HEANEY: Yes. Good afternoon.
`MR. CHO: I plan to argue for about 14 minutes and reserve
`the remainder of the time. I'll first address limitations 15[j] and
`[k] and I welcome the Board's questions at any time. Turning to
`slide 25. Patent Owner has raised arguments about the first and
`second driver circuit in 15[j] and [k] but as we explained in our
`briefs these limitations are taught and suggested by Utsugi. As
`reflected in the claim language the first driver circuit is used to
`provide address signals in sequence and the second driver circuit
`is used to provide image data signal to display images.
`I'll first explain how these features are taught and
`anticipated by Utsugi and by d irecting your attention to slide 26.
`Patent Owner doesn't dispute that Utsugi discloses selectively
`supply an address signal in sequence as recited in 15[j] as shown
`in the upper left part of the slide or that Utsugi discloses
`applying image data through a signal electrode lines as recited in
`15[k] and we have depicted and noted this in figure 3.
`So the question is just whether Utsugi teaches that these
`functions are performed by driver circuits. Now while Utsugi
`doesn't have a figure showing a specific driver circuit design, a
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`POSA would have understood from reading this reference that it
`would use driver circuits to supply the address signals and image
`data. Dr. Fontecchio explained that a POSA would appreciate
`that some form of circuitry would be necessary to perform these
`operations.
`Now Patent Owner's own response in its response is that a
`first driver circuit may be unnecessary because the address line
`signal perhaps could be applied randomly or manually. This is
`in their response page 21. However, it's clear that Utsugi
`discloses supplying address line signals sequentially, not in a
`random manner as I've shown you in the previous slide. Also
`nowhere does --
`JUDGE HEANEY: And, I'm sorry Mr. Cho, can you just
`reorient us as to which slide you're on?
`MR. CHO: Yes. Sorry, I misspoke. I inte nded to mean the
`current slide, slide 26.
`JUDGE HEANEY: Okay.
`MR. CHO: As I've shown you in the upper left portion
`Utsugi discloses that the supply of address signal is done
`sequentially, not in a random manner. So Patent Owner's
`argument as to randomness is without merit. Thank you for the
`clarifying question. And I'd also like to note that nowhere does
`Utsugi describe any manual selection of the scan electrodes for
`the address line so we think that the --
`JUDGE KAISER: Mr. Cho. This is Judge Kaiser. I want
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`to go back to your argument about the driver circuit and in
`particular your -- the expert's testimony that you pointed us to on
`slide 26 that talks about that a person of ordinary skill in the art
`would appreciate that some form of circuitry would be necessary
`to perform this operation.
`MR. CHO: Yes.
`JUDGE KAISER: I understand Patent Owner's argument to
`be that, essentially that Petitioner's contentions read out the term
`driver from this claim limitation so that pretty much if there's
`any sort of circuitry that performs the function that would be a
`driver circuit. So how do you respond to their argument that
`essentially your contentions are reading that driver term out of
`the claim?
`MR. CHO: Sure. We firmly disagree that we're reading
`out any structure from these claims and I think if you turn to
`slide 27 this will help my explanation. So both experts have
`agreed that the recited driver circuits don't require any particular
`structure and we think that the Patent Owner's argument that
`we're reading out this limitation is a misunderstanding because
`as both experts agree, there's nothing in the recited driver
`circuits that require some special or particular circuitry that
`would be -- that requires something more than is taught by and
`understood by reading Utsugi to satisfy those elements.
`So in that regard we disagree that we are reading out the
`structure limitations and what the I submit -- respectfully
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`submitted that when a POSA reads Utsugi it would understanding
`it's performing these operations and would have known that one
`would use driver circuits in order to perform those operations
`and therefore one would know that they would have to use driver
`circuits.
`I hope that answers your question and furthermore, in any
`event, even if it were the case that Utsugi did not disclose driver
`circuits these limitations would have been obvious and I would
`like to turn to slide 28 to highlight the main evidence. A POSA
`would understand that circuitry would be required to implement
`the driving of the address lines and image data disclosed by
`Utsugi and so it would have been obvious to use driver circuits,
`and I would just like to first point to Patent Owner's own expert,
`Mr. Flasck's deposition. He agreed that in his deposition that,
`"In the vast majority of cases for image displays, based on
`this type of OLED technology, there would be driver circuits."
`So we think that this admission really underscores that
`driver circuits would have been the obvious way t
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