Paper No. 20
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG DISPLAY CO., LTD. AND DELL INC.,
`Petitioners,
`
`v.
`
`SOLAS OLED LTD.,
`Patent Owner.
`____________
`
`Case No. IPR2020-00140
`U.S. Patent No. 6,072,450
`____________
`
`
`PATENT OWNER’S RESPONSE TO
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG DISPLAY CO., LTD. AND DELL INC.,
`Petitioners,
`
`v.
`
`SOLAS OLED LTD.,
`Patent Owner.
`____________
`
`Case No. IPR2020-00140
`U.S. Patent No. 6,072,450
`____________
`
`
`PATENT OWNER’S RESPONSE TO
`PETITION FOR INTER PARTES REVIEW
`
`
`
`Case No. IPR2020-00140
`U.S. Patent No. 6,072,450
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`TABLE OF CONTENTS
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`INTRODUCTION .................................................................. 1
`I.
`II. OVERVIEW OF THE ’450 PATENT ...................................... 1
`Summary of the Patent .................................................................... 1
`A.
`The Prosecution History of the ’450 patent .................................... 4
`B.
`III. LEGAL STANDARD FOR PETITION REVIEW .................... 5
`IV. LEVEL OF A PERSON OF ORDINARY SKILL IN THE ART 7
`V. CLAIM CONSTRUCTION ..................................................... 8
`VI. THE PETITION FAILS TO ESTABLISH THAT UTSUGI
`OR 15–16 .............................................................................. 9
`A.
`contact hole” ................................................................................. 10
`B.
`drive transistor” ............................................................................. 14
`C.
`constant voltage is applied to said second electrode” ................... 15
`D.
`correspondence with said drive transistors” .................................. 18
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`Limitation 15[f]: “an insulation film formed over said substrate so
`as to cover said drive transistors, said address lines and said data
`lines, said insulation film having contact holes formed in
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`ANTICIPATES OR RENDERS OBVIOUS CLAIMS 1–2, 4–8,
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`Limitation 1[c]: “an insulation film formed over said substrate so
`as to cover said active elements, said insulation having at least one
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`Limitations 4[a] / 4[b]: “The display apparatus according to claim
`1, wherein said active elements are a selection transistor . . . and a
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`Claim 8: “The display apparatus according to claim 1, wherein a
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`E.
`data to said data lines” .................................................................. 21
`VII. THE PETITION FAILS TO ESTABLISH THAT CLAIM 3 IS
`EIDA ................................................................................... 25
`VIII. CONCLUSION .................................................................... 25
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`Limitation 15[j]: “a first driver circuit for selectively supplying
`said address signal to said address lines in sequence; and” /
`Limitation 15[k]: “a second driver circuit for supplying said image
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`OBVIOUS OVER THE COMBINATION OF UTSUGI AND
`MANABE OR THAT CLAIMS 9, 11–13, AND 17–18 ARE
`OBVIOUS OVER THE COMBINATION OF UTSUGI AND
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`Cases
`
`TABLE OF AUTHORITIES
`
`Ariosa Diagnostics v. Verinata Health, Inc.,
`805 F.3d 1359 (Fed. Cir. 2015) ................................................................. 6
`
`Cisco Systems, Inc. v. C-Cation Techs., LLC,
`IPR2014-00454, Paper 12 (PTAB, Aug. 29, 2014) ................................... 7
`
`Edmund Optics, Inc. v. Semrock, Inc.,
`IPR2014-00583, Paper 50 (PTAB, Sep. 9, 2015) ..................................... 6
`
`Harmonic Inc. v. Avid Tech., Inc.,
`815 F.3d 1356 (Fed. Cir. 2016) ................................................................. 5
`
`In re Magnum Oil Tools Int’l, Ltd.,
`829 F.3d 1364 (Fed. Cir. 2016) ................................................................. 5
`
`SAS Inst., Inc. v. Iancu,
`138 S. Ct. 1348 (2018) .............................................................................. 5
`
`Wasica Finance GMBH v. Continental Auto. Systems,
`853 F.3d 1272 (Fed. Cir. 2017) ................................................................. 6
`
`
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`Constitution and Statutes
`Regulations
`
`35 U.S.C. § 312(a)(3) ............................................................................... 5, 22
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`
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`37 C.F.R. § 42.104(b)(2) .............................................................................. 22
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`37 C.F.R. §42.6(a)(3) ..................................................................................... 6
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`37 C.F.R. §42.65(a) ........................................................................................ 6
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` PATENT OWNER’S EXHIBIT LIST
`
`Description
`Declaration of Richard A. Flasck
`Curriculum Vitae of Richard A. Flasck
`Excerpts of Fundamentals of Microfabrication and
`Nanotechnology (3rd ed. 2012)
`Declaration of Adam Fontecchio, Ph.D. in IPR2020-
`00320
`Transcript of September 10, 2020 Deposition of Dr.
`Adam Fontecchio
`Supplemental Claim Construction Order dated Septem-
`ber 23, 2020
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`Exhibit No.
`2001
`2002
`2003
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`2004
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`2005
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`2006
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`iv
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`I.
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`INTRODUCTION
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`The petition relies on a single reference, Utsugi to allegedly anticipate or
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`render obvious the independent claims of the ’450 patent. However, as set
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`forth below this reference fails to disclose or render obvious key limitations
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`of the independent claims, such as the requirement of an insulating film cov-
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`ering the “active elements” and the requirement of driver circuits. Due to these
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`fatal flaws and the other reasons set forth below, Solas respectfully asks that
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`petitioners’ challenges to the claims be rejected.
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`II. OVERVIEW OF THE ’450 PATENT
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`A.
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`Summary of the Patent
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`The ‘450 patent, titled “Display Apparatus,” was filed by Hiroyasu
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`Yamada, et al. on Nov. 21, 1997 and was issued on June 6, 2000. It claims a
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`priority date of Nov. 28, 1996.
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`Casio, the original assignee of the ’450 patent was a pioneer in the de-
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`velopment of practical and high performing displays utilizing organic light
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`emitting diodes (OLEDs). The ’450 patent taught innovative designs for “ac-
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`tive matrix” OLED displays with a high ratio of the area of the light emitting
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`elements to the overall display area. The invention allowed the development
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`of displays with high brightness, long life, and without various forms of per-
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`formance degradation that plagued prior art designs. (See, Ex. 1001 at 2:66–
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`3:7, 4:19–25, 9:9–19; Ex. 2001, ¶ 21.)
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`The ‘450 patent describes an active matrix type display apparatus to ad-
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`dress the problems in the prior art. One such problem in the prior was that
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`larger numbers of anode lines and cathode lines in OLED displays made it
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`“difficult to display a highly precise image.” (Ex. 1001 at 1:42-46.) Prior art
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`displays included “passive matrix” OLEDs (which had no active elements at
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`each pixel) and “active matrix” OLEDs (with active elements such as transis-
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`tors at each pixel). (Ex. 2001, ¶ 22)
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`Prior art displays often used a bottom emission design deposited directly
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`on the glass substrate. It is important to keep light away from thin film tran-
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`sistors, which if not prevented may cause the transistors to malfunction. (see
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`Paper 9, at 4) which also reduces the brightness and/or reduces the lifetime of
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`the OLED layer. (See, Ex. 1001 at 1:58-2:32 and Fig. 22, 23; Ex. 2001, ¶ 23.)
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`The ‘450 patent discloses an architecture to “provide a display apparatus
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`which has a light emitting area enlarged to as to emit light at a satisfactorily
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`high luminescence even though a voltage applied to an EL layer is low, and
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`which has a long luminance life.” Paper 9, at 5. According to an embodiment
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`of the ’450 patent, the problems with prior art designs are addressed with a
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`top emission OLED design with an insulating layer and contact hole (“via”)
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`to connect to the array substrate. This allows the useful area for OLED mate-
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`rial to be improved while the transistors are shielded light from the OLED
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`layer. (Ex. 2001, ¶ 24.)
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`
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`B.
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`The Prosecution History of the ’450 patent
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`
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`The application that led to the ’450 patent, Application No. 08/976,217
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`(“’217 application”) was filed on November 21, 1997. The ’217 application
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`claimed priority to two Japanese patent applications, filed on November 26,
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`1996.
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`On August 31, 1999, the Patent Office mailed a non-final rejection of
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`certain claims of the ’217 application under 35 U.S.C. §§ 102 and 103. In
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`response, on November 30, 1999, the applicant provided an amendment to
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`address the issues raised in the Patent Office action dated August 31, 1999.
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`The ’217 application was allowed on January 14, 2000, and issued as
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`the ’450 patent on June 6, 2000.
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`III. LEGAL STANDARD FOR PETITION REVIEW
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`The petitioner has the burden to clearly set forth the basis for its chal-
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`lenges in the petition. Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363
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`(Fed. Cir. 2016) (citing 35 U.S.C. § 312(a)(3) as “requiring IPR petitions to
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`identify ‘with particularity . . . the evidence that supports the grounds for the
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`challenge to each claim’”). A petitioner may not rely on the Board to substi-
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`tute its own reasoning to remedy the deficiencies in a petition. SAS Inst., Inc.
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`v. Iancu, 138 S. Ct. 1348, 1355 (2018) (“Congress chose to structure a process
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`in which it’s the petitioner, not the Director, who gets to define the contours
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`of the proceeding.”); In re Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1381
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`(Fed. Cir. 2016) (rejecting the Board’s reliance on obviousness arguments that
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`“could have been included” in the petition but were not, and holding that the
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`Board may not “raise, address, and decide unpatentability theories never pre-
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`sented by the petitioner and not supported by the record evidence”); Ariosa
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`Diagnostics v. Verinata Health, Inc., 805 F.3d 1359, 1367 (Fed. Cir. 2015)
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`(holding that “a challenge can fail even if different evidence and arguments
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`might have led to success”); Wasica Finance GMBH v. Continental Auto. Sys-
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`tems, 853 F.3d 1272, 1286 (Fed. Cir. 2017) (holding that new arguments in a
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`reply brief are “foreclosed by statute, our precedent, and Board guidelines”).
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`To the extent that the petition relies on an expert declaration, it must be
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`more than conclusory and disclose the facts underlying the opinion. See 37
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`C.F.R. §42.65(a) (“Expert testimony that does not disclose the underlying
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`facts or data on which the opinion is based is entitled to little or no weight.”);
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`Edmund Optics, Inc. v. Semrock, Inc., IPR2014-00583, Paper 50 at 8 (PTAB,
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`Sep. 9, 2015) (affording little or no weight to “experts’ testimony that does
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`little more than repeat, without citation to additional evidence, the conclusory
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`arguments of their respective counsel.”). Nor may the petition rely on the ex-
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`pert declaration to remedy any gaps in the petition itself. 37 C.F.R. §42.6(a)(3)
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`(“Arguments must not be incorporated by reference from one document into
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`another document”); see also Cisco Systems, Inc. v. C-Cation Techs., LLC,
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`IPR2014-00454, Paper 12 at 9 (PTAB, Aug. 29, 2014) (“This practice of cit-
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`ing the Declaration to support conclusory statements that are not otherwise
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`supported in the Petition also amounts to incorporation by reference.”).
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`IV. LEVEL OF A PERSON OF ORDINARY SKILL IN THE
`ART
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`Based on the technologies disclosed in the ‘450 patent, a person of ordi-
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`nary skill in the art would include someone who, at the time of the invention,
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`had, (i) a Bachelor’s degree in Electrical Engineering, Physics, and/or Mate-
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`rials Science and Engineering, or equivalent training, and (ii) approximately
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`two years of experience working in design and development related to active
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`matrix-OLED displays. (Ex. 2001, ¶ 30.) Lack of work experience could have
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`been remedied by additional education, and vice versa. (Id.) Such academic
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`and industry experience would be necessary to appreciate what was obvious
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`and/or anticipated in the industry and what a POSITA would have thought and
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`understood at the time. (Id.)
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`Petitioner contends that a POSITA “would have had a relevant technical
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`degree in Electrical Engineering, Computer Engineering, Materials Science,
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`Physics, or the like, and experience in active matrix display design and elec-
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`troluminescence.” (Petition at 13.) This definition of the level of ordinary skill
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`errs to the extent that it suggests that any amount of experience is sufficient,
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`no matter how brief. (Ex. 2001, ¶ 31.) However, the arguments in this response
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`apply under petitioners’ definition of level of ordinary skill as well.
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`V. CLAIM CONSTRUCTION
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`Petitioners contend that no specialized constructions of any of the claim
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`terms are necessary. (Petition at 13.) However, in proceedings before the dis-
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`trict court where Solas has asserted the ’450 patent against Samsung, the par-
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`ties have agreed on constructions for certain of the patent claim terms. (Ex.
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`1012.)
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`Claim Terms
`“active elements”
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`“wherein said at least one
`first electrode has a rough
`surface which is in contact
`with the said organic electro-
`luminescent layer”
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`
`
`Agreed Constructions
`“circuit elements that have gain or that direct
`current flow, e.g., transistors”
`“wherein said at least one first electrode is
`formed to have a substantially uneven sur-
`face in contact with the organic electrolumi-
`nescent layer”
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`On September 23, 2020, the district court hearing the litigation between
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`Solas and Samsung issued a supplemental claim construction order, to resolve
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`certain disputes between the parties that arose during summary judgment in
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`that case. (Ex. 2006.) The district court adopted the following additional con-
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`struction (Ex. 2006 at 14):
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`Claim Terms
`“cover”
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`Court’s Constructions
`“lie over the surface of”
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`In addition, the parties had disputed whether the term “said active ele-
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`ments” in the claims necessarily mapped onto all active elements in a device
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`or could be mapped onto a subset of two or more active elements. The court
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`held that the latter view is correct, stating: “the Court holds that Plaintiff may
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`map its infringement read of the claim to a subset of the active elements in the
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`accused devices.” (Ex. 2006 at 9.)
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`Unless otherwise noted, the arguments set forth in this declaration apply
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`both under these constructions and under the plain meaning of the terms, with-
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`out any explicit construction.
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`VI. THE PETITION FAILS TO ESTABLISH THAT UTSUGI
`ANTICIPATES OR RENDERS OBVIOUS CLAIMS 1–2,
`4–8, OR 15–16
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`The Petition contends that Claims 1–2, 4–8, and 15–16 are anticipated
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`by, or alternatively obvious over, Utsugi. As explained below, the Petition
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`fails to establish that independent claims 1 and 15 are anticipated or obvious
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`and also fails to establish that limitations of dependent claims 4 and 8 are
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`disclosed in or obvious over Utsugi. The same failures to show invalidity in
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`the independent claims apply to dependent claims 2, 5–7, and 15–16.
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`A. Limitation 1[c]: “an insulation film formed over said substrate
`so as to cover said active elements, said insulation having at
`least one contact hole”
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`The Petition and accompanying Fontecchio declaration do not establish
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`that Utsugi discloses limitation 1[c] or that it renders this limitation obvious.
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`Fontecchio Report ¶¶ 151–155, 223–225. (Ex. 2001, ¶ 51.)
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`For the “active elements” in this limitation, petitions identify the “cur-
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`rent-controlling transistor QI” and “switching transistor QS” of Utsugi. (Peti-
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`tion at 24; Ex. 1003 at 6:19–23.) For the “insulation film” in this limitation,
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`petitioners identify the upper layer of the two layers labelled “SiO2” in Figure
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`5 of Utsugi:
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`(Petition at 25.)
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`Figure 5 of Utsugi shows only one of the “active elements,” “current-
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`controlling transistor QI.” As Dr. Fontecchio and Petitioners acknowledge,
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`Figure 5 does not show the “switching transistor QS.” (Ex. 1007 ¶ 168.) How-
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`ever, Petitioner does not explain or cite any evidence establishing that the
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`“SiO2” layer from Figure 5 is “formed over” or “cover[s]” this active element,
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`as required by the claim under Petitioner’s invalidity theories. Indeed, during
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`his deposition, Dr. Fontecchio confirmed that no figure of Utsugi shows an
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`insulating layer covering the switching transistor:
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`Q. Okay. Now turning to figure 5, would you agree that figure 5
`does not show the transistor QS?
`A. I would agree that it doesn’t -- it's not shown in figure 5 --
`QS is not shown in figure 5.
`(Ex. 2005 at 25:21–25)
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`Q. The only figure in Utsugi that expressly depicts the insulat-
`ing layer is figure 5; would you agree?
`A. I would agree that figure 5 is the one that expressly depicts
`the insulating layer, the cross-section -- the cross-section figure.
`I’m sorry.
`(Ex. 2005 at 26:20–27:3)
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`The SiO2 layer described in Utsugi does not necessarily cover the tran-
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`sistors (Qs). (Ex. 2001, ¶ 54.) As an initial matter, as Petitioners acknowledge,
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`the SiO2 layer may not be deposited over QS in the first place because a mask
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`is used to prevent it from being deposited there. (Ex. 1007 ¶¶ 84, 147; Ex.
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`2001, ¶ 54.) Petitioners acknowledge that even if the SiO2 layer is deposited
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`over QS, that layer may be removed by etching, for example as part of the
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`same etching step used to form the “second contact hole 56B.” (Ex. 1007
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`¶¶ 84, 147; Ex. 2001, ¶ 54.) Nothing in Utsugi indicates whether the SiO2
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`layer covers QS or not. (Ex. 2001, ¶ 54.)
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`Dr. Fontecchio states “it would be important for the insulation layer to
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`cover the source and drain electrodes” of QS to prevent a short between those
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`electrodes and the “electron injection electrode” 55. (Ex. 1007 ¶ 84.) How-
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`ever, covering the source and drain electrodes with an insulating layer is not
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`the only, most effective, or most efficient way to avoid such a short. (Ex. 2001,
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`¶ 55.) For instance, a different insulating material could be deposited on the
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`source and drain electrodes, which could take the form of a different insulating
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`layer patterned so as to cover the QS source and drain electrodes. (Id.) Alter-
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`natively, the upper surfaces of the source and drain electrodes could be oxi-
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`dized to form an insulating film, using known techniques such as thermal
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`oxidation or anodic oxidation. (Id.; Ex. 2003, Fundamentals of Microfabrica-
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`tion and Nanotechnology (3rd ed. 2012), at 242–244.) Indeed, Dr. Fontecchio
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`has described in a declaration filed in support of Samsung’s challenge to a
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`different Solas patent how conductors can be oxidized to form insulating lay-
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`ers. (Ex. 2004 ¶¶ 189–191; Ex. 2001, ¶ 55.)
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`Petitioners argue that it would have been obvious to modify Utsugi to
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`satisfy this limitation based upon figure 23 of the ’450 patent. (Petition at 55–
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`56.) However, the figures and disclosures of a patent are generally not prior
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`art to that patent, as they are not “prior” to the patent, and reliance on the
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`patent’s own disclosure as an obviousness motivation is a strong indication of
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`improper use of hindsight. While Figure 23 is mentioned in the “Description
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`of the Related Art” section of the ’450 patent, ’450 patent at 1:58, it is intro-
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`duced as a design “[p]roposed as a display apparatus free from the above-
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`described problems” in the prior art. ’450 patent at 1:47–49. Where is no evi-
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`dence that Figure 23 of the ’450 patent was actually known in the prior art.
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`(Ex. 2001, ¶ 56.) Insulation film 104 in Figure 23 does not have a “contact
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`hole,” as this limitation requires (Id.):
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`The Petition does not explain how a contact hole would be formed in this
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`insulation film, or how that contact hole could connect the “first electrode” to
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`the “active elements,” as required by the ’450 patent claims. (Ex. 2001, ¶ 57.)
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`B.
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`Limitations 4[a] / 4[b]: “The display apparatus according to
`claim 1, wherein said active elements are a selection
`transistor . . . and a drive transistor”
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`The Petition and accompanying Fontecchio declaration do not establish
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`that Utsugi discloses these limitations of claim 4 or that it renders those limi-
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`tations obvious. This dependent claim makes explicit which active elements
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`are the “said active elements” that must be covered by the insulation film and
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`states that the active elements that must be covered includes a selection tran-
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`sistor. As discussed above, petitioners have failed to establish that a selection
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`transistor in Utsugi is covered or that it would have been obvious to make it
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`covered by the insulation film.
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`C. Claim 8: “The display apparatus according to claim 1, wherein
`a constant voltage is applied to said second electrode”
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`The Petition and accompanying Fontecchio declaration do not establish
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`that Utsugi discloses the limitations of claim 8 or that it renders those limita-
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`tions obvious. In order to anticipate or render obvious claim 8, Utsugi would
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`need to disclose or render obvious claim 1. For the reasons explained above,
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`Utsugi does not do so, and so the Petitioners have not established that claim 8
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`is rendered obvious.
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`Further, Petitioners do not establish that Utsugi teaches “a constant volt-
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`age is applied to said second electrode.” Petitioners argue that the voltage VDD
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`in Figure 3 of Utsugi is a constant voltage:
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`VDD of Utsugi does not disclose this limitation. Utsugi does not teach or
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`suggest that VDD is constant. (Ex. 2001, ¶ 66.) To support Petititioners’ argu-
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`ment, Dr. Fontecchio cites Amos, Principles of Transistor Circuits, 8th Ed.
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`(1994) that defines VDD as “supply voltage, d.c.” (Ex. 1006 at 387.) But noth-
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`ing in Utsugi suggests or indicates that its use of “VDD” is identical to how it
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`is defined in the Amos book. (Ex. 2001, ¶ 66.) Indeed, during his deposition,
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`Dr. Fontecchio indicated that the two “D”s in the abbreviation VDD most likely
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`stand for “drain,” not “d.c.” (Ex. 2005 at 57:9–58:15.)
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`Even assuming that Dr. Fontecchio is correct when he says that “VDD
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`refers to a direct current (DC) supply, as opposed to an alternating current
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`(AC) supply” (Ex. 1007 ¶ 129), that does not mean that VDD is necessarily
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`constant. (Ex. 2001, ¶ 61.) “Direct current” simply means that current only
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`flows in one direction through the circuit, as opposed to periodically alternat-
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`ing directions (AC). (Id.) It does not mean that the current is “constant.” (Id.)
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`Petitioner’s reliance on Utsugi’s reference to a 7 V “drive voltage” also
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`does not establish that the voltage applied to the second electrode is constant.
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`(Ex. 1003 at 8:32–40; Ex. 2001, ¶ 62.) As Dr. Fontecchio acknowledges, the
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`voltage across the EL element is the difference between the VDD value on line
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`5 and the voltage on scan electrode line 3N. (Ex. 1007 ¶ 129; Ex. 2001, ¶ 62.)
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`The voltages on the scan electrode lines change as particular lines are selected
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`and unselected. (Ex. 1003 at 8:11–20; Ex. 2001, ¶ 62.) If the 7 V drive voltage
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`is actually constant as Petitioners contend, that would require that the VDD
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`value of Utsugi to change over time. (Ex. 2001, ¶ 62.)
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`17
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`U.S. Patent No. 6,072,450
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`D. Limitation 15[f]: “an insulation film formed over said
`substrate so as to cover said drive transistors, said address
`lines and said data lines, said insulation film having contact
`holes formed in correspondence with said drive transistors”
`
`The Petition and accompanying Fontecchio declaration do not establish
`
`that Utsugi discloses limitation 15[f] or that it renders this limitation obvious.
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`Fontecchio Report ¶¶ 199–204, 230–231.
`
`Petitioners argue that the “scan electrode lines 3N+1” of Utsugi teach the
`
`“address lines” in this limitation. (Petition at 47.) As noted above, they con-
`
`tend that the “insulation film” is the upper layer of the two layers labelled
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`“SiO2” in Figure 5 of Utsugi:
`
`(Petition at 46.)
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`18
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`First, Figure 5 does not show “scan electrode lines 3N+1.” (Ex. 2001,
`
`¶ 65.) Nothing cited by petitioners or Dr. Fontecchio from Utsugi says that the
`
`“SiO2” layer is “formed over” or “cover[s]” these scan electrode lines, as re-
`
`quired by the claim under petitioners’ anticipation or obviousness theories.
`
`(Id.)
`
`A POSITA would recognize that the SiO2 layer described in Utsugi does
`
`not necessarily cover the scan electrode lines. (Ex. 2001, ¶ 66.) The SiO2 layer
`
`may not be deposited over cover the scan electrode lines in the first place, for
`
`example because a mask is used to prevent it from being deposited there. (Ex.
`
`1007 ¶¶ 84, 147; Ex. 2001, ¶ 66.) Petitioners acknowledge that even if the
`
`SiO2 layer is deposited over cover the scan electrode lines, that layer may be
`
`removed by etching, for example as part of the same etching step used to form
`
`the “second contact hole 56B.” (Ex. 1007 ¶¶ 84, 147; Ex. 2001, ¶ 66.) Nothing
`
`in Utsugi indicates whether the SiO2 layer covers cover the scan electrode
`
`lines or not. (Ex. 2001, ¶ 66)
`
`For limitation 1[c], Dr. Fontecchio argues that “it would be important for
`
`the insulation layer to cover the source and drain electrodes” of QS to prevent
`
`a short between those electrodes and the “electron injection electrode” 55.
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`19
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`U.S. Patent No. 6,072,450
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`(Ex. 1007 ¶ 84.) There is no similar concern of shorting for the signal elec-
`
`trode lines. (Ex. 2001, ¶ 67.) As shown below, the scan electrode lines and the
`
`electron injection electrode 55 do not overlap, and no short would occur even
`
`if there were no insulating layer above the scan electrode lines. (Id.)
`
`
`
`To the extent a POSITA would desire an insulator to be located above
`
`the scan electrode lines, a different insulating material could be deposited on
`
`those electrode electrodes. (Ex. 2001, ¶ 67) This could be a different insulat-
`
`ing layer (different from the SiO2 layer of Utsugi) patterned using a mask
`
`20
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`U.S. Patent No. 6,072,450
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`and/or etching so as to cover the scan electrode lines. (Id.) Alternatively, the
`
`upper surfaces of the scan electrode lines could be oxidized to form a layer of
`
`oxidation that provides the desired insulation properties. (Ex. 2003, Funda-
`
`mentals of Microfabrication and Nanotechnology (3rd ed. 2012), at 242–244;
`
`Ex. 2001, ¶ 67.).
`
`E.
`
`Limitation 15[j]: “a first driver circuit for selectively supplying
`said address signal to said address lines in sequence; and” /
`Limitation 15[k]: “a second driver circuit for supplying said
`image data to said data lines”
`
`The Petition and accompanying Fontecchio declaration do not establish
`
`that Utsugi discloses limitations 15[j] or 15[k] that it renders these limitations
`
`obvious. (Petition at 53.) Petitioners do not point to any disclosure of a driver
`
`circuit in Utsugi. (Ex. 2001, ¶ 69.) Though Utsugi refers to “sequentially se-
`
`lecting a corresponding one of row-addressed scan electrode lines,” Ex. 1003
`
`at 8:59–62, it does not explain how that selection is performed. (Ex. 2001,
`
`¶ 69.) There are multiple different ways to select scan electrode lines that do
`
`not involve a driver circuit. (Id.) As one example, selection of scan electrode
`
`lines could be manually or random. (Id.) It would not be unusual to manually
`
`apply signals to particular lines in no particular order, such as in a test device
`
`or an experimental device. (See Ex. 1003 at 8:32–40; Ex. 2001, ¶ 69.)
`
`21
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`U.S. Patent No. 6,072,450
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`Petitioners also argue that a POSITA would have used the driver circuitry
`
`from Kishita in Utsugi. However reliance on Kishita to provide claim ele-
`
`ments in this manner is improper, as this reference is not a part of the grounds
`
`that petitioners set forth in their Petition. (Petition at 5.) See 35 U.S.C. §
`
`312(a)(3) (petitioner must identify “with particularity . . . the grounds on
`
`which the challenge to each claim is based”); 37 C.F.R. § 42.104(b)(2) (re-
`
`quiring a statement that identifies “[t]he specific statutory grounds under 35
`
`U.S.C. 102 or 103 on which the challenge to the claim is based and the patents
`
`or printed publications relied upon for each ground.”) Furthermore, a POSITA
`
`would not have looked to Kishita for circuit designs to combine with Utsugi
`
`or modify Utsugi. (Ex. 2001, ¶ 70.) Utsugi teaches an active matrix display,
`
`with multiple transistors in a circuit for each pixel. (Ex. 1003 at 3:65–4:4;
`
`Figure 3; Ex. 2001, ¶ 70.) Utsugi specifically explains that such active matrix
`
`displays are superior to passive matrix displays, which suffer from lower
`
`brightness and shorter lifetimes. (Ex. 1003 at 2:8–39; Ex. 2001, ¶ 70.)
`
`In contrast to Utsugi’s active matrix design, Kishita is a passive matrix
`
`design, using the type of technology that Utsugi teaches is inferior. (Ex. 2001,
`
`¶ 71.) In the Kishita embodiments, each pixel contains only the EL element
`
`and does not contain any transistors or other active matrix circuit elements.
`
`22
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`U.S. Patent No. 6,072,450
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`(Id.) The scan side driver ICs in Kishita apply a voltage of plus or minus Vr
`
`to only a single scan electrode line at a time, and all of the other scan elec-
`
`trodes are “floating,” i.e. not electrically connected. (Ex. 1011 at 6:20–26,
`
`7:13–17; Figs 1, 5, 13; Ex. 2001, ¶ 71.) Thus, in Kishita devices, current can
`
`only flow through the EL elements in a single row at a time, with only a single
`
`row being illuminated at a time. (Id.) Moreover, the pixels in Kishita are either
`
`on or off and do not have an ability to display a range of brightness. (Id.)
`
`Kishita’s data electrodes either are grounded or supplied with a voltage of
`
`Vm, meaning that the corresponding EL elements either emit light or they do
`
`not. (Ex. 1011 at 6:27–50, 7:24–38; Ex. 2001, ¶ 71.).
`
`Kishita’s driving circuit is for a no-gray-scale passive matrix display
`
`which would not be suitable for combining with Utsugi, particularly in view
`
`of Utsugi’s stated goal of achieving “high-quality vision with a low voltage
`
`and a high luminance.” (Ex. 1003 at 5:20–23; Ex. 2001, ¶ 72.) Utsugi actually
`
`teaches away from the type of circuits contained in Kishita, and in any event
`
`a POSITA would understand that the circuits in Kishita would not be suitable
`
`for use in Utsugi’s active matrix design. (Ex. 2001, ¶ 72.)
`
`In addition, the scan side driver ICs in Kishita would prevent Utsugi’s
`
`active matrix pixel circuits from operating as designed. (Ex. 2001, ¶ 73.)
`
`23
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`Case No. IPR2020-00140
`U.S. Patent No. 6,072,450
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`Utsugi’s scan electrode lines 3N provide part of the path that the current
`
`through each EL element passes through. (Ex. 1003 at 8:17–31; Figure 3; Ex.
`
`2001, ¶ 73.) Kishita’s scan electrode lines are floating, in contrast, and modi-
`
`fying Utsugi with Kishita’s scan electrode lines would result in a device where
`
`pixels in a given row would not emit light, except perhaps during the period
`
`of time that the preceding row was selected. (Ex. 2001, ¶ 73.) Thus, Petition-
`
`ers have not established that a POSITA would combine Utsugi with Kishita,
`
`as such combination would be contrary to the teachings and design goals of
`
`Utsugi and yield an inferior device. (Id.)
`
`Finally, Petitioners note that the examiner found that certain claim limi-
`
`tations were disclosed in Kishita and that it would have been obvious to com-
`
`bine Kishita with the Tang and Stewart references. (Petition at 61; Ex. 1002,
`
`August 31, 1999 Non-Final Rejection at 6.) The same examiner also found
`
`that the claims of the ’450 patent including claims 15 and 16 were novel and
`
`not obvious. The examiner did not find that it would have been obvious to
`
`combine Kishita with Utsugi. For the reasons explained above, a POSITA
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`would not have been
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