1081848
`
`and the rate of trunsmission. Thu5, a different filter must be
`
`provided for each type or modulator implemented. Similar digital
`
`techniques may be used for both multifrequency {MF) and differential
`
`phase shift keyed (DPSK) modulation.
`
`A modulation technique similar to that illustrated in Fig. l
`
`is utilized in the time shared multiline FSK modulator disclosed in
`U.S. Patent 3,697,892 to Lawrence et al which provides a specific
`.
`type of FSK modulation for a set of lines: The multiline time-
`
`shared modulator, however, requires separate digital to analog con(cid:173)
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`10
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`verters for each line and a band pass filter for eact1 line capable
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`of eliminating undesired out of band frequency components generated
`
`in the modulation process. Because of these requ"irements, the
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`multiline modulator is incapable of handling a wide variety of
`
`modulation techniques which may be used for any of the output lines.
`
`This is so because of the specific requirements for the individual
`
`output line band pass filters.
`
`In the patented device, each out(cid:173)
`
`put line must, of necessity, be limited to one type of modulation.
`
`If it is desired to change the modulation characteristics for a
`
`given line, it becomes necessary to alter the characteristics of
`
`20
`
`the connected band pass filter. This requirement severely limits
`
`the usefulness of the multiltne modulator since the lines cannot
`
`b~ dynamically allocated to different modulation techniques.
`
`RA9-74-002
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`I l
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`Apple Exhibit 1010
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`Rembrandt Wireless
`Ex. 2012
`Apple Inc. v. Rembrandt Wireless Technologies, LP, IPR2020-00034
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`Description of the Preferred Embodiment
`
`Fig. l described in detail above illustrates the
`
`application of digital tone synthesis techniques in an
`
`FSK modulator. A digital value of phase e(t) is accumulated
`
`and updated each processing cycle determined by fs where
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`fs ls the sampling rate of the resulting modulated digital
`
`line signal. The amount by which the phase is incremented
`each sample time, MJ • determines the slope of e (t) and hence
`
`the instantaneous frequency of the sine wave generated,
`
`10
`
`For binary FSK, one of two values of phase increment 660 and
`
`691 are selected depending on the data which is to
`
`be transmitted. The frequency of the sine wave being
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`generated is directly proportional to the value of 68,
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`68 and
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`e(t) are both digital signals and the accumulation is
`
`performed with conventional arithmetic components, The
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`digital phase signal is scaled such that arithmetic overflow
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`of the accumulator or buffer 18 corresponds to the normal
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`modulo 360° property of the trignometric sine function.
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`The digital representation of phase et is translated to
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`20
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`a d:l.gital representation of sin e(t) by means of the read only
`
`memory 19, The resulting digital amplitude signal is converted
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`to analog by conventional digital to analog conversion techniques
`
`and subsequent analog filtering. The quantizing noise
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`resulting from the conversion from digital to analog is
`
`removed by the analog filtering along with other unwanted
`
`frequency components introduced by the modulating
`
`technique.
`
`In the FSK modulator illustrated in Fig, 1, as wel~.
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`RA9-74-002
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`Page 2018
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`1081648
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`as in other conventional FSK modulators implemented with
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`either analog or digital circuits, the instantaneous frequency
`
`of the transmitted signal is abruptly .switched between two
`
`values in the course of being modulated by the input data
`
`signal. The abrupt transition in frequency causes an increase
`
`in the bandwidth of the transmitted signal over that act~ally
`
`required to communicate the data by the FM modulation
`
`process. When FSK data transmission over telephone channels
`
`is required) it is necessary to reduce the excessive bandwidth
`
`generated in two significant application areas. One in high
`
`speed FSK, 1200 to 1800 bits per second transmission, bandwidth
`
`reduction is necessary to comply with out of band signal
`
`regulations imposed by various regulatory agencies and
`
`two in full duplex transmission using a single physical
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`channel, the received signal can, in many instances, be
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`significantly smaller in amplitude than the local transmitted
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`signal and the two frequency bands occupied by the two signals
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`18 may be relatively close. This requires that the bandwidth of
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`19
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`the transmitted signal be sharply reduced in order to prevent
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`interference with the received signal.
`
`Classically, FSK bandwidth reduction has been attained
`
`through band pass filtering of the transmitted signal. Some
`
`23 modulators have used premodulation filtering of the data signal;
`however, this approach has had limited application since it
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`requires a linear FM modulator. Either of the above approaches
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`for reducing unwanted signals introduced in the modulation process
`
`has a drawback iri a digital implementation of the modulator since
`
`the arithmetic requirements of a digital filter greatly increase
`..
`the functional complexity of the unit. For this reason, some
`
`digital modulators have used rather complex analog filters in
`
`their implementation.
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`RA9-71i-002
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`,.
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`Page 2019
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`·'
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`1.081.848
`
`A significant reduction in bandwidth can be achieved by
`
`eliminating the abrupt frequency transitions normally present
`
`in FSK modulation of binary data. This c~n be done by having
`
`the instantaneous frequency make a smooth or continuous
`
`transition in changing from one value to another. This
`
`is pointed out by Bettinger in "Digital Transmission for
`
`Mob:lle Rad:!.o" • Electrical Communications, Vol. 47 • No. 4,
`
`1972 at page 225, Such an approach has been implemented
`
`by the use of a premodulation filter, as noted earlier,
`
`or by the application of a control signal or voltage to
`
`a linear modulator,
`
`This approach while producing a
`
`desirable result is not flexible in many uses and limits
`
`the utility of the modulator to a single baud rate and set
`
`of frequencies.
`
`In a digital FSK modulator constructed according to the
`
`invention, a smooth transition in frequency ls accomplished
`
`by storing in memory digital values which represent a
`
`predetermlned trajectory for the Instantaneous frequency to
`
`follow and selecting these values based on the interbaud
`
`time or time since the last data transition. Such an approach
`
`is viable only in a digital FSK modul~tor where the phase
`
`and rate of phase change can be accurately specified.
`
`The trajectory followed as the frequency is slewed from
`
`one value to another is selected to minimize the bandwidth
`
`of the modulated signal. Both the shape and the number
`
`of intermed:l.ate po:ints in the trajectory• per bit t:Lme,
`
`are important parameters in this regard. Analysis and
`
`experiment has shown that a sinusoidal trajectory with
`
`eight points specified in time over the data bit give the
`
`best performance in terms of minimum transmit signal
`
`-7-
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`·-
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`·---------·-·--·-~------------.,.--..,----:-:----:-~----····---··-·,··-
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`DEF0000884
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`IPR2020-00036 Page 02020
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`Ex. 2012
`Apple Inc. v. Rembrandt Wireless Technologies, LP, IPR2020-00034
`Page 2020
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`

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`.. -,
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`1081548
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`l
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`d
`}
`;,ij
`:'j
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`bandwidth and minimum loss in receiver detectability.
`
`This does not, however, imply that an eight point sine
`
`wave trajectory 1s optimum in general. When this technique
`
`is implemented as shown in the modulator illustrated in
`
`Fig. 2j out of band signaling is reduced to the point where
`
`output filterin~ is no longer required and the sole filtering
`
`requirement is that necessitated by the digital modulation
`
`technique employed, that is, the removal of the quantizing
`
`noise. This may be accomplished by a simple RC filter,
`
`The modulator illustrated in Fig. 2 is capable of
`
`providing the FSK modulation for a single line of a number
`
`of different types or frequencies of FSK modulation.
`
`It
`
`requires binary input data and a line control word signal
`
`which in the illustrated embodiment is a single line
`
`designating either one type of FSK modulator or another.
`
`If the one type is designated, the line will be at a voltage
`
`level indicating the binary O and if the other type is indicated,
`
`..
`
`the line voltage will be at a voltage indicating a binary l.
`
`This, of course, could be expanded by providing additional
`
`lines for designating the line control word,
`
`In addition.
`
`the clock generator 30 operating at a frequency fs provides
`
`two clock phase signals Cl and C2, These are illustrated
`
`graphically in the figure and are 180° out of phase with each
`
`other. The data signals, the line control word and the two
`
`clock signals are applied to an address generator 31, The
`
`address generator 31 also receives signals from three conductors
`
`32A, 32B and 32C. These 3 conductors represent the three high
`
`order bits from a buffer register 32, the function of which will
`
`29.
`
`30
`
`be described later on. Based on the inputs described above,
`
`address generator 31 logically derives an address which is
`
`RA9-74-002
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`-8-
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`DEF0000885
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`IPR2020-00036 Page 02021
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`Ex. 2012
`Apple Inc. v. Rembrandt Wireless Technologies, LP, IPR2020-00034
`Page 2021
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`

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`1081846
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`29 .
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`30
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`applied to a read only memory 33 to access during one-half
`
`of the clock cycle rs, a value At and during the other half
`of the clock period rs, the value 4Bt.
`
`The contents of memory 33 are set out in the table of
`
`Fig. 3, This table is divided into two sections,
`
`It shows
`
`memory address 1 - 1+9 which are associated with line control
`
`word O for one type of FSK modulator and memory addresses j -
`
`;)+9 which are associated with line control word 1, another
`
`type of FSK modulator. Obviously, if additional types of FSK
`
`modulators are to be implemented, additional sections of memory
`
`would be necessary as well as additional lines for the line
`
`control word to distinguish the various FSK modulators being
`
`implemented, The conditions of the selection signals are
`
`indicated in the righthand columns of the table underneath
`
`the headings "Line Control Word, Data, t 1 cl and c2. During
`
`the first half of the clock cycle rs, that is, when cl and c2
`
`are 1, 0 respectively, the contents of addresses i and 1+1 or
`
`j and j+l depending on the line control word, will be selected
`
`if the three high order bits from buffer 32 are all zeroes
`
`or all ones and the data bit is O or 1 3 respectively, the
`
`contents from address i+l or j+l, namely, all zeroes will
`
`be provided at the output of th6 read only memory during
`
`that particular- fs clock cycle,
`
`If the contents of the three
`
`high order bits and the data bits are any other value, the
`
`contents of address i or j depending on the line control
`
`word will be selected.
`
`In this case, this value is an increment
`
`dividing the bit period Tinto eight different values to
`
`provide as shown in Fig, 2A 1 eight different values of
`
`68 over a single bit period for causing the frequency of
`
`the output of the modulator to change values smoothly or
`
`RA9-74-002
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`-9-
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`DEF0000886
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`IPR2020-00036 Page 02022
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`Rembrandt Wireless
`Ex. 2012
`Apple Inc. v. Rembrandt Wireless Technologies, LP, IPR2020-00034
`Page 2022
`
`

`

`' .,
`
`1081848
`
`1
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`2
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`sinusoidally as discussed above. For example, if the sampling
`
`frequency·fs of 18,000 cycles per s~cond is selected. this
`
`3 would yield 30 samples per bit for a 600 bit per second line.
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`30
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`Thus, a value of 120 for t/8 will provide eight substantially
`
`equal steps if the three high order bits of a 12 bit
`
`position register are examined. Therefore, the numerical
`
`value 120 will be stored in binary form in memory address i
`
`to implement a FSK modulation for a 600 b1.t per secon.d data
`
`rate. During the first half of each cycle fs, this value
`
`under the conditions described above, that is, data not
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`zero and the three high order bits from buffer 32 not all
`
`zero or data not one and the three high order bits from buffer
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`32 not all ones, will be added or subtracted to modify the
`
`contents of :register 36, How this is accomplished will become
`
`apparent as the description of the circuit shown in Fig, 2
`
`continues.
`
`During the second half cycle of clock fs, that is,.Cl(O)
`
`and C2(1), the values 681 through 688 residing in address
`
`locations 1+2 through 1+9 will be added in a manner similar
`
`to that illustrated in Fig. 1 and described below to thus
`
`generate the actual output frequencies from the modulator.
`
`The form of the values Ml through ll.e8 is illustrated
`
`in the graph shown in Fig. 2A. These values are selected
`
`to provide a smooth transition from the one frequency to
`
`the other.
`
`The contents, under the conditions described above, from
`
`read only memory_33 are applied to one input of an adder circuit
`
`34, The output of the adder circuit is selectively applied
`
`·
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`under control of clock 30 and a read write memory control circuit
`
`35 to one of two registers 36 and 37, During the first half
`
`-10- ·
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`DEF0000887
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`IPR2020-00036 Page 02023
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`Ex. 2012
`Apple Inc. v. Rembrandt Wireless Technologies, LP, IPR2020-00034
`Page 2023
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`1081.848
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`or the clock perlod rs, the output of adder circuit 34 is
`inserted in register 36 under control of read write memory
`control circuit 35 and during the second half of the clock
`
`fs, the output of adder circuit 34 is inserted in register 37.
`
`Likewise~ the contents of register 36 are added in adder 34
`
`during the first half of the clock cycle from clock 30 with
`
`the output of read only memory 33 and during the second half
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`cycle of clock 30, the contents of register 37 are added in
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`adder 34 with the output from read only memory 33, The addition
`
`and readbaak occur under control of read write memory control
`
`circuit 35 at different portions of the output from clock
`circuit 30. Thus, during the first portion of each of the
`
`clock cycles• the contents of the registers 36 and 37 a1'e
`
`added to the output of memory 33 by adder 34. After the addition
`
`takes place the sum of this addition is inserted into the
`
`registers 36 and 37 .. Read write memory contro·1 circuit 35 may
`
`take many.forms as is well known in the prior art for controlling
`
`reading into and out of memory devices and is not shown in
`
`greater detail here since it is well known in the prior art.
`
`The contents of register 36 under control of the clock 30
`
`Cl output are transferred to buffer 32 and the three high order
`
`bits of this register which may, for example, contain 12 bit
`
`positions are applied via conductors 32A, 32B and 32C to the
`
`address generator 31 and are used as described above for
`
`generating the address within read only memory 33 of the
`
`data which must 9e applied during each clock cycle to
`adder 34.
`
`An add~r control circuit 38 responds to the output of
`
`clock 30 and the data input to control the function of adder
`
`34; that is, whether an addition or subtraction takes place.
`
`During the first half of the clock period of clock 30, an
`31
`RA9-74-002
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`IPR2020-00036 Page 02024
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`Page 2024
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`1081848
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`addition or subtraction will take place depending upon the
`
`direction of change of the da.ta.
`
`If the data changes from
`
`al value to a O value, the contents of register 36 must be
`
`decremented and if the data changes from a D to a 1, the
`
`contents of register 36 must be incremented, Adder control
`
`38 includes an AND circuit 39 having one input connected to
`
`the data line and another input connected to the Cl output
`
`of the clock 30. The output of AND circuit 39 is connected
`
`via an OR circuit lJO to a control input of adder 34. When the
`
`data is 1 and during the first half of the clock period
`
`of clock 30, AND circuit 39 provides an output via
`
`OR circuit 40 which causes the adder to increment or add,
`When the data is zero, the output of AND gate 39 is down
`and this signal level causes adder circuit 34 to decrement.
`
`The specific implementation of this control is -well .known in
`
`the art and is not further described. here. During the second
`
`half of clock 30t the C2 output is connected via OR circuit 40
`to the control input of adder 34 and causes the adder to
`
`increment during this second half of the clock period. Buffer
`
`32 is loaded under ~ontrol of the Cl output of clock 30, thus,
`
`after the contents of register 36 have been modified as
`
`described above, the new value calculated is loaded into
`
`buffer 32 where it will be available for the next cycle of
`
`clock 30 during the next sampling period.
`The output of adder 34 is applied to a e to sine e
`
`conversion ch•cuit 41 which l]1ay be a read only memory loaded with
`precomputed values of sine e
`
`to perform the conversion.
`
`Such devices are well known in the prior art and readily
`
`available and are illustrated throughout this specific~tion
`in block form only. The output of e to sine a converter 41
`
`is applied to a register 42. Register 42 is strobed under
`
`RA9-74-002
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`-12-
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`IPR2020-00036 Page 02025
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`Ex. 2012
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`Page 2025
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`1081848
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`1
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`control of the C2 clock from clock generator circuit 30 and the
`
`contents applied at that time to a conventional digital to
`
`analog converter 43. The output of digital to analog
`
`converter 43 pulses a simple RC filter 44 which is designed
`
`solely to remove the quantizing noise introduced by modulation
`
`5
`6
`7 modulator may be changed from any group of frequencies to some
`
`process.
`
`It is obvious from the above description that the
`
`,.
`
`8
`other group of frequencies simply by changing the line control
`9 word and storing the appropriate values for that group in the
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`read only memory 33 since the filte1• 44 is the same for
`
`all values, it need not be changed or switchable.
`
`The basic processing time in Fig. 2 is divided into
`
`two parts, Cl and C2~ During Cl time, a running accumulation
`
`of bit time is calculated, During C2 time, a phase accumulation
`
`is calculated as is done in the conventional digital modulator
`
`illustrated in Fig. 1, with the exception that the values of
`
`ta are selected from memory on the basis of the bit time t
`
`from register 32.
`
`If a data transition occurs, during
`
`Cl time, numerical value which at the sampling rate will
`
`provide eight substantially equal detectably different outputs
`
`tram register 32 is selected from the At memory and
`
`added or subtracted depending on the data input. The
`
`baud time accumulation is made sharing the same adder 34 as
`
`is used for the phase accumulation. The digital value of
`
`baud time is prevented from underunning, that is, going
`
`below the all zero state when b,is subtracted or overrunning,
`
`that is, going above the all one state when A, is added,
`
`28 This is accomplished by the all zero condition stored in
`
`29 memory location i+l or j+l since adding or subtracting all
`
`30
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`zeroes to any .number does not change it, This memory
`
`RA9-74-002
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`-13-
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`DEF0000890
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`Rembrandt Wireless
`Ex. 2012
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`Page 2026
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`~ "
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`1081848
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`address is selected on the basis of the conditions shown
`
`in the table of Fig. 3. namely, data 1 and rall one or data O and
`
`..
`
`T all zero.
`
`In both of these conditions, an under or over
`
`run could occur. Therefore, the zero value is added to the
`
`value of r
`
`contained in register 36 during each processing
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`cycle, With this control, the baud time value changes from
`
`an all zero state to an all one state in eight equal steps
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`spanning the complete bit time when the data changes from
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`a Oto al, Thereafter, the baud time remains at the all
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`one state until the data changes back to zero. At which
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`time, !u is subtracted and -r is permitted to increment
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`to the all zero state.
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`At the end of Cl time, the highest three bits of,
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`are transferred to register 32 and used to address the 6e
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`memory during C2 time. The three highest bits of r
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`select
`
`one of the 8 values of 06
`to be accumulated as r
`traverses
`from one data state to the other, As indicated 1n Fig, 2A,
`
`the values of 68 addressed by
`
`r produce a smooth or
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`sinusoidal trajectory in the instantaneous frequency of the
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`transmitted signal. The phase accumulation, phase to sine
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`conversion, and digital to analog conversion are performed in
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`the same manner as for the conventional modulator illustrated
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`in Fig. 1.
`J:i'ig. 4 .is a schematic diagram of a differentiaJ. phase shift
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`keyed modulator compatible in implementation with the FSK modulator
`
`described above with respect to Fig, 2. The implementation
`in Fig. 4 provides a narrow band modulation in which the
`generated transmit signal spectr•a are :sufficiently narrow
`
`as not to require subsequent filtering for transmission
`
`over telephone lines or similar transmission media. The
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`1081848
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`only requirement being a simple RC filter to remove the
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`quantizing noise associated with the digital generation of
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`the signals and conversion to analog form.
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`The implementation of the DPSK modulator illustrated in
`
`5 Fig, 4 is structurally similar to the FSK modulator illustrated
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`6
`in Fig, 2, Since the two modulation techniques are compatible
`7 with each other, the major differences are in the nature
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`B
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`of the signals stored in the read only memory.
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`In view of
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`this similarity, the reference numerals used in Fig. 2 will
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`be used in part in connection with the description of this
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`figure,
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`In the DPSK modulator, the clock 30-1 operating at
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`a sampling frequency fs provides five outputs during each sampling
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`time. These outputs are illustrated graphically in the figure,
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`The first output Cl occurs during the first quarter of the
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`period of clock 30, The second output C2 occurs during the
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`second quarter, the third output C3 occurs during the third
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`quarter and the fourth and fifth outputs occur during the
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`fourth quarter. The fourth output C4 occupying the first
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`half of the fourth quarter and the fifth output, C5, occupying
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`the last half of the fourth quarter. The clock outputs Cl-C5
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`are applied to the address generator 31-1 along with the
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`three high order bits from the T buffer 32-1, The line control
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`word and one of the two simultaneously provided data bits for
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`a four phase DPSK modulation. The modulation contemplated in
`
`this modulator is a conventional four-phase DPSK modulation
`
`in which two bits of a binary digital signal are simultaneously
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`encoded. The first bit DO defining the sign cf the differential
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`phase change and the second bit Dl defining the magnitµde of the
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`change.
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`In this modulator, the magnitude bit is applied to
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`address generator 31 for selecting along with the other inputs
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`1081848
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`l
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`2
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`the appropriate address within the memory 33-1.
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`The output of address generator 31-1 selects an address
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`during each of the rive processing cycles of clock period 30-1
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`and reads the data stored in that address from the read only
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`5 memory 33-1. This data is applied to one input of an adder
`34-1. Two feedback register 36-1 and 37-1 similar to the
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`6
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`registers 36 and 37 of Fig. 2 are connected from the output of
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`the adder 34-1 to the other input of the adder 3~-1 and selectively
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`entered therein by the clock signals from clock generator
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`30-1 which are applied to a read write control circuit 35-1,
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`The contents of register 36-1 are applied to adder 34-1 during
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`clock time Cl and added to the contents supplied from read only
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`13 memory 33-1 then reinserted into register 36-1. At the end of
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`14
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`15
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`this clock period, the contents of register 36-1 are also
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`inserted into buffer 32-1 and are used as previously described
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`16
`for generating the address in address generator 31-1 along
`17 with the other inputs applied thereto. How these particular
`18
`inputs aocess specific data in the memo~y will be described
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`later in connection with the description of Fig. 5 which
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`includes a table of the memory and the selection signals.
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`During the second clock period, G2, the contents of register
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`37-1 are added to the data supplied from read only memory
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`33-1 and then reinserted in the register 37-1. This step
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`is repeated during the third clock period C3. During clock
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`period C3, the adder 34-1 will either add or subtract
`
`depending upon the sign of the DO data bit applied to
`
`the adder control circuit 38-1.
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`If the sign bit is negative,
`
`adder control circuit 38-1 will provide an appropriate signal
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`to adder 34-1 causing a subtraction to take place.
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`If the
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`sign.bit is positive, an addition will take place.
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`The
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`arrangement of adder control circuit 38-1 will be described below.
`During the fourth clock period c4 1 the contents
`of register 37-1 are added to the signal supplied by the read
`only memory 33-1, passed through e
`to sin e conversion
`read only memory 41-1 and inserted in a buffer 45 which is
`5
`under control of a read-write and clear control circuit 46.
`6
`7 Circuit 46 responds to clock pulses c4, C5 and Cl. During
`clbck pulse C4 the output from e
`
`1081848
`
`to sine conversion circuit
`
`41-1 is inserted into buffer Q5, The contents of registe~
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`37-1 are not altered at this time, That is, the summation during
`
`the fourth cloak period C4 does not alter the contents of buffer
`37-1. This is effected by read/write control circuit 35-1 in
`response to the c4 clock pulse. During the fifth clock pulse C5,
`
`the signals supplied from read only memory 33-1 are subtracted
`
`from the contents of register 37-1 under control of circuit 38-1.
`The output of adder 34-1 is passed through e to sin 6 conversion
`circuit 41-1 and applied to one input of an adder 47, The
`other input of adder 47 is connected to buffer 45 which during
`clock time C5 is read into the other input of adder 47 under
`
`control of read/write and clear circuit 46, The output cf
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`adder 117 is inserted in register Q2-l which at the trailing
`
`edge of clock time C5 is applied to a digital to analog
`
`converter 43-1 which has its output connected to filter 44-1.
`
`Adder control circuit 38-1 is provided with an OR gate 48
`
`having two inputs connected to the Cl and C2 outputs of clock
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`generator 30-1. The output of OR gate 48 1s connected to one
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`input of another OR gate 49 which has its output connected
`
`to the control input of adder 34-1, When this output is in a
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`1 state, that is when either clock pulse Cl or C2 are present,
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`adder 34-1 will add the contents applied at its two inputs.
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`Ex. 2012
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`Page 2030
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`'i
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`l
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`. ~
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`' ,I . .
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`,.\
`.:1
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`d
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`:•1
`:,!
`i
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`1081848
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`1 When the output of OR circuit 49 is o. the contents applied to the two
`inputs wfl 1 be subtracted. An AND gate 50 has one input connected to the
`
`DO data bit line safd a second input connected to the C3 clock output of
`clock generator 30-1. When the data. bit DO is 1, during clock period C3,
`
`AND gate 50 provides an output which is applied via OR circuit 49 to cause
`adder 34-1 to assume the adding mode, if the data bit is a indicating the
`negative sign. the adder will be controlled to perform a subtraction. A
`third input to OR circuit 49 is connected to the C4 output of clock generN
`ator ::m-1 and causes an addition to occur durfog the C4 clock tfme. Sum00
`10 marfzing adder 34-1 under control of adder control circuit 38-1 performs
`an addition during C1. CZ. and C4 times regardless of the circumstances.
`During C3 time it performs an addition, when the 00 bit is positive and a
`
`subtraction when the DO bit is negative. During C5 time, a subtraction 1s
`always performed,
`The modulator of Fig. 4 is speeif\ca11y configured to perform
`
`the function of a four-phase modulator such as the IBM* 3872 and the Bell*
`
`201 modems and is based on encoding two bits of data per baud by the
`differential p~ase between bauds as indicated 1n the table below.
`
`DO
`
`1
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`}
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`0
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`0
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`01
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`1
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`0
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`0
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`Phase Differential
`
`+45
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`+135
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`~45
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`.;.135
`
`As with the FSK modulation previously described. abrupt trans 00
`
`itions in phase between bauds in DPSK modulation produce modulated output
`
`sfgnals containing excessive out of band frequencies. A significant
`
`~
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`reduction in the bandwidth of the output signal can be achieved by
`
`*Trade Marks
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`Page 2031
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`1081848
`
`having the 60 increments between the bauds vary in a
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`smooth manner. Additional reductions in bandwidth can
`
`be obtained by combining amplitude modulation with the
`
`phase modulation. The above attributes are obtained
`
`through a widely used approach which employs a modulated
`
`signal consisting of using two phase modulated carriers,
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`each with envelope modul~tion, Abrupt phase changes are
`
`made when the envelope of the particular carrier is zero.
`
`The equivalent modulated signal has a smooth phase transition
`
`and can be written with the following form.
`
`L(t) ~ E(t) cos [wet+ em+ t(1)]
`
`where We~ carrier frequency
`em= arbitrary phase angle (not significant since the
`
`modulation is on a differential phase)
`
`E(t) = envelope or amplitude function
`
`and $(1) ~ Phasing function which describes the phase
`
`change between bauds,
`
`The direct but straightforward approach to implementing
`
`the above line signal requires a digital multiplier to
`
`accomplish the amplitude modulation. Such an approach would
`
`significantly increase the complexity of the transmitter.
`Multiplication is avoided by taking advantage or the ability
`to accurately control phase angle within the transmitter signal
`
`flow. The technique used is described below, Let
`
`L(t) = E(t) cos [e(t)]
`"' Wet + am + 4>(1)
`
`where e{t)
`
`and assume E(t) is scaled to a maximum level of 1.
`then E{t) cos e(t) = 1/2 {cos [e(t)+cos-1E(t)]+cos[a(t)-cos