`Apple Inc. v. Rembrandt Wireless
`IPR2020-00034
`Page 00001
`
`
`
`TAKLA AND HAQUE: SINGLE-CHIP 300 BAUD FSK MODEM
`
`847
`
`PROGRAMMABLE
`
`x7»
`
`1D e-—————__—_—_+
`
`
`
`
`cD
`
`asiRTs
`or
`aL
`*
`on
`ai
`
`
`
`CONNGL
`AND
`HANDSHAKE
`Loic
`
`
`
`CONTINUOUS
` LOWPASS BANDPASS
`
`
`
`PLTER
`FLIERFILTER
`
`+5
`°-5
`+» AGND
`
`ait
`
`3.58MHz
`
`OSCILLATOR
`
`,
`
`* DGND
`OSC;
`OSC,
`
`oor
`
`"
`
`: a CX
`et
`P| ier |
`
`
`
`
`
`CONTINUOUS
`7
`FSK/
`BASE BAND
`BANDPASS
`LOWPASS
`
`
`
`% | FILTER|CONVERTER en] FUTeR|ALTER RC
`
`RECOVERY|PULSE WIDTH LIMITER WPASS
`
`
`
`
`
`Fig. 1.
`
`300 baud FSK modem block diagram.
`
`II. SysreM ARCHITECTURE
`
`TABLE I
`MODULATOR FREQUENCYAS A FUNCTION OF SL (V21/BELL 103),
`A/O (ANSWER/ORIGINATE), TD (TRANSMIT DaTA), AND V25
`The block diagram of the FSK modem is shownin Fig.
`ANSWER TONE
`1. The input to the modulator is the TD (transmit data)
`signal, which is the digital data to be modulated. This input[—Mowe]—sost_—Ss«]—SSs]Sst===|“FREQUENCY(Hz)
`
`
`would typically be provided by the RS-232 interface, or a]193 onicinate ° 0 0 0 1070
`
`
`
`
`
`UART. The modulator generates a square wave whose
`-
`.
`|
`;
`!
`:
`a -
`
`103 ANSWER
`0
`1
`1
`r
`2225
`frequency1s shifted in response to the transmit data input.
`
`vot ORIGINATE
`The transmit filter outputs a frequency shift keying
`1
`8
`0
`0
`
`1
`9
`;
`9
`signal at the TC (transmit carrier) output. The frequency of
`
`
`the FSK signal corresponds to the fundamental frequency|vei answer - ;
`
`of the square waveat the inputofthefilter.
`[wanewerroe|xxxfd
`On the receive side, the receive filter, whose input is the
`receive carrier, rejects the adjacent channel energy and
`improves the signal-to-noise ratio of the incoming carrier.
`The outputof the receive filter is fed into the demodula-
`tor, where the digital data are retrieved from the filtered
`FSKsignal.
`The next major block is the energy detect circuit. It
`detects energy levels at which reception and demodulation
`of data are considered reliable.
`Thelast block is the timing control and handshakelogic,
`which, besides controlling all the other blocks, also imple-
`ments the RS232 interface protocol and controls the Bell
`103 and CCITT V.21 operations.
`
` ><
`
`those nine are used for 103 operation, two for high band,
`and two for low band. One of these two frequencies
`represents a mark and the other a space. Two bands ate
`used to enable simultaneous transmission and reception of
`data on the same channel, hence, the duplex operation. The
`other four frequencies are allocated for V.21 operation, and-
`the ninth frequency is used for V.25 answertone.
`The modulator, as shownin the left-hand side of Fig. 2,
`consists of a PLA (progranimable logic array) driving a
`programmable polynomial counter, followed by a divide by
`32. The polynomial counter generates 32 times the desired
`frequency. On each edge of this signal the PLA is updated,
`thus determining the frequency of next pulse. This ensures
`phase coherency of the generated signal. Since the output
`of the programmable polynomial counter is divided by 32,
`the maximum delay between TD and corresponding
`frequency shift at TC is 30 ps. The divide by 32 is also
`used as an auxiliary counter to control the divide of the
`programmable counter. This is used to maintain a devia-
`tion of all generated frequencies within 0.1 percent.
`
`IPR2020-00034 Page 00002
`
`TII. MODULATOR
`
`The modulator generates a square wave whose frequency
`is shifted in a phase-continuous fashion. The generated
`frequencyis a function of four signals: TD (transmit data),
`mode (answer/originate), SL (103/V.21 SELECT), and V.25
`(2100 Hz answer tone). As shown in Table I, the modulator
`is capable of generating one of nine frequencies: four of
`
`IPR2020-00034 Page 00002
`
`
`
`848
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. 6, DECEMBER 1984
`
`ENABLE
`
`FROM
`CONTROL4ANS./ORIG.
`LOGIC
`103/V21
`PROGRAMMABLE
`FREQUENCY
`
`GENERATOR
`3
`=§z<c
`
`10
`
`
`
`
`
`
`
`PROGRAMMABLE
`$
`3rd ORDER
`2nd ORDER
`
`
`
`
`
`
`
`4th ORDER
`PROGRAMMABLE
`DIVIDE BY
`ELLIPTIC
`CONTINUOUS
`N
`DIVIDER
`32
`
` LOW PASS
`ELLIPTIC
`SMOOTHING
`
`
`
`
`c
`FILTER
`BAND PASS
`FILTER
`
`Fig. 2. Block diagram of the modulator.
`
`"
`
`3.58
`
`1000
`
`2000
`
`3000
`
`4000
`
`5000
`
`FREQUENCY(Hz)
`(a)
`
`1000
`
`2000
`
`-
`3000
`
`4000
`
`5000
`
`FREQUENCY(Hz)
`(b)
`Fig. 3. Measured transfer function of the transmitfilter.
`
`IPR2020-00034 Page 00003
`
`20
`
`- 30
`
`- 40
`
`~ 50
`
`-9
`
`-70
`
`- 80
`
`- 90
`
`- 108
`
`0
`
`~ 20
`
`- 30
`
`- 40
`
`- 80
`
`=co
`sc
`Zz
`z=
`s
`
`<S
`
`Eoc
`<s
`
`= -60
`z<
`So
`
`-1
`
`- 80
`
`~ 90
`
`~ 100
`
`0
`
`IPR2020-00034 Page 00003
`
`
`
`TAKLA AND HAQUE: SINGLE-CHIP 300 BAUD FSK MODEM
`
`849
`
`103/V21
`ANS./ORIG.
`ANALOG LOOPBACK
`
`DECODER
`
`
`
` DETECT
`
`
`2nd ORDER
`8th ORDER
`
`2nd ORDER
`CONTINUOUS
`2nd ORDER
`BAND PASS
`
`CONTINUOUS
`
`
`
`ANTIALIAS
`SMOOTHING
`PROGRAMMABLE
`
`
`LOW PASS
`
`
`LOW PASS
`FILTER
`FILTER
`FILTER
`
`
`FILTER
`
`
`
`TO
`DEMGOULATOR
`NERGY
`DETECT
`
`&E
`
`FREQUENCY
`
`
`GENERATOR
`59.7kH2/55.9kHz
` 238.6kHz/
`
`
`223,7kHz
`
`Fig. 4. Receive filter block diagram.
`
`IV.
`
`TRANSMIT FILTER
`
`The function of the transmit filter is to produce an FSK
`signal
`from the phase-continuous
`frequency-shifted
`square-waveinput.
`The structure of the ninth-order filter is shown in the
`right-hand side of Fig. 2, while its measured frequency
`response is shown in Fig. 3. The filter consists of three
`major sections. Thefirst is a third-order switched capacitor
`elliptic low-pass filter, sampled at 111.9-223.7 kHz, de-
`pending on the modeof operation. The cutoff frequency of
`this
`filter
`is programmed by changing the sampling
`frequency.
`The second section is a fourth-order elliptic bandpass
`filter which is programmedto operate in either the high or
`low band by changing both the capacitor ratios and the
`sampling frequency. The third section of the filter is a
`second-order Sallen and Key continuous smoothing filter.
`It attenuates the sampling frequency of
`the preceding
`section by more than 31 dB and produces a smooth FSK
`signal at its output.
`,
`The prime objective of the transmitfilter is to pass the
`square wave fundamental component, while attenuating its
`harmonics. These harmonics could be located in the receive
`band. Unless attenuated by the transmit filter, they would
`be coupled back through the hybrid, unattenuated by the
`receivefilter, thus causing degradation of bit errorrate.
`The transmit filter was designed to have a zero at the
`third harmonic of the square wave, to alleviate the above
`problem.
`The second objective of the transmit filter 1s to attenuate
`the out-of-band energy. This is necessary since the modula-
`tion process produces energy over a broad spectrum and
`not just at the mark/space frequencies. The fundamental
`component is attenuated by 24 dB to produce a signal at
`—9 dBm at the TC (transmit carrier) output.
`
`implemented using biquadratic
`filters were
`The
`switched-capacitor second-order sections allowing imple-
`mentation of both poles and zeros [2]. The filters were
`designed using bilinear transformation [3] and the results
`were optimized for acceptable group delay and frequency
`attenuation performance.
`
`V. RECEIVE FILTER
`
`The block diagram of the receive filter is shown in Fig. 4.
`The receive carrier is first fed into a second-order Sallen
`and Key continuous low-passfilter, which is followed by a
`second-order antialiasing filter clocked at 4 times the
`frequency of the main filter to follow. This antialiasing
`filter attenuates the incoming signal by 41 dB at
`the
`sampling frequency of the following section. This mini-
`mizes the aliasing effects and allows the main filter to be
`clocked at a lower frequency with resulting smaller capaci-
`tor ratios [2]. The antialiasing filter has programmable gain
`that can vary between 5 and 17 dB.The gain ofthe filter is
`changed under control of the energy detect circuit thus
`implementing the automatic gain control function.
`The next section is an eighth-order bandpass program-
`mable filter. It can be programmed to operate in one of
`four configurations depending on the band (high or low)
`and the specifications (Bell 103 or CCITT V21). Changing
`the capacitor ratios and sampling frequencies is used to
`reconfigure this section for the appropriate transfer func-
`tion. Both the transmit and receive filter can also be
`configured to work in the same band of frequency allowing
`true analog loopback, which facilitates testing.
`The last section is a second-order Sallen and Key con-
`tinuous low-passfilter. It attenuates the sampling frequency
`of the preceeding section by 20 dB and produces a smooth,
`filtered FSK output, which is fed to the demodulator. This
`action reduces the jitter of the demodulated signal.
`
`IPR2020-00034 Page 00004
`
`IPR2020-00034 Page 00004
`
`
`
`IBEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. 6, DECEMBER 1984
`
`{ \
`
`i
`
`30 20
`jWas
`
`20
`
`- 40
`
`so
`
`60
`
`Q
`
`1000
`
`2000
`
`3000
`
`4000
`
`5000
`
`850
`
`GAININdBm
`
`GAININdBm
`
`FREQUENCY(Hz)
`
`30
`
`20
`
`10
`
`0
`
`- 10
`
`- 20
`
`- 30
`
`- 40
`
`— 50
`
`- 60
`
`-70
`
`0
`
`1000
`
`2000
`
`3000
`
`4000
`
`5000
`
`FREQUENCY(Hz)
`
`Fig. 5. Measured transfer function of the receive filter. (a) Bell 103.
`(b) CCITT V21 specifications.
`
`The measured frequency response of the receivefilter is
`shownin Fig. 5. The receive filter rejects out-of-band noise
`so that
`the filtered signal can be demodulated with a
`resulting low bit errorrate.
`The filter was designed to reject the adjacent channel
`energy, which is attenuated by 60 dB. This is essential since
`that channel
`is used for carrier transmission, which is
`coupled back through the hybrid and into the receive
`section. Unless attenuated by the receivefilter, this compo-
`nent would corrupt the demodulated data and result in
`excessive bit-error rate. The filter was also designed to
`minimize group delay distortion between the mark and
`space frequencies. The bandwidth of the filter is 500 Hz
`
`and is centered aroundthe center frequency of the received
`carrier.
`The dynamic range of the receive signal is 50 dB due to
`the automatic gain control circuit employed.
`
`VI. DEMODULATOR
`
`The demodulator is the most critical part of the modem.
`Its block diagram, the corresponding waveforms, and the
`measured frequency response of the baseband recovery
`filter are shownin Fig.6.
`The input
`to the demodulator is the filtered receive
`carrier (waveform A). The filtered signal
`is amplitude
`
`IPR2020-00034 Page 00005
`
`IPR2020-00034 Page 00005
`
`
`
`- TAKLA AND HAQUE: SINGLE-CHIP 300 BAUD FSK MODEM
`
`851
`
`RD
`
`SLICER
`
`BASE
`PROGRAMMABLE
`
`
`
`BAND
`FSK/
`
`
`
`FILTERED
`RECOVERY
`PULSE WIDTH
`
`
`
`FILTER
`RECEIVE
`CONVERTER
`
`CARRIER
`
`
`
`(a)
`
`SIGN
`TO ENERGY
`DETECT
`
`DEMODULATORFILTER
`
`1 n3
`
`oa
`
`1 ~o
`
`~ $0
`
`- 60
`
`-70
`
`0
`
`500
`
`1000
`
`1500
`
`.
`
`-—4
`2000
`
`FREQUENCY(Hz)
`
`Ee
`
`2 z
`
`=z
`
`oa
`
`|j~«—
`| —>|
`ACh)
`A(fz)
`
`DEMODULATOR
`
` .
`»
`
`~
`
`(o)
`
`(b)
`
`Fig. 6. Demodulator. (a) Block diagram. (b) Corresponding waveforms
`and measuredtransfer function of baseband recovery filter.
`
`limited, generating a digital waveform B, which is fed into
`a programmable FSK/pulsewidth converter. The function
`of the converteris to generate 2 sequential pulses at 4 times
`the center frequency of the received signal. On each edge of
`the amplitude-limited signal the converter is reset.
`In this fashion the time interval, as shown in waveform
`C, is a function of the received signal frequency and can be
`used as a measure of it. To recover the baseband data, the
`converted signal is fed into a low-passfilter that rejects the
`x4 carrier frequency component while passing the base-
`band signal. The baseband recovery filter consists of a
`Bessel low-pass filter driven by a numerical generator. The
`output of this filter is followed by a smoothing filter. The
`output of the filter is the eye pattern and is available at
`the EP pin of the device. It is important to keep the high
`and low levels of the digital wave C (Fig. 6) of equal
`magnitude and opposite polarity since any asymmetry gives
`rise to voltage offset. The input to the baseband recovery
`filter uses a unique sampling scheme where switched-capa-
`citor techniques are used to make both the low and high
`levels referenced to one power supply with one of the
`polarities being inverted.
`
`The output of the baseband recovery filter is then fed
`into a slicer that recovers the digital signal. These are the
`received digital data which are made available at the RD
`pin under RS232C control. The block diagram of the
`programmable FSK/pulsewidth converter
`is shown in
`Fig. 7.
`
`VII.
`
`ENERGY DETECT CIRCUIT
`
`The energy detect circuit is used to detect three different
`energy levels. Detection of one of these levels is used to
`control the carrier detect output. Detection of this level,
`together with the other two,
`is used for automatic gain
`control of the receivefilter.
`The energy detect circuit, as shown in Fig. 8, consists of
`three major sections: the rectifier, the integrator, and the
`comparator and latches. The rectifier stage samples the
`filtered receive carrier and either passes it
`through or
`inverts it, depending on the signal’s polarity. The integrator
`integrates the rectified signal for 1.67 ms after which it is
`reset. At the end of each integration period, the output of
`
`IPR2020-00034 Page 00006
`
`IPR2020-00034 Page 00006
`
`
`
`852
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. 6, DECEMBER 1984 -
`
`
`EDGE DETECTOR
`SIGN
`
`(OUTPUT OF
`RECEIVE FILTER)
`
`
`
`
`
`COMBINATIONALLOGIC
`
`PROGRAMMABLE FREQUENCY
`
`DIVIDER
`
`3.58 MHZ
`
`Fig. 7. Block diagram of programmable FSK/pulsewidth converter.
`
`ENERGY DETECT CIRCUIT AND AGC
`
`OUT
`(TO BASE BAND
`RECOVERYFILTER)
`
`CONTROL
`
`V
`
`FILTERED
`RECEIWE
`CARRIER
`
`RECTIFIER
`}--——_ WITH GAIN
`CONTROL
`
`LOGIC
`poe 2cu
`
`
`— 48 ~ 43
`
`INPUT ENERGY
`IN dBm
`
`Vrer
`
`}———-——— COMPARATOR ————->|
`|~——-—- INTEGRATOR —~——-+}
`
`Fig. 8. Block diagram of energy detectcircuit.
`
`
`
`300 kHz
`
`the integrator is compared with an internally generated
`reference voltage and the result is saved in one of the two
`latches. Time division multiplexing is used to detect differ-
`ent energy levels. During the first time frame the energy
`detect circuit is configured to detect energy levels corre-
`sponding to — 48 or — 43 dBm at the inputofreceive filter,
`depending on the state of the carrier detect output. The
`result of the comparison is saved in the lower latch and is
`used by the timing control section to generate the carrier
`detect output. It is worth noting that one energy level at
`the output of the receive filter corresponds to either — 48
`or —43 dBm at the input of the filter, depending on the
`filter’s gain at that time.
`During the second time frame, the gain of the rectifier
`andintegrator is reduced to detect higher energy levels and
`the result
`is stored in the upper latch in Fig. 8. The
`
`contents of these latches are used to control capacitor
`ratios in the receive antialiasing filter, which enables imple-
`mentation of an AGC function as well as hysteresis control
`of the energy detect circuit (5 dB in this case).
`Offset voltage and correlated noise is reduced in the
`energy detect circuit by adding an additional signal in the
`integrator. This signal is the offset and correlated noise at
`the rectifier output (with no signal
`input) with proper
`weighting [4].
`
`VIII. TIMING CONTROL AND HANDSHAKE LOGIC
`
`This section configures the chip into the appropriate
`operating mode and implements the handshake protocol.
`A protocol, in this context, is an agreed upon sequence
`of events used to establish a data call. A typical example is
`
`IPR2020-00034 Page 00007
`
`IPR2020-00034 Page 00007
`
`
`
`TAKLA AND HAQUE: SINGLE-CHIP 300 BAUD FSK MODEM
`
`853
`
`™m ¢
`
`COMPUTER
`
`
`
`TERMINAL | MODEM
`
`RD
`
`RC
`
`ORIGINATING DEVICE
`
`ANSWERING DEVICE
`
`DTR(ORIG.)
`
`RTS (ORIG.)
`
`OH (ORIG.)
`
`CD (ORIG.)
`
`TC (ORIG.)
`
`CTS (ORIG.)
`
`DTR (ANS.)
`
`Ri (ANS.}
`
`OH (ANS.)
`“TC (ANS.)
`CD (ANS.)
`
`CTS (ANS.)
`
`ik
`
`120ms
`
`<— 640ms—-»
`
`j- 240ms—>|
`
`1270 Hz
`
`Jo 2.18 ——>]
`
`2225 Hz
`
`120ms
`
`Fig..9. Bell 103 protocol as implemented bychip.
`
`230ms
`
`whenthe originating device is a terminal while the answer-
`ing device is connected to a computer. This is shown in
`Fig. 9.
`-
`The originating device starts by setting the DTR (data
`terminal ready) high to enable its modem.It then proceeds
`by pulsing RTS (ready to send). This in effect pulse dials
`the number out. Once the connection is made and ringing
`is detected at the remote device, RIB (ring indicator bar) is
`pulsed. This takes the remote device off hook and puts it in
`the answer mode. The answering device responds by wait-
`ing for 2.1 s, the billing delay, and then starts sending the
`mark frequency, which is 2225 Hz, for the Bell 103 specifi-
`cations.
`Upon receiving the answer tone, the originating device
`indicates carrier detection by turning the. carrier detect
`output on, waits for 240 ms, and then starts sending 1270
`Hz mark frequency for 640 ms. At the end of the this
`period, clear to send turns on indicating to the terminal
`that it is clear to send data.
`The answering device detects the carrier in 120 ms and
`indicates that to the data terminal equipment by turning
`the carrier detect output on. It also indicates to the DTE
`that it can start sending data by turning CTS on.
`On the right-hand side of Fig. 9,
`the loss of carrier
`termination is demonstrated. If one of the two modems
`does not receive the carrier at a detectable level for more
`than 10 ms, it will respond by turning the carrier detect
`and clear to send outputs off. If this condition lasts for
`more than 230 ms, the modem will respond by disabling
`the transmit section and going on hook, thus terminating
`thecall.
`
`
`
`es
`BE
`modem.
`Fig. 10. Microphotograph of single-chip 300 baud
`
`The chip also incorporates a 14 s abort timer. This is
`necessary for automatic operation. When a call is auto-
`matically originated, and the remote device is busy, then
`the originating device waits for 14 s and hangs up. On the
`other hand, if a modemis called by mistake it will hang up
`in 14 s, unless the appropriate carrier is received.
`The protocol described above implements the Bell 103
`specification. The chip. also implements the CCITT V.21
`specification which is conceptually similar, although differ- .
`ent in implementation.
`
`IPR2020-00034 Page 00008
`
`IPR2020-00034 Page 00008
`
`
`
`854
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. 6, DECEMBER 1984
`
`IX.
`
`EXPERIMENTAL RESULTS
`
`REFERENCES
`
`[1 A. Takla and Y. Haque, “A 300 baud frequency shift keying modem,”
`in ISSCC Dig. Tech. Papers, 1984, pp. 188-189.
`{2] R. Gregorian, K. W. Martin, and G. C. Temes, “Switched-capacitor
`circuit design,” Proc. [EEE, vol. 71, Aug. 1983.
`[3] K. Martin and A. S. Sedra, “Stray insensitive switched-capacitor
`filters based on bilinear z transform,” Electron Lett., vol. 19, pp. 365,
`June 1979.
`Y. A. Haque, “Design technique for dynamic range improvement on
`CMOS circuitry,” in Proc. Custom Integrated Circuits Conf., May
`1983, pp. 376.
`
`[4]
`
`Ashraf K. Takla (M’81) was born in Cairo, Egypt,
`in 1956. He received the B.S.E.E. and M.S.E.E.
`degrees from San Diego State University, San
`Diego, CA, in 1979 and 1981, respectively.
`In 1980 he joined the Micro Component
`Organization, Burroughs Corporation, San Di-
`ego, CA, where he designed computer communi-
`cation integrated circuits. Since 1982, he has been
`with the Communication Group, American Mi-
`crosystems, Inc., Santa Clara, CA, where he has
`been involved in the definition and design of
`data communications IC’s.
`
`The photomicrograph of the chip is shown in Fig. 10. It
`measures 216 X 260 mils”. It uses a +5 V power supply.
`Typical power dissipation is 110 mW. The modulator
`frequency deviation is +0.095 percent. The transmit car-
`rier harmonic attenuation is 60 dB. The receive carrier
`range is 0 to. —50 dBm. Typical bit jitter measured at 300
`baud and at an input of — 30 dBm is 100 ps. Bit-error rate
`at 5 dB SNR is 3X10~°. The bit bias is measured at an
`input of — 30 dBm is 3 percent.
`
`X. CONCLUSION
`
`A single-chip frequency shift keying modem has been
`successfully integrated in a 5 4m CMOStechnology. This
`modem represents a higher level of system integration
`where modulation, demodulation, filtering, energy detec-
`tion, as well as RS-232 control functions, are performed on
`the same chip for both.the Bell 103 and V.21 standards.
`The devices meet all required specifications.
`
`ACKNOWLEDGMENT
`
`The authors would like to acknowledge the help of S. C.
`Fan and B. Ghaderi for designing the eighth-order receive
`filter. Also, very helpful suggestions from R. Gregorian
`and. V. Godbole are gratefully acknowledged.
`
`
`
`
`Yusuf A. Haque received the Ph.D degree in
`electronics from Carleton University, Ottawa,
`Ont., Canada, in 1977, and the M.B.A. degree
`from the University of Santa Clara, Santa Clara,
`CA,in 1982.
`While in Ottawa (1973-1977), he designed
`several integrated circuits at Bell Northern Re-
`search. He joined American Microsystems, Inc.,
`Santa Clara, CA,
`in 1978 and has since been
`involved in the design and developmentof tele-
`communicationscircuits. He is currently Manager
`for Communications Products. He has received several patents in the area
`of MOSintegrated circuits.
`
`IPR2020-00034 Page 00009
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`IPR2020-00034 Page 00009
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