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`
`U8007940809BZ
`
`(12; United States Patent
`US 7,940,809 BZ
`Lee
`(45) Date of Patent:
`May 10, 2011
`
`(10) Patent No.2
`
`(54} DIGITAL VIDEO INTERFACE WITII
`Ell—DIRECTIONAL HALF-DUPLEX CLOCK
`CHANNEL USED AS AUXILIARY DATA
`CHANNEL
`
`(75)
`
`Inventor: Bong-Juan Lee. Seoul (KR)
`
`[73} Assignee: Synerehip Co. Ltd.. l-lsinchu (TW)
`
`[ * } Notice:
`
`Subject to any disclaimer. the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154fb) by 405 days.
`
`..................... 3755295
`”52002 Kilnetal.
`20025018|608 A1 "
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`200850112371 Al‘
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`O'I‘I lliR I’UBLlCAl‘IONS
`
`"Digital Visual Inlerlitce. [)\-'1: Revision 1.0."Apr. 2. [999. Digital
`Display Working Group. pp. l-Tti.
`“liigh~1)efiuit ion Multimedia Interface: Specification Version 1.23.“
`Dec. I4. 2005. pp. 1-193. IIDMI Licensing. LLC.
`“High—Definition Multimedia interface: Specification Version 1.33."
`Nov. 10. 2006. pp.
`l—ETG. HDN’II Licensing. I_[.C.
`“[Irti ficd Display interface (CD1 ) Specification: Revision Lila Final.”
`Jul. [2. 2006. pp. 1-185.
`
`(2}) Appl. No; nosinm
`
`[22}
`
`Filed:
`
`Jun. 8, 200'?
`
`(65}
`
`(60}
`
`(so
`
`(52}
`(53;
`
`[56)
`
`Prior Publication Data
`
`US 2m8t024'i'341 A]
`
`061. 9. 2008
`
`Related U.S. Application Data
`
`Provisional application No. 60t910.?59. filed on Apr.
`9. 200?.
`
`int. (.‘1.
`
`H04J3/12
`US. Cl.
`Field of Classification Search
`
`{2006.01}
`
`3701525
`None
`
`See application file for complete search history.
`
`References Cited
`
`US. PATENT DOCUMENTS
`
`6.507.592 Bl '
`1.295.513 BI '
`200l’fl024430 A1"
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`’°‘ cited by examiner
`
`Primatjr Examiner — Chi H Pham
`Assistant Examiner — Fan Ng
`(74) dimmer. Agent. or Firm liiimbeth Kim
`
`(5?)
`
`ABSTRACT
`
`A digital video interface system and method for communi-
`cating digital video data from a source device to a sink device
`is provided. where the clock channel is used to transmit data
`as well as clock signals in a bi-direclional. half-duplex inan-
`ner using time division multiplexing. The digital video inter-
`face system comprises one or more data channels configured
`to transmit digital video data from the source device to the
`sink device in time divisional multiplexing including a pin-
`rality of first time slots and second time slots. and a clock
`channel configured to transmit a clock signal from the source
`device to the sink device in the first time slots and configured
`to transmit additional data from the source device to the sink
`device or from the sink device to the source device in the
`second time slots.
`
`32 Claims. 4 Drawing Sheets
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`US 7,940,809 32
`
`1
`DIGITAL VIDEO INTERFACE WITH
`Bil-DIRECTIONAL HALF-DUPLEX CLOCK
`CHANNEL USED AS AUXILIARY DATA
`CHANNEL
`
`CROSS-RIiFlziRliNCli TO RI-EliA’l‘lil)
`.r'tPPIJCAI’ION
`
`This application claims priority under 35 U.S.C. §119(e)
`front ctr-pending US. Provisional Patent Application No.
`60t910.759. entitled “Digital Video Interface witlt Bi-Diree-
`tional Half«Duplex Auxiliary Data Channel.“ filed on Apr. 9.
`2007. which is incorporated by reference herein in its entirety.
`
`It]
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a digital video interface
`and. tnore specifically. to a digital video interface that uses the
`clock channel as an auxiliary data channel.
`2. Description ofthe Related Art
`Current digital video interfaces such as DVI (Digital Video
`Interface). l-IDMI (High-Definition Multimedia interface).
`and DD} (Unified Display Interface) typically use 3 or 6 RGB
`(Red. Green, and Blue video data) channels for the ntain data
`stream and l clock channel for a frequency reference. in order
`to transmit digital video data between a video sotutce device
`(eg. a digital video disk player) and a video sink device (e.g..
`a higl‘i-dellnition television]. liach channel (R. (i. B. and
`clock) is typically comprised of a differential pair of two
`matched wires. The clock channel is used to transmit the
`
`frequency reference for the digital video data from the video
`source device to the video sink device. with the clock fre-
`
`20
`
`I.) 1):
`
`3t]
`
`quency being set to the video data rate of the digital video
`data.
`
`35
`
`In conventional digital video interfaces such as I-lDM]. the
`R. G. B data channels transmit video data and control data in
`an alternating manner with time-division multiplexing. That
`is. video data is transmitted in certain tinte slots of the R. G.
`B data channels while control data is transmitted in other time
`
`slots of the R. G, B data channels in an alternating trimmer.
`The clock signal is transmitted via the clock channel continu—
`ously regardless o fwhether the R. G. 13 data charuiels are used
`to transmit digital video data or control data.
`tlte fre-
`However. once the RGB links become settled.
`quettcy information is tto longer needed by the video sittk
`side. because the receiver clock and data recovery circuit in
`the digital video interfaces can keep the link synchronized
`using the serial RG8 data. Thus. conventional digital video
`interfaces use the clock channel inefficiently, transmitting the
`clock signal continuously even when the frequency informa-
`tion may not be needed at the video sink. This results in
`inefiicicnt use of the clock channel.
`
`5th
`
`Thus. there is a need for a technique for using the clock
`channel ofa digital video interface more efiiciently.
`
`55
`
`SUMMARY OF T'I-lli INVENTION
`
`Embodiments of the present invention include a digital
`video interface system attd method for communicating digital
`video data front a source device to a sink device. where the
`
`Gill
`
`clock channel is used as an auxiliary data channel to transtnit
`data as well as clock signals in a Iii-directional. half«duplex
`manner using time division multiplexing. In one embodi~
`ntent. the digital video interface system comprises one or
`more data channels configured to transmit digital video data
`from the source device to the sink device. where the data
`
`2
`
`channels are configured to operate in time divisional multi-
`plexing with a plurality of first time slots and second time
`slots. and a clock channel configured to transmit a clock
`signal from the source device to the sink device in the lirst
`titne slots and configured to transmit additional data from the
`source device to the sink device in the second time slots. The
`clock channel may also be configured to transmit the addi—
`tional data in the opposite direction from the sink device to the
`source device in tlte second time slots.
`
`The digital video data are transmitted front the source
`device to the sink device via the data channels in the second
`time slots. while control data corresponding to the digital
`video data are transmitted from the source device to the sink
`device via the data chatmels in the first time slots. in addition.
`additional control data may be transmitted from the source
`device to the sink device via the clock channel in the first time
`slots.
`
`is configured to
`ltt one embodiment. the clock channel
`operate in one of a plurality of operation modes. In a first
`mode. the clock signal is transmitted front the source device
`to the sink device via the clock channel in the first time slots.
`in a second mode. the additional data are transmitted from the
`source device to the sink device via the clock channel in the
`second time slots. In a third mode. the additional data are
`transmitted from the sink device to the source device via the
`clock channel in the second time slots.
`Accordingly. the digital video interface system further
`comprises a source side transmitter configured to transmit the
`clock signal in the first mode or the additional data in the
`second mode to the sink device via the clock channel. a sink
`side receiver configured to receive the clock signal in the first
`mode or the additional data in the second mode from the
`source device via the clock channel. a sink side transmitter
`configured to transmit the additional data in the third mode to
`the source device via the clock channel. and a source side
`receiver configured to receive the additional data in the third
`mode from the sink device via the clock channel. The sink
`side transmitter is disabled in the first ntode attd the second
`mode, and the source side transmitter is disabled in the third
`mode.
`In one embodiment. the additional data transmitted via the
`clock channel from the source device to the sink device
`includes a control packet indicating whether subsequent pay-
`load data to be transmitted via the clock drama] is in a first
`direction front the source device to the sink device or in a
`second direction from the sink device to the source device.
`
`The digital video interface system ofthe present invention
`enables a bi-directional. half-duplex. auxiliary data channel
`using the clock cltannel of the digital video interface. yet
`neither changing the channel composition nor sacrificing the
`performance of the data channels of the digital video inter-
`face. Thus, the clock channel is more efficiently used, and
`more data can be communicated between the source device
`attd the sink device without making any significant changes to
`the cltannel composition of the digital video ittterfaces.
`The features and advantages described in the specification
`are not all inclusive and. in particular. many additional fea-
`tures and advantages will be apparent to one of ordinary skill
`in the art in view of the drawings. specification. and claims.
`Moreover. it should be noted that the language used in the
`specification has been principally selected for readability and
`instructional purposes. attd may ttot have been selected to
`delineate or circumscribe the inventive subject matter.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The teachings of the embodiments of the present invention
`can be readily uttderstood by considering the following
`detailed description in conjunction with the accompanying
`drawings.
`
`

`

`US 7,940,809 32
`
`4
`
`3
`FIG. 1 is a conceptual block diagram illustrating the bi-
`directional hal f-duplex auxiliary data channel using the clock
`channel of the digital video interface. according to one
`embodiment of the present invention.
`FIG. 2 illustrates a half-duplex link protocol and the trans-
`ceiver configurations at each TDM (time-division multiplex-
`ing} step for implementing the auxiliary channel using the
`clock channel ol'the digital video interface. according to one
`embodiment of tlte present invention.
`FIG. 3 illustrates the hardware implementation of tlte bi-
`directional auxiliary data channel using the clock chamiel of
`the digital video interface, according to one embodiment of
`the present invention.
`FIG. 4 illustrates the operation of the clock data recovery
`(CUR) circttits of the RGB channels. according to one
`embodiment of the present invention.
`
`DETAILED DESCRIPTION OF EMBODIMENTS
`
`The Figures (FIG) and the following description relate to
`preferred embodiments of the present invention by way of
`illustration only. It should be noted that from the following
`discussion. alternative embodiments of the structures and
`methods disclosed herein will be readily recognized as viable
`alternatives that may be employed without departing from the
`principles of the claimed invention.
`Reference will now be made in detail to several embodi~
`
`ments of the present inventionts). examples of which are
`illustrated in the aceompanying figures. 1t is noted that wher-
`ever practicable similar or like reference nutnbers may be
`used in the figures and may indicate similar or like function-
`ality. The figures depict embodiments ofthe present invention
`for purposes of illustration only. One skilled in the art will
`readily recognize front the following description that alterna-
`tive embodiments of the structures and methods illustrated
`
`herein may be etnployed without departing from the prin—
`ciples of the invention described herein.
`FIG. 1 is a conceptual block diagram illustrating the bi-
`directional hal f-duplex auxiliary data channel using the clock
`channel of the digital video interface 100. according to one
`embodiment ofthe present invention. The digital video inter-
`face 100 transmits digital video data. control data. and clock
`signals from the video source device 102 to the video sink
`device 104. The digital video interface 100 includes transmit-
`ters (TX) 108. 110. 112 for transmitting R. G. B digital video
`data. respectively, from the video source 102 over the video
`cables 106 to the video sink device 104. The digital video
`interface 100 also includes receivers (RX) 114. 116. 118 for
`receiving the R. G. B digital video data= respectively. over
`video cables 106 at the video sink 104. The R. G. B channels
`are unidirectional from the video source 102 to the video sink
`104. The video cables 106 include 4 ditferential pairs (3+1 )of
`2 wires. with each ofthe 4 pairs corresponding to the R. G. B.
`and clock channels. respectively.
`-
`The digital video interface 100 also includes a clock ch:
`ne] 120.111e clock channel 120 includes a transmitter 124 for
`transmitting clock and data from the video source 102 to the
`video sink 104 via the video cable 106 and a receiver 126 for
`receiving the clock and data front the video source 102 at the
`video sink 104 via the video cable 106 . Thus. unlike the clock
`
`channel of conventional digital video interfaces, the clock
`channel 120 of the digital video interface 120 of the present
`invention is used to transmit both clock and data. The clock
`
`channel 120 also includes a transmitter 128 for transmitting
`data from the video sink 104 to the video source 102 via the
`video cable 106 and a receiver 122 for receiving the data from
`the video sink 104 at the video source 102 via the video cable
`
`It]
`
`21']
`
`106. Thus. unlike the clock cliarutel of conventional digital
`video interfaces. the clock channel 120 of the digital video
`interface 120 ofthe present invention is bi-directional and can
`be used to transmit data in both directions between the video
`source 102 and the video sink 104.
`As shown in FIG. 1_. the conventional digital video inte -
`face protocol consists of repetitive ‘V’—blank‘ (Vertical Blank)
`and ‘active‘ sequences [or time slots] alternating iii a time-
`divisiona] multiplexing (TDM) manner. The RGB channels
`131 transmit control signals (Ctrl) during the \"-blank
`sequences altd video data (Data) during the active sequences
`in an alternating manner. The clock channel 130 of the con-
`ventional digital video interface continuously transmits the
`clock signal 129 regardless ofwhether the RGB channels are
`in the V—blank sequences or in the active sequences.
`In contrast. the clock channel 120 of the present invention
`is configured to transmit data (in addition to the RGB data
`transmitted via the RGB channel) as well as clock signals.
`The clock channel 120 of the present invention applies tinte-
`division multiplexing (TDM) to the clock channel to enhance
`the clock channel utility. The clock channel 120 is configured
`to transmit clock signals and additional control signals (e.g..
`frame headers. control packets. etc.) 138 while the RGB
`choline] 119 transmits control data (Ctrl) 143 during the
`I.) JI
`. V-blank sequences. and transtnits data signals (Data) 140.
`142 while the RGB channel 119 transmits video data (Data)
`144 during the active sequences. TheTDM ofthe clock chan-
`nel 120 is synchronized to the sequences (video channel
`periods) of the RGB channels 121.
`The data 140. 142 may be. for example. audio data or other
`types of data. The clock channel 120 transmits data signals
`140. 142 bidirectionally. For example. the data 140 is trans-
`mitted in the direction from the video source 102 to the video
`sink 104 via the clock channel 120. and the data 142 is
`transmitted in the direction from the video sink 104 to the
`video source 102 via the clock channel 120. Thus, an auxil—
`iary data channel in addition to the RGB channels 121 is
`enabled by the clock channel 120. The clock channel 120 is
`bi-dircctiona] but half-duplex in the sense that data 140 and
`142 are in different directions but that data can be transmitted
`
`3t]
`
`35
`
`.
`
`5th
`
`55
`
`61]
`
`only uni—directionally at a time in each sequence. Thus, the
`clock channel 120 does not transmit data in both directions at
`
`the same time. By adopting a half-duplex protocol. the aux-
`iliary data channel can be easily transformed to a bi-direc-
`tional link. providing great flexibility in dynamic allocation
`of bandwidth, compared to the conventional digital video
`interfaces.
`
`FIG. 2 illustrates a hal f-duplex link protocol and the trans-
`ceiver configurations at each TDM step for implementing the
`auxiliary channel over the clock chaimel of the digital video
`interface. according to one embodiment ofthe present inven-
`tion. The clock-embedded. half-duplex data charuiel imple-
`mented over the clock chatmel 120 is comprised of trans-
`ceiver cores in each video sourcetsink sides and a 'I'DM
`
`protocol to control them.
`As shown in FIG. 2. the clock chatutel 120 and transceiver
`pairs have 3 Operation modes A. 13. and C. In mode A, the
`clock pattern 138 is transmitted from the video source 102 to
`the video sink 104 via the clock chatutel 120 during V—blank
`sequences (time slots} of the RGB channels 121. In ntode B.
`data 140 [NR2 (Non-Return to Zero) data) is transmitted
`front the video source 102 to the video sink 104 via the clock
`channel 120 during active sequences (time slots) of the RGB
`channels 121. 111 mode C. data 142 (NR2 pattern) is transmit—
`ted in the opposite direction from the video sink 104 to the
`video sottrcc 102 via the clock channel during V—blank
`sequences ot‘the RGB channels 121. Therefore. in modes A
`
`

`

`US 7,940,809 32
`
`5
`and 13. the source receiver 122 and the sink transmitter 128 are
`disabled [as illustrated by the high impedance notation Z in
`the sink transmitter 128). In mode C. the source transmitter
`124 and the sink receiver 126 are disabled (as illustrated by
`the high impedance notation 7'. in the source transmitter l 24).
`Referring to the example sequence of modes as shown in
`FIG. 2. inmode B 150. the data 140 (the frame header 170) is
`transmitted from the video source 102 to the video sink 104
`during the \-"-blank time slot via the clock charmel 120 using
`the transmitter 124 and the receiver 126. In mode A 152. the
`
`clock signal 138 (which is the training sequence 172] is
`transmitted from the video source 102 to the video sink 104
`
`during the V—blank time slot via the clock channel 120 using
`the transmitter 124 and the receiver 126. The clock sequence
`138 is used as a frequency relercncc for main RGB data
`channels while subsequent control packet sets up a link pro-
`tocol for the auxiliary data channel. In tnode B 154. data 140
`which is a control packet 174 is transmitted from the video
`source 102 to the video sink 104 during the V—blank titne slot
`via the clock channel 120 using the transmitter 124 and the
`receiver 126. The control packet 174 indicates whether the
`next data stream is upward (from sink to source) or downward
`(frtom source to sink), and the subsequent data stream is
`transferred accordingly during the active period. For
`example. the control packet 174 indicates downstream traffic.
`In addition. the control packet 174 may contains training
`sequences which help the auxiliary channel transrnitterlrew
`ceiver switch their operation mode smoothly.
`Still in mode IS 154. data 140 which is payload data 176.
`178 are transmitted front the video source 102 to the video
`
`sink 104 during the active time slot via the clock channel 120
`using the transmitter 124 and thereceiver 126. Additionally in
`mode B 154. data 140 which is a frame header 180 is also
`transmitted from the video source 102 to the video sink 104
`during a V—blank time slot via the clock channel 120 using the
`transmitter 124 and the receiver 126. Next. in mode A 156,
`another clock signal 138 (training sequence 182) is transmit-
`ted from the video source 102 to the video sink 104 during the
`V—blank time slot via the clock channel 120 using the trans-
`mitter 124 and the receiver 126. In mode B 158. data 140
`
`(control packet 182) is transmitted from the video source 102
`to the video sink 104 via the clock channel 120 during the
`V—blank time slot using the transmitter 124 and the receiver
`126. ‘l‘his time, the control packet 182 indicates that the
`subsequent data stream will be transferred in the opposite
`direction from the video sink 104 to the video source 102.
`
`Thus. in mode C 160. data 142 (payload data 184. 186} is
`transmitted from the video sink 104 to the video source 102
`during the active time slot via the clock channel 120 using the
`transmitter 128 and the receiver 122.
`
`The auxiliary data channel using the clock channel 120 of
`the present invention has an aggregate bandwidth comparable
`to one ofthe main stream chatmels (R. G, or B). The source
`device can control
`the bandwidth allocation between
`
`upstream traffic and downstream traffic between the video
`source 102 and the video sink 1114. Through a dynamic halid-
`width allocation. the auxiliary channel can be either dedicated
`to uni-directional communication or shared by the upward or
`downward data streams. maximizing bandwidth efficiency.
`FIG. 3 illustrates the hardware implementation 300 of the
`bi-directional auxiliary data channel using the clock channel
`ofthe digital video interface. according to one embodiment of
`the present invention. Note that FIG. 3 only shows compo
`nents necessary for illustrating the present invention. but the
`hardware may include other components not shown in FIG. 3
`in actual implementations. The hardware 300 includes a mas-
`ter link layer 302 corresponding to the video source 102. a
`
`6
`slave link layer 304 corresponding to the video sink 104,
`wires 106 connecting the master link layer 302 with the slave
`link layer 304. sottrce side transmitter 124 for the clock chan-
`nel 120. sotuce side receiver 122 for the clock channel 120.
`sink side receiver 1 26 for the clock channel 120. and sink side
`transmitter 128 for the clock channel 120.
`The RGB channels include latches 350 for storing RGB
`data. output drivers 352 for sending the RGB data via the
`cable 106. receiver buffers 354 for receiving and storing the
`received RGB data. and clock data recovery (CDR) circuits
`356 for recovering the data and clock signals. RGB data are
`transmitted over the RGB channels at the frequency of the
`transmitter clock Tclk as provided by the phase locked loop
`[PLIJ 318 ofthe source side transmitter 124. Note that. in one
`embodiment. three identical data channels exist {as shown in
`the three overlapping blocks in FIG. 3), one each for R. G. B.
`As will be explained in there detail with reference to FIG. 4.
`the RGB CDRs 356 acquire a frequency lock during the
`period when the clock pattern 138 is transmitted over the
`auxiliary channel implemented by the clock channel
`[20.
`then acquire phase lock to the incoming RGB data. and pro—
`vide a stable receiver clock (Rclk) to the sink side transmitter
`128 while it delivers NR2 data from the sink device 104 to the
`source device 102.
`As illustrated above. the source side transmitter 124 is
`active in mode A and mode B, and inclttdes a phase locked
`loop (I’LL) circuit 318. a nutltiplexer 316. a latch 322. and an
`output driver 324. The multiplexer 316 is configured to select
`the clock signal 'l'clk 138 in mode A and the data 140 in mode
`B in response to a selection signal (not shown herein). The
`I’LL 318 synchronizes to the clock signal Tclk and provides
`the synchronized clock signal to the latch 322. the multiplexer
`346 in the source side receiver 122. and the latches 350 in the
`
`ll]
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`20
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`I.) 1):
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`3t]
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`35
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`RGB channels. The latch 322 temporarily stores the output
`[either Tclk 138 in mode A or data 140 in mode B) of the
`multiplexer 316. and the output driver 324 transmits the
`stored clock signal Tclk 138 or data 140 over the cable 106 to
`the sink side receiver 126.
`The sink side receiver 126 is active in mode A and mode B.
`and includes a receiver buffer 340. a multiplexer 332. and a
`clock data recovery [C DR) circttit 330. The receiver buffer
`340 receives the clock signal Telk 138 in mode A or the data
`140 in mode B as transmitted by the source side transmitter
`124. In mode A, the received clock sigtal 'l‘cllt 138 is pro-
`. vided to the C DR circuit 356 of the RGB chaimels. so that the
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`5th
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`55
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`64]
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`CDR circuit 356 can be lulled to the proper frequency to
`recover RGB data correctly. Additional detailed explanation
`regarding the operation of the CDR circuit 356 is set forth
`below with reference to FIG. 4. In mode B the multiplexer 332
`selects the received data signal 140. but in mode A or mode C
`the multiplexer 332 selects the output clock 346 of the PLL
`336 for idling. 1n mode B. the CDR circuit 330 recovers NR}!
`data (data) from the received data signal 140 and provides the
`recovered NRZ data 360 to the synchronisation circuitry 308
`of the slave link layer 304. The syntchronization circuitry 308
`synchronizes tltc recovered NRZ data 360 with the receiver
`clock Rclk recovered by the CDR circuit 356 of the RGB
`channels.
`The sink side transmitter 128 is active in ntodc C. and
`
`includes a phase locked loop (PLL) circuit 366. a latch 334.
`and an output driver 338. The PI .L 336 synchronizes to the
`receiver clock signal Rclk recovered by the CDR circuit 356
`of the RGB chamtels, and provides the synchronized clock
`siyal to the latch 334 and the multiplexer 332 in the sink side
`receiver 126. The latch 334 temporarily stores the data 142.
`and the output driver J38 sends the stored data 142 over the
`cable 106 to the source side receiver 122.
`
`

`

`US 7,940,809 32
`
`7
`'[he source side receiver 122 is active in mode C, and
`includes a receiver butler 326. a multiplexer 346. and a clock
`data recovery (CDR) circttit 328. The receiver butler 326
`receives the data 142 in mode C as transmitted by the sink side
`transmitter 128 and provides it to the multiplexer 346. la
`mode C the multiplexer 346 selects the received data signal
`142. but in rnoch or mode 13 the multiplexer 346 selects the
`output clock Tclk 344 ofthe PLL 318 for idling. In mode C.
`the C.‘DR circuit 328 recovers NRZ data (data) from the
`received data signal 142 and provides tlte recovered NRZ data
`364 to the synchronization circuitry 306 of the master link
`layer 302. The synchronization cll'Cuilly 306 synchronizes
`the recovered NR2 data 364 with the transmitter clock Tclk.
`As illustrated above. the architecture of each transmitter
`
`and receiver is different frotn conventional iinpletnentations.
`for example in the reference clock configuration. The CDRs
`in the auxiliary data channel (implemented by the clock chan-
`nel 120) alternates its reference between systeln clock (Tclk
`in Source and Rclk in Sink) and incoming data according to
`the link operation mode. In modes A and B. the source side
`CDR 328 is synchronized to the system clock (Tclk) from the
`PLL 318 while the sink side CDR 330 is synchronized to the
`incoming data (data 140}. In mode C, the source side CDR
`328 is synchronized to the incoming data (data 142) while the
`sink side CDR 330 is synchronized to the system clock (Rclk)
`from the PLL 336. When the CDRs 328. 330 change their
`reference. a lock-in period is needed for the CDR loops to
`settle. The training sequences 172. 182 in the control packets
`help the CDRs 328. 330 switch their reference quickly and
`smoothly.
`As shown in FIG. 3. the source and sink devices are iii a
`single mesochronous clock system. in which all the building
`blocks operate in a single frequency domain but may not be
`aligned inphase. Thus. the phase synchronization blocks 306.
`308 are used at the boundary of the two different clock
`domains. but the cost of such phase synchronization blocks
`306, 308 is very low because the data rates are exactly iden-
`tical. No flow control such as data rate conversion is required.
`Hence the phase synchronization blocks 306. 308 align the
`recovered data phase with the system clock phase to maxi-
`miae setnpr’hold time margins.
`As shown in 1: 1G. 3. the master link layer 302 handles the
`‘l‘DM based half-duplex commtmication protocol
`and
`dynamically allocates the auxiliary channel bandwidth to the
`upward or downward data stream. Since the uni-directional
`RG13 channels are independent and identical to conventional
`DVI and 1113M] RGB channels, the digital video interface of
`the present invention can be fully compatible with conven~
`tional digital video interfaces by simply disabling the TDM
`operation in the clock channel 120.
`FIG. 4 illustrates the operation of the clock data recovery
`[CDR] circuits 356 of the RG13 channels. according to one
`embodiment of the present invention. Each of the CDR cir-
`cuits 356 forthe RGB channel includes a data recovery loop
`402 and a frequency tracking loop 404. The data recovery
`loop 402 removers RG13 data from the NR2 KGB data
`received over the RGB data channel using conventional data
`recovery circuits and techniques. The frequency tracking
`loop 404 tunes the center frequency ofthe CDR circuit 356 to
`the NR7. data rate of the RGB channel using conventional
`frequency tracking techniques. and the data recovery loop
`402 also regenerates the receiver clock signal Rclk based on
`the tuned (locked) frequency. However. the data recovery
`loop 402 and the frequency tracking loop 404 are unique and
`different from the conventional data recovery loop and the
`conventional frequency tracking loop in conventional CDR
`
`It]
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`21']
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`8
`in that they are enabled or
`circuits for the RGB channel.
`disabled also in a time-division multiplexed manner.
`Specifically. the data recovery loop 402 and the frequency
`tracking loop 404 are enabled or disabled depending upon the
`operation modes of the auxiliary data charutel implemented
`by the clock channel 120 and what auxiliary channel data
`[clock Tclk 138 or data 140} are received over the auxiliary
`data channel. As shown in FIG. 4 together with reference to
`FIG. 3. when the receiver buffer 340 receives and outputs the
`clock signal Tclk 138 over the auxiliary data channel during
`the V—blank period of the RGB channel. the CDR 356 is in
`frequency tracking mode. In the frequency tracking mode, the
`frequency tracking loop 404 is enabled. tuning the center
`frequency of the CDR circuit 356 to the NR7. data rate ofthe
`RG13 charmel. while the data recovery loop 402 is disabled.
`Once the frequency tuning is done. the freq_10ck signal is
`asserted from the lrequency tracking loop 404 to the data
`recovery loop 402. This freq_1ock signal enables the data
`recovery loop 402 to recover the R013 data from the NR7.
`RG13 data and regenerate the receiver clock Rclk. making the
`CDR circuit 356 enter clockldata recovery mode in which the
`data recovery loop 402 is enabled. Once the CDR 356 enters
`clockfdata recovery mode, the frequency tracking loop 404 is
`disabled. and is periodically activated only when the clock
`I.) JI
`. pattern 138 is present at the auxiliary data channel to check if
`the CDR 356 is running at the correct frequency. Typically,
`the V—Blank period is as long as several thousands times of a
`pixnl period. which is long enough for the CDRs 356 to
`acquire frequency lock and smoothly change its reference to
`the RGB NRZ data. As long as the NRZ RGB data are present.
`the CDR circuit 356 can sustain phase lock state by it