(12) United States Patent
`Nagashima
`
`USOO674844.4B1
`(10) Patent No.:
`US 6,748,444 B1
`(45) Date of Patent:
`Jun. 8, 2004
`
`(54) TRANSMISSION SYSTEM OF SHORT TIME
`LAG
`
`(75) Inventor: Masaru Nagashima, Tokyo (JP)
`(73) Assignee: Mitsubishi Denki Kabushiki Kaisha,
`Tokyo (JP)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 622 days.
`
`(21) Appl. No.: 09/609,937
`(22) Filed:
`Jun. 30, 2000
`(30)
`Foreign Application Priority Data
`Nov. 26, 1999
`(JP) ........................................... 11-335890
`(51) Int. Cl." ................................................ G06F 13/00
`(52) U.S. Cl. ........................ 709/236; 709/224; 370/231
`(58) Field of Search ................................. 709/200, 201,
`709/220, 224, 225, 231, 232, 236; 370/230,
`231, 232
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`1/1990 Kondo et al. ............... 370/446
`4,894,819 A
`5,090,011 A 2/1992 Fukuta et al. ............... 370/230
`5,465,354 A 11/1995 Hirosawa et al. ........... 395/650
`5,862.338 A * 1/1999 Walker et al. .............. 709/224
`
`6,067,563 A * 5/2000 Thomas et al. ............. 709/212
`6,094,434 A
`7/2000 Kotzur et al. ............... 370/401
`6,483,845 B1
`11/2002 Takeda et al. .............. 370/429
`FOREIGN PATENT DOCUMENTS
`JP
`A5265 775
`10/1993
`JP
`A667899
`3/1994
`JP
`A7152.588
`6/1995
`* cited by examiner
`Primary Examiner Moustafa M. Meky
`(74) Attorney, Agent, or Firm-Birch, Stewart, Kolasch &
`Birch, LLP
`ABSTRACT
`(57)
`A delay time period, Such as the H/W process time period,
`and the S/W process time period needed for Starting up a
`timer, and a time period from the task Starting to the packet
`transmission beginning are predicted and Stored in the
`control information in advance. A Set value calculating part
`calculates a timer Set value at the System initialization. In a
`packet forming part, the timer Set value is Set in a relative
`time timer for starting the timer. The relative time timer
`generates an interrupt after a specific elapse time has passed
`for Starting a transmission requesting part. By dint of this,
`the time lag of the time period from the period interrupt to
`the packet transmission beginning can be reduced, and each
`of the formed packets is certainly requested to be transmitted
`within each requested time period for processing.
`
`17 Claims, 20 Drawing Sheets
`
`CONTROL PROGRAM
`
`
`
`
`
`
`
`
`
`
`
`
`
`START
`
`7
`
`
`
`INTERRUPT
`DETECTING
`PART
`
`INTERRUPT
`WECTOR
`TABLE
`
`
`
`3
`-
`RELATWE
`TIME
`TIMER
`
`INTERRUPT
`
`PERIODC
`INTERRUPT
`GENERATING
`PART
`OTHER
`FACTOR
`
`2
`
`INTERRUPT
`
`INTERRUPT
`
`TIMER
`OPERATING PT.
`TIMER
`STARTING PT.
`
`
`
`SET UP VALUE
`calcularis Pt.
`
`N
`PACKET FORMING
`PT.
`
`
`
`START
`START
`
`TRANSMISSION
`REQUESTING PT.
`PACKET
`10N-N TRANSMITTING PT.
`
`START
`
`OTHER PROCESS
`(ex. PACKET
`RECEIWING PT.)
`
`13
`
`14
`-1
`INFORMATION
`PART
`CONTROL
`INFO.
`11
`SENSOR
`oBrAIND INFO.
`
`REFER
`
`PACKET
`1 INFO.
`DA
`TRANSFER
`REQUEST
`
`CONTROLLER
`
`LAN
`Sission
`
`5
`4
`
`Ex. 1018 / Page 1 of 35
`ERICSSON v. UNILOC
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`US. Patent
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`Jun.8,2004
`
`Sheet170f20
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`US 6,748,444 B1
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`Ex. 1018 / Page 2 of 35
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`Ex. 1018 / Page 2 of 35
`ERICSSON v. UNILOC
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`U.S. Patent
`US. Patent
`
`Jun. 8, 2004
`
`Sheet 2 0f 20
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`US 6,748,444 B1
`US 6,748,444 B1
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`Ex. 1018 / Page 3 of 35
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`Ex. 1018 / Page 3 of 35
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`US. Patent
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`Jun.8,2004
`
`Sheet3 0f20
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`US 6,748,444 B1
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`Ex. 1018 / Page 4 of 35
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`US. Patent
`
`Jun. 8, 2004
`
`Sheet4 0f20
`
`US 6,748,444 B1
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`Ex. 1018 / Page 5 of 35
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`U.S. Patent
`
`Jun. 8, 2004
`
`Sheet 5 of 20
`
`US 6,748,444 B1
`
`51
`N
`52
`
`53
`
`54
`
`55
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`56
`
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`
`58
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`Fig. 5
`
`START
`
`MASK INTERRUPT
`
`OBTAIN TIMER SET UP WALUE
`
`PROCESS AX
`
`START TIMER
`
`OBTAIN SENSOR DATA
`
`FORM PACKET
`
`STORE PACKET
`
`PROCESS Ay
`
`SET PACKET PREPARATION STATUS
`
`CANCEL INTERRUPT MASKING
`
`END
`
`Ex. 1018 / Page 6 of 35
`ERICSSON v. UNILOC
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`U.S. Patent
`
`Jun. 8, 2004
`
`Sheet 6 of 20
`
`US 6,748,444 B1
`
`Fig. 6
`
`START
`
`61
`
`MASK INTERRUPT
`
`62 - Packet Exists D
`
`63
`
`YES
`REQUEST TRANSMISSION
`
`PROCESS Bi
`
`PROCESS Bj
`
`64
`NO
`
`65
`
`66
`
`67
`
`TRANSMISSION IS FINISHED
`
`YES
`
`CLEAR FRAME INFORMATION
`
`CLEAR PACKET PREPARATION STATUS
`
`CANCEL INTERRUPT MASKING
`
`END
`
`Ex. 1018 / Page 7 of 35
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`US. Patent
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`Jun. 8, 2004
`
`Sheet 7 0f 20
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`US 6,748,444 B1
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`Ex. 1018 / Page 8 of 35
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`Ex. 1018 / Page 8 of 35
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`US. Patent
`
`Jun.8,2004
`
`Sheet8 0f20
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`US 6,748,444 B1
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`Ex. 1018 / Page 9 of 35
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`Ex. 1018 / Page 9 of 35
`ERICSSON v. UNILOC
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`U.S. Patent
`
`Jun. 8, 2004
`
`Sheet 9 of 20
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`US 6,748,444 B1
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`Ex. 1018 / Page 10 of 35
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`U.S. Patent
`US. Patent
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`US 6,748,444 B1
`US 6,748,444 B1
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`ERICSSON v. UNILOC
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`Ex. 1018 / Page 11 of 35
`ERICSSON v. UNILOC
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`US. Patent
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`Jun. 8, 2004
`
`2
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`US 6,748,444 B1
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`U.S. Patent
`
`Jun. 8, 2004
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`Sheet 12 of 20
`
`US 6,748,444 B1
`
`Fig. 12
`
`
`
`Y
`
`63
`
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`
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`
`166
`
`167
`168
`
`169
`
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`
`READ REFERENCE TIME
`
`OBTAIN TIMER SET UP WALUE
`
`PROCESS Ea
`u
`
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`
`START TIMER
`
`STORE REFERENCE TIME
`
`OBTAIN SENSOR DATA
`
`FORM FIRST PACKET
`
`STORE FIRST PACKET
`
`PROCESS Ec
`
`17 O
`
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`
`171
`
`172
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`
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`
`STORE SECOND PACKET
`
`SET SECOND PACKET PREPARATION STATUS
`
`CANCEL INTERRUPT MASKING
`
`END
`
`Ex. 1018 / Page 13 of 35
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`U.S. Patent
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`Jun. 8, 2004
`
`Sheet 13 of 20
`
`US 6,748,444 B1
`
`Fig. 13
`
`START
`
`1
`8
`
`MASK INTERRUPT
`
`182 - Packer Exists 2d-"
`
`183
`
`184
`
`REQUEST TRANSMISSION
`
`CLEAR FIRST PACKET PREPARATION STATUS
`OR SECOND PACKET PREPARATION STATUS
`
`185N
`PACKETS HAVE BEEN TRANSMITTED
`
`OBTAIN TOTAL PREDICTED WALUE
`
`OBTAIN REFERENCE TIME
`
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`
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`
`
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`
`186
`
`187
`
`188
`
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`
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`
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`
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`
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`Ex. 1018 / Page 14 of 35
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`U.S. Patent
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`Jun. 8, 2004
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`Sheet 14 of 20
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`US 6,748,444 B1
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`
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`Ex. 1018 / Page 15 of 35
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`US. Patent
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`Jun.8,2004
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`SheetlS 0f20
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`US 6,748,444 B1
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`Ex 1018/Page 16 of35
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`US. Patent
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`Jun. 8, 2004
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`Sheet16 0f20
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`US 6,748,444 B1
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`Ex. 1018 / Page 17 of 35
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`U.S. Patent
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`Jun. 8, 2004
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`Sheet 17 of 20
`
`US 6,748,444 B1
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`Fig. 17
`
`61
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`162
`s
`
`READ REFERENCE TIME
`
`64
`
`165
`
`66
`
`167
`168
`
`OBTAIN TIMER SET UP WALUE
`
`START TIMER
`
`STORE REFERENCE TIME
`
`OBTAIN SENSOR DATA
`
`FORM FIRST PACKET
`
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`
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`
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`
`182
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`
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`
`CANCEL INTERRUPT MASKING
`
`END
`
`Ex. 1018 / Page 18 of 35
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`U.S. Patent
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`Jun. 8, 2004
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`Sheet 18 of 20
`
`US 6,748,444 B1
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`Fig. 18
`
`START
`
`81
`
`MASK INTERRUPT
`
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`
`183
`
`84
`
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`
`CLEAR PACKET PREPARATION STATUS
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`
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`
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`
`86
`
`187
`
`188
`
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`
`19
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`CAL CULATE TIMER SET UP WALUE
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`PROCESS FK
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`START TIMER
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`N CANCEL INTERRUPT MASKING
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`PROCESS F
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`Ex. 1018 / Page 19 of 35
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`U.S. Patent
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`Jun. 8, 2004
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`Sheet 19 of 20
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`US 6,748,444 B1
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`(WWH)
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`KHOW&W NIWW
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`80%[07
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`6 | “3 | -
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`Z0
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`S?NI YILNI
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`JLYHV CIGALVTEINH
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`Ex. 1018 / Page 20 of 35
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`U.S. Patent
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`Jun. 8, 2004
`
`Sheet 20 0f 20
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`US 6,748,444 B1
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`RELATED ART
`
`Fig. 20
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`2
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`TO BE SET AT REAL
`DECIDING
`TIME WAIT QUEUE AREA
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`212
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`T-NEXT AREA TIME
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`19
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`CHANGE TIME IN COMPARISON
`AREA TO (T-t)
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`SET t AT AREA
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`SET AT HEAD AREA
`YE S
`START REAL TIMER
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`END
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`NO
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`Ex. 1018 / Page 21 of 35
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`1
`TRANSMISSION SYSTEM OF SHORT TIME
`LAG
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`US 6,748,444 B1
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
`This invention relates to a transmission System of Short
`time lag (meaning a reduced Small time lag) where a task is
`Started, in the State that a delay time period, a timer interrupt
`process time period and the like are predicted, based on a
`periodic interrupt as a trigger, and a packet transmission is
`Started within a limited time period (requested time period
`for processing).
`2. Description of the Related Art
`FIG. 19 shows a configuration of a task wait time con
`troller used in a conventional computer System, disclosed in
`Unexamined Japanese Patent Publication HEI 7-152588. In
`FIG. 19, there provided a system bus 201, a CPU (Central
`Calculation Processing Unit) 202 for executing various
`information processes, a ROM (Read Only Memory) 203 for
`memorizing fixed data of operating System (OS), application
`program etc., a RAM (Random Access Memory) 204 for
`memorizing various variable data as a main memory, an
`input/output port 205 for receiving and transmitting data
`from/to an external device, a System timer 206, and a real
`timer 207.
`In the task wait time controller for the conventional
`computer system as shown in FIG. 19, two timers are used
`for measuring a specified wait time period of task execution
`request. One is the system timer 206 which is usually used
`for outputting a periodic interrupt request at a regular cycle
`and the other is the real timer 207 which measures a
`remainder time calculated by Subtracting an odd time period
`from a wait time period and dividing the Subtracted time
`period by the regular cycle. By dint of using the two timers,
`the CPU does not need to execute a useleSS interrupt proceSS
`and each task is Started at an accurate timing designated by
`each specified wait time.
`The task wait time controller set forth above has a
`problem that a delay time period of interrupt proceSS in the
`H/W is not taken into consideration. The real timer wait
`queue Setting process of FIG. 20 shows the case that a
`specified wait time is set as a set value of the real timer 207
`at a step 211 when the Specified wait time is larger than a
`regular cycle. In this case, there is a problem that a delay
`time period occurred during the Steps from 211 up to 221
`where the real timer 207 is actually started is not taken into
`the consideration. Therefore, it is difficult to accurately start
`up a task at the timing Specified by the Specified wait time
`of task execution request.
`In the task execution requests, Some are requesting to
`execute tasks when the Specified time period has passed
`Since the current time, and others are requesting to execute
`tasks within a specified limited time period. For instance,
`Sensor data is transferred to a server through an Ethernet at
`a specified cycle, in the electric power Substation. In this
`case, it is requested to complete processes up to starting the
`data transmission to the Ethernet within 225+25 us based on
`an interrupt generated at a specific period as a reference. For
`dealing with this kind of request, it is not enough to execute
`a task after the Specified time period having passed since the
`current time, as has been done in the conventional System.
`This is a problem of the conventional one.
`One of the objects of the preferred embodiment of the
`present invention is to provide a transmission System of
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`Short time lag in which a packet transmission can be started
`within a limited time period based on a periodic interrupt as
`a trigger in the State that a delay time period, Such as the time
`period of the H/W process responsive to an interrupt, the
`S/W process needed for Starting up a timer, and a time period
`from the task Starting to the packet transmission beginning
`are predicted, and in the State that a timer interrupt genera
`tion time for Starting up the task is Set based on the predicted
`time period. Another object is to lessen a time lag of the time
`period spent from the periodic interrupt to the packet trans
`mission Starting.
`SUMMARY OF THE INVENTION
`According to one aspect of a transmission System of the
`present invention, in which a packet is formed and trans
`mitted within a specific time period, the transmission System
`comprises:
`a periodic interrupt generating part for generating a peri
`odic interrupt at intervals longer than the Specific time
`period;
`a relative time timer in which a specific timer Set value is
`Set, for generating an interrupt by measuring a specific
`elapse time based on the Specific timer Set value;
`a control information memorizing part for memorizing
`control information used for calculating the Specific elapse
`time measured by the relative time timer;
`a Set value calculating part for calculating the Specific
`timer set value to be measured by the relative time timer, by
`using the control information memorized in the control
`information memorizing part;
`a packet forming part, which is Started when the periodic
`interrupt by the periodic interrupt generating part occurs, for
`Setting the Specific timer Set value calculated by the Set value
`calculating part in the relative time timer and forming a
`packet; and
`a transmission requesting part, which is started when the
`interrupt by the relative time timer occurs, for transmitting
`the packet formed by the packet forming part.
`According to one aspect of a transmission method for the
`transmission System of the present invention, in which a
`packet is formed and transmitted within a Specific time
`period, the transmission method comprises:
`generating a periodic interrupt at intervals longer than the
`Specific time period;
`generating an interrupt by measuring a Specific elapse
`time based on a specific timer Set value;
`memorizing control information used for calculating the
`Specific elapse time,
`calculating the Specific timer Set value to be measured by
`a relative time timer, by using the control information;
`when the periodic interrupt occurs, Setting the Specific
`timer Set value in the relative time timer and forming a
`packet; and
`when the interrupt occurs, transmitting the packet.
`The above-mentioned and other objects, features, and
`advantages of the present invention will be made more
`apparent by reference to the following detailed description
`when taken in conjunction with the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`In the drawings,
`FIG. 1 shows a basic theory of a transmission system of
`Short time lag according to Embodiment 1 of the present
`invention;
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`3
`FIG. 2 shows System requests according to Embodiment
`1 of the present invention;
`FIG. 3 shows processes from the periodic interrupt 21 to
`the transmission request 22 of FIG. 2;
`FIG. 4 shows processes performed between the timer
`operating part 17 and the control information 13 according
`to Embodiment 1 of the present invention;
`FIG. 5 shows a process flowchart of the process A 31
`according to Embodiment 1 of the present invention;
`FIG. 6 shows a process flowchart of the process B 32
`according to Embodiment 1 of the present invention;
`FIG. 7 shows processes performed between the timer
`operating part 17 and the control information 13 according
`to Embodiment 2 of the present invention;
`FIG. 8 shows a basic theory of a transmission system of
`Short time lag according to Embodiment 3 of the present
`invention;
`FIG. 9 shows system requests according to Embodiment
`3 of the present invention;
`FIG. 10 shows processes from the periodic interrupt 121
`to the second packet transmission request 123 of FIG. 9;
`FIG. 11 shows processes performed between the timer
`operating part 117 and the control information 113 according
`to Embodiment 3 of the present invention;
`FIG. 12 shows a process flowchart of the process E 131
`according to Embodiment 3 of the present invention;
`FIG. 13 shows a process flowchart of the process F 132
`according to Embodiment 3 of the present invention;
`FIG. 14 shows system requests according to Embodiment
`4 of the present invention;
`FIG. 15 shows processes from the periodic interrupt 121
`to the nth packet transmission request 223 of FIG. 14;
`FIG. 16 shows processes performed between the timer
`operating part 117 and the control information 113 according
`to Embodiment 4 of the present invention;
`FIG. 17 shows a process flowchart of the process E 131
`according to Embodiment 4 of the present invention;
`FIG. 18 shows a process flowchart of the process F1132a
`according to Embodiment 4 of the present invention;
`FIG. 19 shows a configuration of a task wait time con
`troller of a conventional computer System; and
`FIG. 20 shows a flowchart of a conventional real timer
`Wait queue Setting process.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Embodiment 1
`FIG. 1 shows a basic theory of a transmission system of
`Short time lag according to Embodiment 1 of the present
`invention. In FIG. 1, the followings are provided: a control
`program 1 for controlling operations of the transmission
`System of Short time lag according to the present
`Embodiment, a periodic interrupt generating part 2 by which
`a periodic interrupt is generated at a specific time interval,
`a relative time timer 3 by which a timer interrupt is gener
`ated after a Specified time period has passed, a LAN trans
`mission line 4, a LAN controller 5 for transmitting a packet
`formed in the control program 1 to the LAN transmission
`line 4 based on a direction of the control program 1, an
`interrupt vector table 6 which memorizes relations between
`interrupts and process tasks to be started responsive to the
`interrupts, an interrupt detecting part 7 for detecting inter
`rupts by the periodic interrupt generating part 2 or the
`relative time timer 3 and Starting a process task correspond
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`4
`ing to the detected interrupt based on the interrupt vector
`table 6, a packet forming part 8 for forming a packet to be
`output to the LAN transmission line 4 by being started
`responsive to an interrupt from the periodic interrupt gen
`erating part 2, a transmission requesting part 9 for requesting
`the LAN controller 5 to transmit the packet formed by the
`packet forming part 8 by being responsive to an interrupt
`from the relative time timer 3, a packet transmitting part 10
`composed of the packet forming part 8 and the transmission
`requesting part 9 for executing processes from the packet
`forming to the packet transmission requesting, a Sensor
`information 11 for Storing the latest Sensor data updated at
`every periodic interrupt to be transmitted as a packet, a
`packet information 12 for Storing packets formed by the
`packet forming part 8 based on the Sensor information 11, a
`control information 13 for Storing data related to a predicted
`delay time period of the control program 1, the number of
`packets to be transmitted to the LAN transmission line 4 at
`every periodic interrupt occurrence, a limited time period
`needed from the time of the periodic interrupt generation to
`the time of the transmission request to the LAN controller 5,
`and So on, an information part 14 composed of the Sensor
`information 11, the packet information 12, and the control
`information 13, which memorizes information and is located
`on the memory, a Set value calculating part 15 for predicting
`and calculating a time at which a timer interrupt is generated
`by the relative time timer 3, based on the control information
`13, a timer Starting part 16 for Starting the relative time timer
`3 based on a timer set value calculated by the set value
`calculating part 15, and a timer operating part 17 composed
`of the Set value calculating part 15 and the timer Starting part
`16.
`In FIG. 2 showing System requests, a periodic interrupt 21
`indicates a time at which an interrupt from the periodic
`interrupt generating part 2 is generated. The periodic inter
`rupt 21 occurs at intervals of a specific time Tp. A trans
`mission request 22 indicates a time at which the transmis
`Sion requesting part 9 makes a request to the LAN controller
`5.
`In this Embodiment 1, the control program 1 transmits
`one packet at every periodic interrupt 21. It is Supposed there
`exists a time limit that the transmission request 22 should be
`issued within Tito. of the periodic interrupt 21. T stands for
`a requested time period for processing requested by the
`System. C. Stands for a tolerable time lag of the requested
`time period T for processing.
`FIG. 3 shows processes from the periodic interrupt 21 to
`the transmission request 22 of FIG. 2. A timer start 23
`indicates the time at which the timer Starting part 16 Starts
`up the relative time timer 3. A timer interrupt 24 occurs after
`the time Set in the relative time timer 3 has passed.
`Process A31 indicates an interrupt handler responsive to
`the periodic interrupt 21 from the periodic interrupt gener
`ating part 2, that is the processes of the packet forming part
`8 and the timer operating part 17. Process B 32 indicates an
`interrupt handler responsive to the timer interrupt 24 from
`the relative time timer 3, that is the process of the transmis
`sion requesting part 9. A process C 33 indicates a H/W
`process responsive to the periodic interrupt 21 and a proceSS
`D 34 indicates a H/W process responsive to the timer
`interrupt 24.
`The process A31 is supposed to be divided into two at the
`timer start 23. A process AX 35 in the process A31 indicates
`the proceSS from the first instruction of the packet forming
`part 8 to the timer start 23. A process Ay 36 in the process
`A31 indicates the process from the timer start 23 to the last
`instruction of the packet forming part 8.
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`Ex. 1018 / Page 23 of 35
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`The process B 32 is supposed to be divided into two at the
`transmission request 22 to the LAN controller 5 performed
`by the transmission requesting part 9. A process Bi 37 in the
`process B 32 indicates the process from the first instruction
`of the transmission requesting part 9 to the transmission
`request 22. A process B38 in the process B 32 indicates the
`proceSS from the transmission request 22 to the last instruc
`tion of the transmission requesting part 9.
`The time period for each process is defined as follows: the
`time period necessary for the process AX 35 is TAX (timer
`Set-predicted-time-period), the time period necessary for the
`process Bi 37 is TBi (transmission-request-predicted-time
`period), the time period necessary for the process C33 is TC
`(the first process time period or the predicted delay time
`period), and the time period necessary for the process D34
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`is TD (the Second process time period or the predicted delay
`time period).
`In the transmission System of Short time lag, the trans
`mission requesting part 9 is started in order to issue the
`transmission request 22, by generating the timer interrupt 24
`with using the relative time timer 3 after a specific time
`period has passed. This Specific time period is calculated by
`subtracting TAX+TBi+TC+TD from the requested time
`period T for processing, meaning (Requested Time Period T
`for Processing)-(TAX+TBi+TC+TD), that is the time period
`25
`expressed by the Slanted lines in FIG. 3.
`According to the above, it is possible to issue the trans
`mission request 22 within the limited time period (TEC) of
`the periodic interrupt 21. In addition, it is guaranteed that the
`accurate time is kept at the time period from the timer Start
`23 to the timer interrupt 24 because the time period is
`correctly measured by using the relative time timer 3.
`Therefore, factors of the time lag can be restricted to be the
`process AX 35, the process Bi 37, the process C 33 or the
`proceSS D34, meaning the process from the periodic inter
`rupt 21 to the timer start 23 or the process from the timer
`interrupt 24 to the transmission request 22. By way of
`predicting the time period for these processes, the time lag
`(time error) with respect to the real time can be lessened. The
`time lag can be reduced by making the Sum of the time errors
`be within C. In addition, the process efficiency can be
`enhanced by executing other processes Such as a packet
`receiving in the time period between the packet forming and
`the transmission request. This time period is expressed in
`FIG.3 to be between (the process C+the process A): packet
`forming) and (the process D+the process B); transmission
`request), that is a part of the Slanted lines illustrated in FIG.
`3.
`FIG. 4 shows processes performed between the timer
`operating part 17 and the control information 13. Number of
`packets 41 indicates the number of packets to be transmitted
`to the LAN transmission line 4 at every periodic interrupt
`21. In this Embodiment 1, it is Supposed that the packet
`forming part 8 forms one packet at one Starting of the packet
`forming part 8. Therefore, “1” is set as the number of packets
`41 by the packet forming part 8. The number of packets 41
`is set only once at the System initialization and the number
`of packets 41 is not renewed. A requested time period 42 for
`processing indicates the requested time period T for per
`forming processes from the periodic interrupt 21 to the
`transmission request 22, requested by the System.
`A TAX predicted value 43 (timer-set-predicted-time
`period) indicates a predicted process time period needed for
`the process AX35. ATBi predicted value 44 (transmission
`request-predicted-time-period) indicates a predicted process
`time period needed for the process Bi37. A predicted delay
`time period 45 of H/W process (the first process time period,
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`the Second process time period) indicates a predicted process
`time period needed for H/W process performed responsive
`to the interrupt. Each of the process time period TC neces
`sary for the process C 33 and the process time period TD
`necessary for the proceSSD 34 corresponds to the predicted
`delay time 45 of H/W process. Namely, the same value is
`used for the process time periods TC and TD.
`A timer Set value 46 indicating a specific time period is Set
`in the relative time timer 3 based on the calculation of the
`requested time period 42 for processing, the TAX predicted
`value 43, the TBi predicted value 44 and the predicted delay
`time period 45 of H/W process calculated by the set value
`calculating part 15.
`A packet preparation Status 47 shows whether packets to
`be transmitted to the LAN transmission line 4 exist or not.
`The packet preparation Status 47 is Set at the time when the
`packet forming part 8 Stores a packet into the packet
`information 12. The packet preparation Status 47 is cleared
`at the time when the transmission requesting part 9 issues a
`transmission request to the LAN controller 5.
`An error occurs in TC of FIG. 3 by the instruction just
`being executed when the periodic interrupt 21 is generated
`or by the existence of cache or not. Similarly, an error occurs
`in TD of FIG.3 by the instruction just being executed when
`the timer interrupt 24 is generated or by the existence of
`cache or not. Information regarding the proceSS interrupted
`by the packet forming part 8 or the transmission requesting
`part 9 is temporarily Saved. For instance, all the local register
`values of the processor are Saved or the Stack area is
`Switched. These temporary Savings are Sometimes processed
`by S/W in Some processors, while Such Savings are pro
`cessed in the process C 33 and the process D 34 in this case
`of Embodiment 1.
`It is impossible for the control program 1 to know the real
`time period of TC or TD spent on performing the above H/W
`process. Therefore, in order to obtain the predicted delay
`time period 45 of H/W process, a middle value is calculated
`between a predicted maximum value and a predicted mini
`mum value regarding the time period from an interrupt
`detection by the interrupt detecting part 7 to a starting of an
`interrupt handler meaning the packet forming part 8 or the
`transmission requesting part 9.
`Information relating to a time period needed for the S/W
`(interrupt handler) starting is disclosed in Some CPU speci
`fication with the conditions of instructions being executed at
`the time of interrupt occurrence, the cache using, and So on.
`AS the real time period is unknown, a predicted maximum
`value and a predicted minimum value calculated based on
`the above disclosed time period are used for predicting the
`real time period.
`Supposing that the minimum value of the process C is
`TCmin and the maximum value of the process C is TCmax,
`a TC predicted value (the first process time period) is
`calculated to be (TCmin+TCmax)/2. Similarly, supposing
`that the minimum value of the process D is TDmin and the
`maximum value of the process D is TDmax, a TD predicted
`value (the Second process time period) is calculated to be
`(TDmin+TDmax