UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
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`Petitioner
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`v.
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`AQUILA INNOVATIONS INC.
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`Patent Owner
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`Case IPR2019-01526
`U.S. Patent No. 6,895,519
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`PATENT OWNER’S SURREPLY TO PETITIONER’S REPLY
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
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`Petitioner
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`v.
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`AQUILA INNOVATIONS INC.
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`Patent Owner
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`Case IPR2019-01526
`U.S. Patent No. 6,895,519
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`PATENT OWNER’S SURREPLY TO PETITIONER’S REPLY
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`I.
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`II.
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`III.
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`IV.
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`TABLE OF CONTENTS
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`Page
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`PETITIONER ABANDONED ITS ORIGINAL THEORY THAT OBER
`DISCLOSES A “PLURALITY OF ORDINARY OPERATION MODES.” .................... 2
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`THE REPLY CONFIRMS THAT THE COMBINATION DOES NOT RENDER
`THE CLAIMS OBVIOUS ................................................................................................. 5
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`A.
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`B.
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`C.
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`D.
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`Petitioner Admits That “Other Modifications” To Ober Are Necessary To
`Achieve The Claimed Invention ............................................................................ 6
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`Supplying the System Clock, By Itself, Does Not Disclose Ordinary
`Operation Modes .................................................................................................... 8
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`Ober’s “Low Speed Clocks” Is Not Ambiguous ................................................. 11
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`The Power Management State Machine Would Behave Unpredictably If
`Modified ............................................................................................................... 12
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`1.
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`2.
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`Petitioner’s Combination Would Cause System Timer Failures ............. 13
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`Petitioner Does Not Show That Its Combination Would Not Cause
`Ober’s State Machine To Act Predictably Or Stably ............................... 14
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`E.
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`Petitioner Does Not Rebut The Showing That Ober Teaches Away From
`Using Nakazato’s Power-Saving Driver .............................................................. 18
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`PETITIONER HAS NOT SHOWN THAT OBER’S SYSTEM
`INADEQUATELY ADDRESSES SYSTEM CLOCK FAILURES ............................... 20
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`CONCLUSION ................................................................................................................ 21
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`-i-
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`TABLE OF AUTHORITIES
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` Page(s)
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`Federal Cases
`ActiveVideo Networks, Inc. v. Verizon Commc’ns, Inc.,
`694 F.3d 1312 (Fed. Cir. 2012) ................................................................ 5, 12, 13
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`Hulu, Inc. v. Soundview Innovations LLC,
`IPR2018-00582, Paper No. 34 (Aug. 5, 2019) ..................................................... 4
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`Intelligent Bio-Systems, Inc. v. Illumina Cambridge,Ltd.,
`821 F.3d 1359 (Fed. Cir. 2016) ...................................................................... 3, 12
`
`Kinetic Concepts, Inc. v. Smith & Nephew, Inc.,
`688 F.3d 1342 (Fed. Cir. 2012) .......................................................................... 20
`
`KSR Int’l Co v. Teleflex, Inc.,
`550 U.S. 398 (2007) .............................................................................................. 6
`
`Polaris Indus. v. Arctic Cat, Inc.,
`882 F.3d 1056 (Fed. Cir. 2018) .......................................................................... 19
`
`SAS Inst., Inc. v. Iancu,
`138 S. Ct. 1348 (2018) .......................................................................................... 2
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`Wasica Fin. GmbH v. Continental Automotive Sys., Inc.,
`853 F.3d 1272 (Fed. Cir. 2017) ............................................................................ 3
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`Federal Statutes
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`35 U.S.C. § 312(a)(3) ................................................................................................. 2
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`Regulations
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`37 C.F.R. § 42.6(a)(3) .............................................................................................. 17
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`37 C.F.R. § 42.23(b) .................................................................................................. 3
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`-ii-
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`PATENT OWNER’S UPDATED EXHIBIT LIST
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`2003
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`Exhibit No. Description
`2001
`Joint Claim Construction Statement dated May 17, 2019
`2002
`Revised Joint Claim Construction Statement dated November 1,
`2019
`Markman Order re Infineon Technologies AG and Infineon
`Technology North America Corp. v. Atmel Corporation
`Email Correspondence with Board re Sur-Replies
`Declaration of Dr. Steven Przybylski
`Curriculum Vitae of Dr. Steven Przybylski
`MNSC140CORE Reference Manual
`ARM920T Technical Reference Manual
`DDI0275 ETB11 Technical Reference Manual
`Excerpts from CRC Modern Dictionary Electrical Engineering
`VDHL Coding Styles and Methodologies, 2nd Ed.
`Transcript of D Albonesi May 21 deposition
`Microsoft Computer Dictionary, 5th Ed.
`Graf Modern Dictionary of Electronics
`Declaration of Melanie Arlantico
`Library of Congress Catalog VHDL coding styles and
`methodologies, B Cohen, 2nd Ed.
`Copyright Catalog VHDL coding styles, B Cohen, 2nd Ed.
`
`2004
`2005
`2006
`2007
`2008
`2009
`2010
`2011
`2012
`2013
`2014
`2015
`2016
`Not Filed
`2017
`Not Filed
`2018
`Not Filed
`2019
`Not Filed
`2020
`Not Filed
`2021
`Not Filed
`
`Copyright Catalog Comprehensive dictionary of electrical
`engineering, 2nd Ed.
`Copyright Catalog Modern dictionary of electronics, R Graaf, 7th
`Ed.
`Copyright Catalog Microsoft computer dictionary, 5th Ed.
`
`Library of Congress Catalog Comprehensive dictionary of
`electrical engineering, P Laplante, 2nd Ed.
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`-iii-
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`Exhibit No. Description
`2022
`Joint Claim Construction Statement with Attachment A, May 17,
`2019
`Not Filed
`2023
`Transcript of the September 28, 2020 deposition of David H.
`Albonesi
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`-iv-
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`In accordance with the Board’s scheduling order, Paper No. 13, Patent
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`Owner Aquila Innovations Inc. (“Aquila”) submits this sur-reply regarding the
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`patentability of claims 1 through 9 of U.S. Patent No. 6,895,519 (the “’519
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`patent”).
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`Petitioner has not shown by a preponderance of the evidence that any claims
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`of the ’519 patent are unpatentable over the asserted references. Petitioner admits
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`that the combination of Ober and Nakazato requires “other modifications” that
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`Petitioner has not presented in order to write to unused bits in the Ober registers. In
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`a belated attempt vaguely to describe these modifications, Petitioner now asserts
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`that it proposes to make the Ober-Nakazato combination “ACPI-compatible.” But
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`Petitioner ignores the ACPI’s warning against using unused bits in ACPI registers.
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`Petitioner also improperly points to the “creativity” of a skilled artisan to fill in the
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`gaps of its admitted failure to present a prima facie case of obviousness, and
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`attempts to shift the burden of proof to Aquila. None of these last-ditch efforts save
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`the combination and helpfully underscore the problems that infect the petition.
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`Ober, alone or in combination with Nakazato, does not teach a “plurality of
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`ordinary operation modes.” Nakazato’s power saving driver, when loaded into
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`Ober’s memory banks, would not control clock frequency transitions between the
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`claimed ordinary operation modes because Ober’s microcontroller does not,
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`without modifications to its hardware, transition clock frequencies during RUN
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`mode. Ober even teaches away from using something like Nakazato’s power-
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`saving driver by disparaging the type of power management approach utilized in
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`Nakazato. In addition, using Nakazato’s power-saving driver to write to unused
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`bits in the Ober registers would cause the combination microcontroller to behave
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`unpredictably. As a result of this unpredictability, a person of ordinary skill in the
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`art would have no reasonable expectation that the combination of Ober and
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`Nakazato would be successful.
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`Finally, Petitioner has not shown by a preponderance of the evidence why a
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`person of ordinary skill in the art would have been motivated to modify Ober to
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`use redundant clocks from the Doblar reference. Ober’s power management state
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`machine already addresses system failures with its FAULT mode. A hindsight
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`motivation is never legally sufficient. The Board should confirm that patentability
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`of claims 1 through 9 of the ’519 patent.
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`I.
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`PETITIONER ABANDONED ITS ORIGINAL THEORY THAT
`OBER DISCLOSES A “PLURALITY OF ORDINARY OPERATION
`MODES.”
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`Petitioner argues for the first time in its reply that the combination of Ober
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`and Nakazato discloses the “plurality of ordinary operation modes” recited in the
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`preamble. Paper No. 24 at 3-12. Petitioner was required to state its grounds of
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`challenge with particularity in the petition, 35 U.S.C. § 312(a)(3), and may not
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`raise new theories and new combinations in reply. See SAS Inst., Inc. v. Iancu, 138
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`S. Ct. 1348, 1356 (2018). “[T]he expedited nature of IPRs bring with it an
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`obligation for petitioners to make their case in their petition to institute.” Intelligent
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`Bio-Systems, Inc. v. Illumina Cambridge, Ltd., 821 F.3d 1359, 1369 (Fed. Cir.
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`2016); see also Wasica Fin. GmbH v. Continental Automotive Sys., Inc., 853 F.3d
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`1272, 1287 (Fed. Cir. 2017) (“We also are unpersuaded by [petitioner]’s attempts
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`to cure the petition’s deficiencies in its subsequent briefing to the Board and to
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`us.”); Trial Practice Guide (Aug. 2018 Update) at 14; 37 C.F.R. § 42.23(b).
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`Ground 1 of the petition relied on Ober for the purported disclosure of the
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`preamble of claim 1. See Paper No. 2 at 24-25. Petitioner did not assert that the
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`combination of Ober and Nakazato disclosed the preamble’s “plurality of ordinary
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`operation modes.” Dr. Albonesi also did not opine in his original declaration that
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`the combination of Ober and Nakazato disclosed the plurality of ordinary operation
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`modes. See Ex. 1003 ¶¶ 93-107. Dr. Albonesi admitted on cross-examination that
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`his opinion relied on Ober alone for the “ordinary operation modes” in the
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`preamble. Ex. 2012 23 13-24:10; 25:7-13; see also Ex. 2023 91:10-106:8 (Dr.
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`Albonesi admitting that he did not cite Nakazato in paragraphs 93–107 of his
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`original declaration).
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`Petitioner unsuccessfully attempts to tie its new contention back to the
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`petition. See Paper No. 24 at 3 (citing Paper No. 2 at 16-17). But there is no
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`support in the petition. The petition reveals that Petitioner did not argue that Ober
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`and Nakazato disclosed the claimed “plurality of ordinary operation modes.” Paper
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`No. 2 at 19-25. See Hulu, Inc. v. Soundview Innovations LLC, IPR2018-00582,
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`Paper No. 34 at *23 (Aug. 5, 2019) (precedential) (rejecting new motivation to
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`combine arguments where citations to the petition were not parts of the motivation
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`to combine discussion). To the contrary, the petition states that “Ober discloses a
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`‘system LSI’ having a plurality of ‘ordinary operation modes,’ ‘special operating
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`modes,’ and a ‘clock generation circuit’ that receives a ‘plurality of standard
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`clocks.’” Paper No. 2 at 16.; see also id. at 17 (“With respect to switching among
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`‘ordinary modes,’ Ober explains that it can adjust the frequency of the system
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`clock during either sleep mode or ‘normal mode.’”); 7 (“Ober’s ‘system LSI’ also
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`includes ‘ordinary operation modes’ and ‘special operation modes.’ Specifically,
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`Ober explicitly discloses changing CPU clock frequency by dividing the CPU
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`clock.”). Petitioner also argued that a person of ordinary skill in the art would have
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`been motivated to seek out Nakazato for its power-saving driver for the claimed
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`“clock control library.” Id. at 18 (“This writing of data, according to an
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`embodiment of Nakazato, is controlled by a driver (i.e., a clock controlled library)
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`installed in the OS of the computer.”). Petitioner did not argue that Ober combined
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`with Nakazato would disclose the plurality of ordinary operation modes, and
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`reiterated its theory that Ober alone disclosed the plurality of ordinary operation
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`modes. Paper No. 2 at 16, 17. Having failed to argue that the combination of Ober
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`and Nakazato disclose the plurality of ordinary operation modes, Petitioner should
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`not be permitted belatedly to raise it in reply.
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`Importantly, by advancing a new argument that the combination of Ober and
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`Nakazato discloses the “plurality of ordinary operation modes” recited in the
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`preamble, Petitioner abandons its original contention that Ober alone discloses the
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`claimed “plurality of ordinary operation modes.” Petitioner’s acknowledgment that
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`the theory advanced in the petition is defective should be controlling and the Board
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`should find that the challenged claims are patentable.
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`II. THE REPLY CONFIRMS THAT THE COMBINATION DOES NOT
`RENDER THE CLAIMS OBVIOUS.
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`A petitioner in inter partes review bears the burden of showing “[1] how
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`specific references could be combined, [2] which combination(s) of elements in
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`specific references would yield a predictable result, or [3] how any specific
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`combination would operate or read on the asserted claims.” ActiveVideo Networks,
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`Inc. v. Verizon Commc'ns, Inc., 694 F.3d 1312, 1327-28 (Fed. Cir. 2012). To
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`invalidate a claim based on obviousness, the petitioner must demonstrate “‘that a
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`skilled artisan would have been motivated to combine the teachings of the prior art
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`references to achieve the claimed invention, and that the skilled artisan would have
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`had a reasonable expectation of success in doing so.’” Id. at 1327 (quoting Pfizer,
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`Inc. v. Apotex, Inc., 480 F.3d 1348, 1361 (Fed. Cir. 2007)). Petitioner has not met
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`its burden in this case.
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`-5-
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`Ober alone does not teach or suggest executing instructions on a reduced
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`clock frequency because the RUN mode is the only ordinary operation mode and it
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`operates at one clock frequency. See Paper No. 19 at 27-36. The Ober and
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`Nakazato combination does not teach the claimed clock control library for
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`controlling a clock frequency transition between said ordinary operation modes
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`because Nakazato’s driver would not cause Ober’s CPU to execute instructions on
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`different clock frequencies. See Paper No. 19 at 36-43. As a result, the combination
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`of Ober and Nakazato does not render any claims of the ’519 patent obvious.
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`Petitioner cannot overcome these deficiencies.
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`A.
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`Petitioner Admits That “Other Modifications” To Ober Are
`Necessary To Achieve The Claimed Invention.
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`Petitioner asserts that it would have “made no sense” for a person of
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`ordinary skill in the art to modify SFR 62 “without making any other modifications
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`to Ober to use those bits.” Paper No. 24 at 15. If so, Petitioner should have stated,
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`with explicit particularity and rational underpinning, see KSR Int’l Co v. Teleflex,
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`Inc., 550 U.S. 398, 418, (2007), what modifications a skilled artisan would have
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`been motivated to make and why. Petitioner did not identify any “other
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`modifications” that a skilled artisan would have needed to make in order for
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`Petitioner’s asserted combination of Ober and Nakazato to result in the claimed
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`invention of the ’519 patent. See e.g., Paper 19 at 37 (“Petitioner does [not]
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`propose any hardware modifications.”); 47 (“Even assuming a person of ordinary
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`skill in the art could have succeeded, through a substantial modification of the
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`power management block 26, substantial modification of SFR 62 to put register
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`bits where non previously existed and to cause those new register bits to produce
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`the effect hypothesized by Petitioner, and supplied a low-speed clock to the CPU
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`core 22 while it is active through the unused bits of SFR 62, the result would have
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`been an undefined state outside of the bounds of the pre-defined discreet states
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`recognized by Ober’s power management state machine.”). But without these
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`unidentified “other modifications,” Petitioner’s combination of Ober and Nakazato
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`does not disclose the claimed “plurality of ordinary operations modes” or “control
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`clock frequency transitions between said ordinary operation modes.”
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`Petitioner does not identify what modifications it contends a person of
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`ordinary skill in the art would have known to make in order to achieve the
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`invention in claim 1 of the ’519 patent. Although Dr. Albonesi opines that these
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`unidentified modifications are within the level of skill in the art, see Ex. 1028 ¶¶
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`43-46, he does not (1) address the fact that neither he nor Petitioner ever previously
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`proposed any modifications to Ober’s hardware or (2) explain how, in the absence
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`of modifications to Ober’s hardware, a skilled artisan would be able to effect clock
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`frequency transitions simply by writing to blank register fields in the SFR 62. Ex.
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`1028 ¶ 46. In contrast to Dr. Przybylski’s detailed explanation, see Ex. 2005 ¶¶ 95-
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`98, Dr. Albonesi’s conclusory, unsupported testimony is not entitled to any weight.
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`-7-
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`Petitioner counters that “a person of ordinary skill in the art is not an
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`automaton.” Paper No. 24 at 16 (citing KSR, 550 U.S. at 421). While true,
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`Petitioner’s reliance on a maxim of patent law is not evidence, and certainly is no
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`substitute for proof. It is not sufficient for Petitioner to declare that an ordinarily
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`creative person of skill in the art would have divined other modifications to Ober’s
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`hardware to allow clock frequency transitions in Ober. Petitioner must recite those
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`modifications in sufficient detail to meet its burden and provide Aquila a target for
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`a response. Petitioner admits that its asserted combination of Ober and Nakazato
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`requires further modifications. Having not described those modifications,
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`Petitioner has not met its burden to demonstrate that claims 1 through 9 of the ’519
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`patent are unpatentable over Ober and Nakazato.
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`B.
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`Supplying the System Clock, By Itself, Does Not Disclose
`Ordinary Operation Modes.
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`Petitioner argues that Ober discloses a “plurality of ordinary operation
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`modes.” Paper No. 24 at 9. It contends that Ober’s “CPU,” as depicted in
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`Petitioner’s annotated Figure 1, includes the FPI. It further argues that accepting
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`Aquila’s argument that the subsystems each include the FPI, Ober’s CPU
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`necessarily receives divided clocks because the subsystems receive divided clocks.
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`See Paper No. 24 at 9 (“And thus, by acknowledging that at least ‘subsystems 30-
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`40’ can have their clocks adjusted during ‘normal mode,’ PO is effectively
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`conceding that Ober’s CPU, as identified by AMD, is also having its clock divided
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`-8-
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`during ‘normal mode,’ because FPIs 42-52 are part of the CPU identified by
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`AMD.”)
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`Setting aside Petitioner’s misguided argument that Aquila simultaneously
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`challenged and did not challenge Petitioner’s annotation of Figure 1, Petitioner’s
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`argument incorrectly assumes that the subsystems run on the System Clock. The
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`FPI, through control of the SFR 116, control the local clock provided to the
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`subsystems through their DivClk and SlpClk bits. Ex. 1004 9:49-10:6. It is
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`important to examine the phrase “may supply divided clocks to the peripherals
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`during a normal mode” from Ober. Ex. 1004 9:65-10:2. Petitioner confuses what
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`component is supplying the “divided clock” to the peripherals during “normal
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`mode,” and attempts to sow confusion with respect to the “divided clock” and
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`“normal mode” elements. Ober teaches that the FPI, through its control of SFR
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`116, is capable of dividing the system clock.1 During RUN mode, when the CPU
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`1 Ober unequivocally teaches that the various SFR 116 for each subsystem are in
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`the respective FPI blocks. Ex. 1004, Abstract, Fig. 1, 4:19-24, Cl. 1 Ober also
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`teaches that the FPI blocks are separate from the FPI busses. Ex. 1004, Fig. 1,
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`2:59-62, 2:65-3:16, 3:56-61, 3:62-67, 4:19-24, 5:35-37, claims 1, 5. Ober further
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`teaches that each FPI block has its own SFR 116 that controls the frequency of the
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`local clock in each subsystem. Id. at Col. 4:19-24. Ober’s claims also confirm that
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`core 22 and the system clock are both at full speed, each of the peripherals, through
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`its own SFR 116 and FPI, may request that its own clock be divided. Ex. 1004
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`9:59-10:2 (“As noted in Table 4, the register 116 includes … a divide clock
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`(DIVCLK) bit … may also provide a divided clock signal to the subsystem during
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`a normal mode.”). As explained in the patent owner response, the division of the
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`peripheral clocks does not mean that the system clock is divided during RUN
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`mode. Paper No. 19 at 29-31. Contrary to Petitioner’s assertion, the clock
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`generator does not provide reduced speed clocks to the FPIs during RUN mode.
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`Even assuming that Petitioner is correct that the clock generator supplies
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`reduced speed clocks to the system, the mere act of supplying the system clock
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`from the clock generator is not sufficient to disclose the claimed “plurality of
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`ordinary operation modes.” The preamble of claim 1 recites that the ordinary
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`operation modes are “in response to clock frequencies supplied to a central
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`processing unit.” Ex. 1001, Claim 1. Merely supplying clock frequencies, without
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`operation, that is, the CPU core executing instructions, is not sufficient to disclose
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`an “ordinary operation mode.” Ex. 2005 ¶ 42; see also Ex. 1003 ¶ 102 (“the
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`claimed ordinary operation modes operate at different frequencies”). And even
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`the subsystems, FPI blocks, and FPI busses are each separate components, and that
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`the SFR 116 are located in the peripheral interfaces. See Ex. 1004, Claim 1.
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`under Petitioner’s theory of Ober’s “CPU,” only the CPU core 22 is “operating.”
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`The claim language requires more than supplying a system clock; it requires that
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`the CPU is executing instructions. Paper No. 19 at 20-22. Petitioner does not
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`dispute Aquila’s proposed construction of “ordinary operation modes” to require
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`that the CPU execute instructions. Paper No. 24 at 2-3. Ober alone or in
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`combination with Nakazato does not disclose a “plurality of ordinary operation
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`modes.”
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`C. Ober’s “Low Speed Clocks” Is Not Ambiguous.
`In response to Aquila’s argument that Ober defines RUN mode to require
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`the state variable “Low Speed Clocks” to be “False,” Petitioner argues that “Ober
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`never suggests that ‘Low Speed Clocks’ is equivalent to a reduced system clock.”
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`Paper No. 24 at 10. Petitioner does not attempt to explain to what “Low Speed
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`Clocks” is “equivalent,” arguing instead that the Board should ignore the plain
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`meaning of the phrase “low speed clock” and Ober’s disclosures regarding the
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`“Low Speed Clock” variable. Ober teaches that the “Low Speed Clocks” variable
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`is “True” when the “ClkSrc” bits take any value other than “0000.” Ex. 1004
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`18:13, 18:54. Petitioner is thus not correct that the state variables are divorced from
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`the SFR 62. Instead of rebutting Aquila’s argument, Petitioner confirms its reliance
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`on hindsight to cherry pick isolated disclosures from the references in its attempt to
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`reconstruct the claimed inventions.
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`-11-
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`D. The Power Management State Machine Would Behave
`Unpredictably If Modified.
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`Claim 1 of the ’519 patent includes a “clock control library for controlling
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`clock frequency transitions between said ordinary operation modes.” Ex. 1001,
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`Claim 1. Petitioner concedes that Ober alone does not teach or disclose the “clock
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`control library for controlling clock frequency transitions between said ordinary
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`operation modes,” and relies on Nakazato’s power-saving driver loaded into
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`Ober’s memory banks for this element. See Paper No. 2 at 18. In order to establish
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`obviousness, Petitioner asserts that a person of ordinary skill in the art would be
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`motivated to combine Ober with the power-saving driver of Nakazato and write
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`data to the unused bits in SFR 62 with a reasonable expectation of success.
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`ActiveVideo, 694 F.3d at 1327.
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`The Petition advanced only a conclusory theory for the reasonable
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`expectation of success in making this combination. See Paper No. 2 at 18; Ex. 1003
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`¶ 91 (“This would result in a reasonable expectation of success because both
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`Nakazato’s software is already described as modifying registers to change a CPU
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`clock frequency and Ober’s system includes registers to change CPU clock
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`frequency.”). Aquila showed that Petitioner’s proposed combination would not
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`produce a reasonable likelihood of success in meeting the limitations of claim 1 of
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`the ’519 patent. Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d
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`1359, 1367 (Fed. Cir. 2016) (“The reasonable expectation of success requirement
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`-12-
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`refers to the likelihood of success in combining the references to meet the
`
`limitations of the claimed invention.”). Ober’s system does not have registers to
`
`change CPU clock frequency, and writing to the unused bits of SFR 62 would not
`
`result in clock frequency transitions in the CPU but would produce unpredictable
`
`responses. Paper No. 19 at 44-48; Ex. 2012 at 69:5–71:20.
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`Petitioner’s Combination Would Cause System Timer Failures.
`
`1.
`Petitioner’s reply does not offer a reasonable response to Aquila’s showing
`
`that the proposed combination of Ober and Nakazato would produce unpredictable
`
`and undesirable behavior. Dr. Albonesi admitted that writing to the unused bits in
`
`SFR 62 could be problematic, undercutting Petitioner’s rationale for using
`
`Nakazato’s driver to write to those bits. Ex. 2012 at 69:5–71:20.
`
`To begin, Petitioner agrees with Aquila that changing the system clock
`
`would change the input frequency of the peripherals. Paper No. 24 at 7; Paper No.
`
`19 at 52. Changing the input frequency would cause components, such as the
`
`System Timer 62, to fail because the components would unexpectedly receive
`
`input clocks with reduced frequency, and they would not keep time properly. Paper
`
`No. 19 at 52. Petitioner does not address this other than to rely on the level of skill
`
`in the art. But that is not a substitute for proof. ActiveVideo, 694 F.3d at 1327.
`
`-13-
`
`
`
`
`
`2.
`
`Petitioner Does Not Show That Its Combination Would Not
`Cause Ober’s State Machine To Act Predictably Or Stably.
`
`Next, Petitioner argues that “[c]hanging a state variable would not cause the
`
`system to behave unpredictably, because they are meant to be changed.” Paper No.
`
`24 at 17. This is not correct. Ober’s power management state machine is the
`
`“heart” of Ober’s power management system. Paper No. 19 at 47, citing Ex. 1004
`
`17:2-3. A state machine is a mathematical model that can be in one of a finite
`
`number of discreet states at one time defined by state variables. Paper No. 19 at 46,
`
`citing Ex. 2010 at 262; Ex. 2011 at 296, 656. A person of ordinary skill in the art
`
`would not have been motivated to use Nakazato’s power-saving driver to write bits
`
`into Ober’s SFR 62 because such a combination would have caused the state
`
`machine to act unpredictably.
`
`A state machine that enters an undefined state behaves unpredictably. Ex.
`
`2011 at 304 (“What happens if the state register enters [an undefined state]? The
`
`action to be taken in one of those undefined states is tool dependent and is
`
`unpredictable.”); see also Ex. 2005 ¶ 97.2 Petitioner admits that it proposes to
`
`modify Ober to be ACPI-compatible. Paper No. 24 at 23 (“The Petition instead
`
`describes modifying Ober and Nakazato to make them ACPI compatible.”). The
`
`
`2 Paragraph 97 of Dr. Przybylski’s declaration inadvertently cited to Exhibit 2010
`
`instead of Exhibit 2011 at 304.
`
`-14-
`
`
`
`
`
`ACPI specification teaches that undefined bits in a power management register
`
`should be left alone. Ex. 1013 at 0065-66. Data written to undefined bits in power
`
`management registers are either ignored or cause unpredictable results. Paper No.
`
`19 at 45 (citing Ex. 1013 at 0065-66). Any data written to the unused bits in Ober’s
`
`SFR 62 would be ignored or cause unpredictable results. Under no circumstances
`
`would the ignored bits result in a frequency change during RUN mode and
`
`Petitioner presents no evidence to the contrary.
`
`Modifying the RUN mode using the bits of SFR 62 to operate on low speed
`
`clocks would also cause Ober’s system to become unstable in IDLE mode. Paper
`
`No. 19 at 51. Dr. Przybylski’s unrebutted testimony shows that the bits of Ober’s
`
`SFR 62 are tied to hardware control. Ex. 2005 ¶ 57. IDLE mode is requested by
`
`setting a bit in the ReqSlp field of SFR 62. In IDLE mode, the CPU core’s local
`
`clock is shut down and the peripherals are fully clocked. Ex. 2005 ¶ 96.
`
`Petitioner’s combination would result in Ober’s system unpredictably vacillating
`
`from a low-speed RUN mode to a full-speed IDLE mode. Id. “Indeed, as
`
`presented, the frequency being provided to the peripherals would jump from a
`
`divided clock to an undivided clock and back again without warning as the CPU
`
`core 22 transitioned from RUN MODE to IDLE MODE and back at the direction
`
`of the PMSM.” Id. Thus, Petitioner’s combination would also result in
`
`-15-
`
`
`
`
`
`unpredictable and undesirable behavior in the transitions between RUN and IDLE
`
`mode.
`
`Dr. Albonesi, in a portion of his declaration not cited or discussed by
`
`Petitioner in its reply, cites to paragraphs 112 and 113 of his original declaration to
`
`support Petitioner’s proposed combination. Ex. 1028 ¶ 47 (citing Ex. 1003 ¶¶ 112-
`
`113.). Neither of those paragraphs explains why a person of ordinary skill in the art
`
`would have enjoyed a reasonable expectation of success in writing to the unused
`
`bits in SFR 62. Paragraph 112 merely states that SFR 62 has unused bits while
`
`paragraph 113 asserts, without support, that writing to the unused bits in SFR 62
`
`would have resulted in divided clocks being provided to the CPU during RUN
`
`mode. Absent modification of Ober’s hardware, which Petitioner does not
`
`articulate, the data written by Nakazato’s driver would be ignored by the power
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`manager or place the state machine in an undefined state. Ex. 2005 ¶ 98; Ex. 2011
`
`at 304; Ex. 1013 at 0065-66.3
`
`
`3 Dr. Albonesi also asserts, for the first time, that a person of ordinary skill in the
`
`art would have known to define a new state using the existing state variables. Ex.
`
`1028 ¶ 52. The reply does not cite to this paragraph, nor does it discuss Dr.
`
`Albonesi’s new theory. The Board should disregard this new theory, as Petitioner
`
`obviously did not think it worthy of actual discussion, opting instead to incorporate
`
`
`
`-16-
`
`
`
`
`
`Dr. Albonesi does not rebut Dr. Przybylski’s testimony – that writing to
`
`Ober’s unused bits would produce unpredictable behavior. Like the Petitioner, he
`
`relies on the knowledge of a skilled artisan to make unspecified changes that
`
`should have been set forth with particularity in the petition. Ex. 1028 ¶¶ 47-48. He
`
`does not explain what changes a person of skill in the art would have made, nor
`
`does he explain why, contrary to the petition’s theory, a person of ordinary skill in
`
`the art would have been motivated to make those changes. His conclusory opinions
`
`are entitled to no weight. Absent the unexplained changes, Petitioner’s
`
`combination would result in a system with unpredictable behavior that no person
`
`of ordinary skill in the art would be motivated to achieve, let alone accept.
`
`At bottom, the combination of Ober and Nakazato admittedly requires “other
`
`modifications” to Ober in order for a person of ordinary skill in the art to have a
`
`reasonable expectation of success. Paper No. 24 at 16. But as presented in the
`
`petition, the combination simply would not have the effect that Petitioner hopes to
`
`achieve. Ex. 2005 ¶ 98. The combination would not cause the power manager to
`
`
`Dr. Albonesi’s new argument by reference from the reply declaration. 37 C.F.R. §
`
`42.6(a)(3). Furthermore, if a modification to the state machine was necessary, then
`
`Petitioner’s failure to adequately present the necessary modification in the petition
`
`is fatal to its case. ActiveVideo, 694 F.3d at 1327.
`
`
`
`-17-
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`
`
`
`
`control the clock generator to generate a different frequency for the system clock
`
`during RUN mode. A person of ordinary skill in the art would not have reasonably
`
`expected that using Nakazato’s driver to write to the undefined bits in SFR 62
`
`would transform Ober’s microcontroller into the inventive system LSI claimed in
`
`the ’519 patent.
`
`E.
`
`Petitioner Does Not Rebut The Showing That Ober Teaches Away
`From Using Nakaza
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