UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`ADVANCED MICRO DEVICES, INC.
`Petitioner
`
`V.
`
`AQUILA INNOVATIONS, INC.
`Patent Owner
`
`Case IPR2019—01526
`
`US. Patent No. 6,895,519 B2
`
`PETITION FOR INTER PARTES REVIEW
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`US. Patent & Trademark Office
`
`PO. Box 1450
`
`Alexandria, VA 22313—1450
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`TABLE OF CONTENTS
`
`I.
`
`INTRODUCTION ........................................................................................... 1
`
`II.
`
`IDENTIFICATION OF THE CHALLENGE ................................................. 1
`
`III.
`
`THE ’519 PATENT ......................................................................................... 2
`
`A.
`
`B.
`
`The ’519 patent admits that most of its claimed elements were
`well-known, and arranged in the same manner as its claims. ............... 2
`
`The ’5 l9 specification’s alleged points of novelty are
`insignificant and well-known. ............................................................... 4
`
`IV. ASSERTED REFERENCES ........................................................................... 6
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Like the challenged claims of the ’5 19 patent, Ober
`discloses a System LSI with a clock generation circuit
`that receives a plurality of clocks and a system control
`circuit that can switch between ordinary operation
`modes and special operation modes via a register...................... 6
`
`Nakazato discloses “a clock control library” and an
`“application” for controlling CPU frequency. ............................ 8
`
`Cooper and Windows ACPI disclose a main library
`and a plurality of clock control libraries ..................................... 9
`
`Doblar discloses a PLL that receives a plurality of
`clock signals and then multiplies them ..................................... 11
`
`Ober, Nakazato, Cooper, Windows ACPI, and Doblar
`are prior art................................................................................ 12
`
`V.
`
`CLAIM CONSTRUCTION .......................................................................... 13
`
`A.
`
`B.
`
`“system LSI” ....................................................................................... 14
`
`“a clock control library for controlling a clock frequency
`transition between said ordinary operation modes” ............................ 14
`
`“principal constituents of said central processing unit” ...................... 15
`
`D.
`
`Level of ordinary skill in the art .......................................................... 16
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`VI. GROUNDS OF REJECTION ....................................................................... 16
`
`A.
`
`Ground 1: Claims 1, 7, 10, and 11 are obvious over Ober and
`Nakazato. ............................................................................................. 16
`
`1.
`
`2.
`
`3.
`
`4.
`
`Overview: Ober discloses a “system LSI” with
`ordinary operation modes for adjusting CPU
`frequency and Nakazato discloses a system that
`adjusts CPU frequency using a “clock control library”
`and an “application.” ................................................................. 16
`
`Claim 1 ...................................................................................... 19
`
`Claim 7 ...................................................................................... 45
`
`Claims 10 and 11 ....................................................................... 50
`
`B.
`
`Ground 2: Claims 2-6 are obvious over Ober and Nakazato,
`
`Cooper and Windows ACPI. ............................................................... 51
`
`1.
`
`2.
`
`3.
`
`4.
`
`Overview: Ober and Nakazato disclose using a “clock
`control library” to control CPU frequency, and
`Cooper and Windows ACPI discloses using multiple
`clock control libraries and a main library. ................................ 51
`
`Claim 2 ...................................................................................... 57
`
`Claims 3 and 4 ........................................................................... 61
`
`Claim 5 and 6 ............................................................................ 62
`
`C.
`
`Ground 3: Ober in View of Nakazato, in further View of Doblar
`render claims 8 and 9 obvious ............................................................. 63
`
`1.
`
`2.
`
`3.
`
`Overview: Doblar discloses a clock generation circuit
`with a PLL that receives multiple standard clocks ................... 64
`
`Claim 8 ...................................................................................... 68
`
`Claim 9 ...................................................................................... 72
`
`VII. MANDATORY NOTICES ........................................................................... 73
`
`A.
`
`Real parties-in-interest ........................................................................ 73
`
`-11-
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`B.
`
`Notice of related matters ..................................................................... 74
`
`C.
`
`Lead and back—up counsel with service information .......................... 74
`
`VIII. GROUNDS FOR STANDING ...................................................................... 74
`
`IX.
`
`STATEMENT OF RELIEF REQUESTED ..................................................75
`
`X.
`
`CONCLUSION .............................................................................................. 75
`
`-iii-
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`EXHIBIT LIST
`
`
`
`
` Exhibit Description
`
`US. Patent No. 6,895,519 B2 to Endo (“the ’519 patent”)
`1001
`
`
`1002
`
`File history of US. Patent No. 6,895,519 B2 to Endo (“’519 file
`history”)
`
`Declaration of Dr. David Albonesi
`1003
`
`
`US. Patent No. 6,665,802 to Ober (“Ober”)
`1004
`
`
`1005
`
`“Draft ACPI Driver Interface Design Notes and Reference,”
`Microsoft Hardware White Paper, Microsoft Corporation, 1998
`
`(“Windows APCI”)
`
`US. Patent No. 6,516,422 to Doblar et al. (“Doblar”)
`1006
`
`
`1007
`“
`77
`US. Patent No. 6,823,516 to Cooper ( Cooper )
`
`
`
`
`
`
`1008
`t.
`a:
`US. Patent No. 6,681,336 to Nakazato et al. ( Nakazato )
`
`
`Curriculum vitae of Dr. David Albonesi
`1009
`
`
`McDaniel, G., IBM Dictionary of Computing, McGraw-Hill,
`1010
`10th ed., (1993) (“IBM Dictionary”)
`“Aquila Innovations, Inc.’s Claim Construction Brief,” Aquila
`Innovations, Inc. v. Advanced Micro Devices, Inc., Case No.
`
`1011
`
`1:18-cv-00554-LY (W.D. TeX.) (filed July 2, 2019). (“Claim
`
`Construction Brief”)
`
`1012
`
`1013
`
`“Aquila Innovations, Inc.’s Preliminary Infringement
`Contentions,” Aquila Innovations, Inc. v. Advanced Micro
`Devices, Inc., Case No. 1:18-cv-00554-LY (W.D. Tex.) (filed
`
`Feb. 3, 2019). (“Preliminary Infringement Contentions”)
`Compaq Computer Corporation et (11., “Advanced
`Configuration and Power Interface Specification, Revision 2.0”
`(July 27,2000) (“ACPIspec”)
`US. Patent No. 5,952,890 to Fallisgaard et al. (Fallisgaard)
`1014
`
`
`-lV-
`
`
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`
`Exhibit
`Description
`
`
`1015
`Intel Pentium 111 Processor/840 Developer Kit Manual (April
`
`2001) (“Intel Pentium 111 Manual”)
`
`1016
`TMS320C55X DSP Functional Overview (June 2000) (“TMS
`
`Overview”)
`
`1017
`ST7 8-Bit MCU Family User Guide (July 2002)(“ST7 User
`
`Guide)
`
`1018
`'cc
`7
`57
`US. Patent No. 7,155,617 B2 to Gary et al. ( the 617 patent )
`
`
`1019
`Microsoft Computer Dictionary, Microsoft Press, 5th ed.,
`
`(2002)(“Microsoft Dictionary”)
`
`MICROSOFTCOM, OnNow and Power Management (“OnNow”)
`1020
`
`
`Affidavit of Christopher Butler
`1021
`
`
`1022
`
`Olukotun et al., The Case for a Single-Chip Multiprocessor
`(1996)
`
`1023
`Albonesi et al., Tradeofi‘s in the Design of Single Chip
`
`Mttltiprocessors (1994)
`
`1024
`V
`.
`.
`.
`.
`Bossen et al, P0wer4 Systems: Design for Reliability (2001)
`
`
`1025
`a
`7
`US. Patent No. 5,260,979 to Parker et al. ( the 979 patent)
`
`
`
`
`
`
`1026
`
`7
`“
`-
`-
`US. Patent No. 5,530,726 to Toshiaki Ohno ( the 726 patent)
`
`Trevor Mudge, “Power: A First- Class Architectural Design
`1027
`Constraint,” IEEE Computer, April 2001
`
`
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`I.
`
`Introduction
`
`The Board should cancel all claims of the US. Patent No. 6,895,519 (“the
`
`’519 patent”), because they recite nothing more than combinations of well—known
`
`prior art. The ’519 patent is purportedly directed to a system “LSI” or large scale
`
`integration, capable of “executing the dynamic clock control from the side of an
`
`application program.” EXlOOl, ’519 Patent, 1: 6-10. But the ’519 patent admits
`
`that Virtually all of its claim elements were known, including dynamic clock
`
`control, special and normal operation modes, system LSIs, clock generation
`
`circuitry, and software control of dynamic clocks. EXlOO3, Albonesi Decl., ‘HSO-
`
`60; see also EX1001, 126-3218. And as demonstrated below, the remaining
`
`elements are simply insubstantial and well-known. Thus, for these reasons, the
`
`Board should cancel all claims of the ’519 patent.
`
`II.
`
`Identification of the Challenge
`
`AMD requests IPR on the grounds listed below. Per 37 C.F.R. § 42.6(0),
`
`copies of the references are filed with this petition, including the declaration of Dr.
`
`David Albonesi (EX1003) and his curriculum vitae (EX1009).
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`
`
`Grounds References
`‘
`Type
`Challenged Claims
`1
`Oberl and Nakazatoz
`‘
`§103
`1, 7, 10, and 11
`i
`2
`and Windows ACPI4
`|
`§103
`2-6
`Ober, Nakazato, Cooper3,
`
`3
`Ober, Nakazato, and Doblar5
`§103
`‘
`8 and 9
`
`
`
`
`
`III. The ’519 Patent
`
`A.
`
`The ’519 patent admits that most of its claimed elements were
`well-known, and arranged in the same manner as its claims.
`
`The ’5 l9 patent admits that many of the elements ultimately claimed were
`
`well-known in the prior art, and arranged similarly to the claims of the ’5 19 patent.
`
`According to the ’5 19 patent, there was a known desire in the art to reduce the
`
`amount of power used by mobile devices. EX1001, 126—20. To this end, the ’51 9
`
`patent explains that one known method of reducing power is by “gradually”
`
`changing the clock speed. 161., 1:20—26. One known microcontroller that performed
`
`
`1 Attached as EX1004.
`
`2 Attached as EX1008.
`
`3 Attached as EX1007.
`
`4 Attached as EX1005.
`
`5 Attached as EX1006.
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`such a method was the “ST Microelectronics” CPU ST7. Below, according to the
`
`’519 patent, is the “clock control circuit” of the ST7:
`
`FIGS
`
`
`I CLOCK I
`I
`OSCIILMING
`PORTION
`I FJLTER I roam“ I
`
`45
`
`
`
`
`
`
`
`
`
`
`IID ‘
`SWITCHING
`PORTION
`
`iPERIPHEFm:
`__ _ ,J_,a...
`I DEVICE
`'
`
`4:5
`
`EX1001, 1:39-42, FIG. 9.
`
`The ’519 admits, like its claims, that the prior-art ST7 clock control circuit
`
`also has a “clock frequency dividing portion 47,” which divides the frequency of
`
`the supplied clock prior to output. Id., 1:56-62.
`
`Importantly, the ’519 patent also admits that the ST7 included numerous
`
`“ordinary operation modes” that control the clock frequency of the CPU: “the ST7
`
`core operates at the frequency of 1/2 of the oscillation frequency in the high—speed
`
`operation mode. In the low-speed operation mode, it operates at the frequency of
`
`1/4, 1/8, 1/16, and 1/32 of the oscillation frequency .
`
`.
`
`.
`
`.” 1d,, 1265—222. Likewise,
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`the ’519 patent admits that “special operation modes” were known too. And even
`
`the Examiner agreed that the “special modes” were well known, taking official
`
`notice during prosecution: “Official Notice is taken that...[the] first, second and
`
`third special modes...are old and well known in the art.” EX1002,
`
`’519 file
`
`history, 357-358.
`
`The ’519 patent background concludes by admitting that the ST7 ordinary
`
`operation and special modes could also be controlled via software written in
`
`assembly: “it has been tried to dynamically control the clock from the application
`
`program side.” EXlOOl, 326-10. Thus, the ’519 concedes that a clock generation
`
`circuit that receives a plurality of clocks was known, ordinary operation modes
`
`were known, special modes were known, and software control of these modes was
`
`known, leaving only insignificant distinctions left in the claims of ’519 patent over
`
`the admitted prior art. And those insignificant distinctions were also known in the
`
`prior art.
`
`B.
`
`The ’519 specification’s alleged points of novelty are insignificant
`and well-known.
`
`As set forth above, the ’519 patent admits that much of its claimed subject
`
`matter was well-known.
`
`But according to the ’5 l9 patent, systems at the time of the invention
`
`suffered from two drawbacks that the ’5 l9 patent aimed to solve. First, there was a
`
`recent trend of collecting “common elements,” such as peripheral devices, and
`
`-4-
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`placing them on the same chip with the CPU in the form of an LSI (large scale
`
`integrated circuit). EX1001, 2:49-55. According to the ’519 patent, in “order to
`
`achieve a total power management” of such a chip, there was a need to be able to
`
`separately control the CPU and peripheral devices. Id., 2:56—60. Second, although
`
`software control via assembly language of the CPU frequency was known, the ’5 19
`
`patent contends this was subject to too “many restrictions from the point of View of
`
`the application program development.” 161., 3: 10-13. Accordingly, the ’5 19 patent
`
`alleges to solve this problem by “provid[ing] a flexible interface constituted by
`
`using the high-level program language like the C language.” Id., 3:13-16.
`
`But neither of these alleged problems were first solved by the ’5 19 patent.
`
`With respect to managing peripheral devices and the CPU separately, as Dr.
`
`Albonesi explains, and how the remainder of this Petition demonstrates, this was
`
`well-known in the art, prior to the earliest effective filing date of the ’519 patent.
`
`EX1003, ‘fl60. Moreover, the ’5 19 patent itself seemingly admits this was known in
`
`its disclosure of special modes. Id. With respect to programming software in the C-
`
`programming language instead of using assembly language to control a CPU, as
`
`Dr. Albonesi explains, this was commonly performed prior to the ’5 19 patent, and
`
`the ’5 19 patent itself even suggests that the “C language. . .is usually adopted in the
`
`current software development.” EX1001, 3: 13—16. Moreover, merely writing
`
`software as a “library” as claimed is not novel for the same reasons—it was well-
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`known and conventional by the time of the ’519 patent. 1d.; see also EXlOOZ, 357—
`
`358.
`
`IV. Asserted References
`
`1.
`
`Like the challenged claims of the ’5 19 patent, Ober discloses
`a System LSI with a clock generation circuit that receives a
`plurality of clocks and a system control circuit that can
`switch between ordinary operation modes and special
`operation modes Via a register.
`
`Like the ’519 patent, Ober discloses a “System LSI” in the form of a “System
`
`on Chip” (SOC), “which can be utilized. . .with different numbers of subsystems.”
`
`EX1004, Ober, 3:45-51. These subsystems and the other subsystems of Ober’s
`
`system LSI are shown below in Figure 1:
`
`
`
`
`DRAM Rairesh
`
`30
`
`
`
`
`I
`
`22
`
`
`
`
`
`
`
`
`
`4
`
`
`40
`
`Standard
`Peripheral
`JTAG
`50 I
`26
`
`App SEEM;
`Peripheral
`l
`JTAG
`J 52 I8
`
`DRAM Refresh
`
`
`
`
`
`HG‘I
`
`Main Crystal W
`
`NMI.FauItelr..
`
`EX1004, FIG. 1.
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`One subsystem in Ober is its “clock subsystem,” which “is used to generate
`
`a system clock signal as well as a management clock signa .” Id., 8:53-54. The
`
`clock subsystem is further shown below in annotated Figure 3 of Ober:
`
`System
`Clock
`
`Management
`Clock
`
`1/ 54
`
`Real ‘fime Clock
`
`Optional
`
`Km “plurality of
`
`standard clocks"
`
`EX1004, FIG. 3 (annotated).
`
`As can be seen, Ober’s clock generation circuit receives a “plurality of
`
`standard clocks” in the form of “[tlhe main crystal 84,” which is “for example, 15
`
`MHZ” and a “the 32 KHZ crystal 86.” Id, 8:58-9:3.
`
`Ober’s “system LSI” also includes “ordinary operation modes” and “special
`
`operation modes.” Specifically, Ober explicitly discloses changing CPU clock
`
`frequency by dividing the CPU clock. Id., 9:65-1022; EX1003, ‘][65. And Ober
`
`discloses several different configurable power modes and sub-modes (IDLE,
`
`SLEEP (Clock Distributed), and SLEEP (Clock Not Distributed)), which as
`
`-7-
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`explained in further detail below, correspond to claimed “Special operation
`
`modes.”
`
`2.
`
`Nakazato discloses “a clock control library” and an
`“application” for controlling CPU frequency.
`
`Like the ’519 patent and Ober, Nakazato relates to a system for setting
`
`processing speed. EX1008, Nakazato, 1:20-24. And similar to the ’5 l9 patent and
`
`Ober, Nakazato, as shown below in Figure l, discloses a “CPU speed control
`
`circuit 152” that “controls the processing speed of the CPU 11.” Id., 5 144-48.
`
`
`DRIVE
`
`CIRCUIT
`
`
`
`
`
`PCl—ISA BRIDGE
`
`152
`151
`
`
`CPU SPEED CONTROL CIHflllT
`
`
`[.2PU SPEED
`
`
`-HROTTLING .E‘ISERVILLEFU_CTIDN =UH-TION ‘
`
`VARIABLLSEWING
`
`
`
`
`ISA BUS
`
`FIG.'1
`
`EXlOOS, FIG. 1.
`
`One method that Nakazato discloses for adjusting CPU frequency is using a
`
`mechanism that Nakazato refers to as the “‘Geyserville’ function.” Id. Similar to
`
`Ober, when using the GeyserVille function, the CPU clock frequency can be
`
`switched by simply changing the value in a register. Id., 6: 19-21.
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`In Nakazato, the Geyserville register is controlled by a driver (i.e., a Clock
`
`control library). Id., 723-6. And the driver is controlled by a user application. Id.,
`
`7:6-8. Specifically, the user can select a “user-designated speed” (i.e. highest, high,
`
`middle, low, lowest) via an “application” as shown below in Figure 2:
`
`[PU SPEED SE'ITH'IE mm
`
`.—::PU SPEED—fl
`'r
`0mm SPEED
`
`OHJGHSPEEI]
`
`DmDDLESPEED
`
`
`
`
`@3me
`
`C) LflHEST SPEED
`
`DESIGMTED:
`._._..m III-I:
`
`| 1.
`
`FIG.2
`
`EX1008, FIG. 2.
`
`3.
`
`Cooper and Windows ACPI disclose a main library and a
`plurality of clock control libraries
`
`Like Ober and Nakazato, Cooper relates to setting processor clock speed.
`
`EX1007, Cooper, 1 27—10. And like Nakazato, Cooper describes that CPU clock
`
`control can occur using either a driver or SMI (system management interrupt). Id.,
`
`8:33—44. But Cooper suggests another way as well—Advanced Configuration and
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`Power Interface or “ACPI.” Id., 1:48-51. As Cooper explains, ACPI defines a
`
`standard interface for adjusting CPU clock frequency. Id., 1:54-56.
`
`With respect to Cooper’s ACPI implementation, numerous objects are used
`
`in conjunction with controlling CPU clock frequency. All of these ACPI objects
`
`together are then used to “control[] the system control circuit and the clock
`
`generation circuit as well to transit the clock state supplied to the central
`
`processing unit” like the “plurality of libraries” as described in the ’5 l9 patent. See
`
`EXlOOl, 4:30—37.
`
`The Windows Operating System (“OS”) was the most popular OS around
`
`the time of the purported invention. EX1003, W172, 174. If a POSITA were to
`
`develop hardware for use with ACPI and the Windows OS,
`
`they would have
`
`looked to the Windows ACPI document.
`
`Id. Specifically, Windows ACPI
`
`describes how to develop drivers compatible with ACPI and the Windows OS.
`
`EXlOl3, ACPIspec, 00017. Windows ACPI explains that like the claimed “main
`
`library,” the Windows ACPI driver allows other software to control functions of
`
`ACPI. That is, when using ACPI with the Windows OS, the Windows ACPI driver
`
`(the main library) allows other software to load and control the same types of
`
`objects described in Cooper (the plurality of libraries). EX1003, ‘][‘][72, 176.
`
`-10-
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`4.
`
`Doblar discloses a PLL that receives a plurality of clock
`signals and then multiplies them
`
`Doblar is concerned that failure of a system clock may “disable the entire
`
`system.” EX1006, Doblar, 1:36-37. Doblar solution to this problem is to provide
`
`two clocks. Id., 1:37-39.
`
`Doblar’s PLL circuit is shown below in Figure 4:
`
`PLLiEN
`
`SELECT E
`PLLfl lI
`
`lI
`
`COM IROL
`432
`I'NPUT CLOCKS
`
`IDS
`
`
`.
`
`SWITCHING
`LOGIC
`
`SEL_CLI(
`OUTPUT
`
`| SlG NALS
`l
`420MB
`
`.3
`
`106A .
`
`PHASE
`.
`
`DETECTOR 1
`
`
`
`
`:
`
`
`
`\ FEEDBACK SIGNAL
`4215
`
`FIG. 4
`
`EX1006, FIG. 4.
`
`As can be seen, Doblar’s PLL receives multiple standard clocks in the form
`
`of clock sources 106A and 106B. Id., 6:19—23. These clocks differ from each other
`
`by an integer multiple. See id., 3:35-39. The “select clock input” sets the identity of
`
`which of the clock signals (e.g. 106A or 106B) is the primary clock input. Id.,
`
`6:26-27. As a result of this process, “[u]pon a failure of one of the clock signals
`
`106A or 106B .
`
`.
`
`.
`
`, the system controller .
`
`.
`
`. switches in the other clock signal,
`
`-1]-
`
`

`

`Inter Partes Review of US. Patent No. 6,895,519 32
`
`106A, 106B, previously serving as the slave clock signal, as the new master clock
`
`signal.” Id., 3:39-43.
`
`5.
`
`Ober, Nakazato, Cooper, Windows ACPI, and Doblar are
`prior art.
`
`Ober, Nakazato, Cooper, and Doblar are prior art to the ’5 19 patent. As
`
`shown in the table below, each reference qualifies as prior art under 35 U.S.C. §
`
`102(e), because the references were filed prior to the earliest possible effective
`
`filing date of the ’5 19 patent—February 15, 2002—the filing date of Japanese
`
`Parent Application JP 2002—047696.
`
`
`Reference
`
`Prior-Art Date
`
`
`
`U.S.P. 6,665,802 to Ober Filed February 29, 2000
`
`
`
`U.S.P. 6,681,336 to Nakazato Filed June 16, 2000
`
`U.S.P. 6,516,422 to Doblar
`
` Filed May 27, 1999 U.S.P 6,456,135 to Cooper
`
`
`
`
`
`Filed August 10, 1999
`
`Windows ACPI is prior art under 35 U.S.C § 102(b), because it was
`
`published at least as early as May 4,1999, which is more than 1 year prior to the
`
`effective filing date of the ’519 patent. Specifically, the Internet Archive Wayback
`
`machine captured the Window ACPI document itself as of May 4, 1999 from the
`
`Microsoft.com website. EX1005, Windows ACPI; see also EX1021, Affidavit of
`
`Christopher Butler. At the time of the invention, the Windows OS was by far the
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`Inter Partes Review of US. Patent No. 6,895,519 32
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`most popular OS available. And thus, a POSITA or the interested public seeking
`
`information on how to integrate power management, such as disclosed in the ’5 19
`
`patent, Ober, Nakazato, Cooper, or Doblar, with the Windows OS would certainly
`
`have known to look at the hardware development section of the Microsoftcom
`
`website for information on how to do this. EX1003, ‘][43.
`
`V.
`
`Claim Construction
`
`The claim construction standard set forth in Phillips v. AWH Corp., 415 F.3d
`
`1303 (Fed. Cir. 2005) applies to this proceeding. 83 Fed. Reg. No. 197, 51341
`
`(Oct. 11, 2018); 37 C.F.R. 42.100(b).
`
`At this time in the proceeding, AMD contends that the terms in the
`
`following sections require construction.6 The remaining terms need only be given
`
`their plain and ordinary meaning for the purposes of this proceeding.
`
`6 AMD’s proposed constructions, or lack thereof, for the purpose of this
`
`proceeding are not an admission that the claims are valid under §112. AMD
`
`reserves the right to challenge the validity of the claims under §112 in other
`
`proceedings and forums.
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`Inter Partes Review of US. Patent No. 6,895,519 32
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`A.
`
`“system LSI”
`
`The proper construction of the term “system LSI” is a “single integrated
`
`chip, which has a CPU memory, and I/O capability.” This construction is
`
`consistent with the claims and the specification of the ’5 19 patent.
`
`Specifically, claim 1—the sole independent claim in the ’519 patent——
`
`explicitly recites that the “system LSI” includes “a first memory” and a “second
`
`memory.” And although the preamble of claim 1 does not explicitly state that that
`
`the “system LSI” includes “a central processing unit,” a POSITA would have
`
`nonetheless understood that the “system LSI” includes the central processing unit,
`
`memories, and I/O capability. EX1003, fl[77.
`
`This is further confirmed by the ’5 l9 patent’s specification itself, which
`
`repeatedly confirms that the “system LSI” includes memory, a CPU, and I/O
`
`capability. See EXlOOl, FIG. 2, see also 5:58-61, 12:34-37.
`
`B.
`
`“a clock control library for controlling a clock frequency
`transition between said ordinary operation modes”
`
`AMD contended in the co—pending district court proceeding that this term
`
`should be interpreted under 35 U.S.C. § 112, para. 6. EXlOl 1, Joint Claim
`
`Construction Brief, 14. The function is: controlling a clock frequency transition
`
`(that is not a state transition) between said ordinary operation modes. Id. However,
`
`AMD also contended in the co—pending district court proceeding that there is
`
`insufficient structure for this term, and thus it is indefinite under 35 U.S.C. § 112.
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`Inter Partes Review of US. Patent No. 6,895,519 32
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`Id. Given that AMD cannot raise indefiniteness challenges in this proceeding,
`
`solely for the purposes of this proceeding, AMD adopts Patent Owner’s
`
`construction of this term from the district court proceeding, which is “software that
`
`controls the change in the frequency of the clock signals in the ordinary operation
`
`modes.” Id., 7. As shown below, the prior art teaches the claimed “clock control
`
`library” under Aquila’s construction because it discloses “software that controls
`
`the change in the frequency of the clock signals in the ordinary operation modes.”
`
`Id.
`
`C.
`
`“principal constituents of said central processing unit”
`
`The proper construction for this term is “the processor cores but not
`
`circuitry responsible for responding to inputs, such as peripheral devices, or
`
`interrupts.” Both AMD and Aquila agree that “principal constituents” at least
`
`involves “processor cores.” See EXlOl 1, 13. And Dr. Albonesi explains that the
`
`’519 patent explicitly excludes the ’5 19 patent’s circuitry responsible for
`
`responding to inputs and interrupts from being part of the principle constituents.
`
`EX1003, ‘][84;EX1001, 10:31—45.
`
`Thus, AMD’s construction is consistent with the specification, which
`
`discloses that the “principal constituents” of the CPU include the processor cores
`
`but not circuitry responsible for responding to inputs (e. g., peripheral devices), or
`
`interrupts. EX1003, [][84.
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`Inter Partes Review of US. Patent No. 6,895,519 32
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`D.
`
`Level of ordinary skill in the art
`
`A person of ordinary skill in the art (“POSITA”) would have a BS. degree
`
`in Electrical Engineering, Computer Engineering, or an equivalent field as well as
`
`at least 3 to 5 years of academic or industry experience in computer systems
`
`architecture or computer chip design, or comparable industry experience.
`
`VI. Grounds of Rejection
`
`Claims 1—11 are unpatentable based on the following grounds: (1) claims 1,
`
`7, 10, and 11 are obvious over Ober and Nakazato; (2) claims 2-6 are obvious over
`
`Ober in View of Nakazato, and in further View of Cooper and Windows ACPI; and
`
`(3) claims 8 and 9 are obvious over Ober in View of Nakazato, and in further View
`
`of Doblar.
`
`A.
`
`Ground 1: Claims 1, 7, 10, and 11 are obvious over Ober and
`Nakazato.
`
`The combination of Ober and Nakazato teaches or suggests every element of
`
`claims 1, 7, 10, and 11.
`
`1.
`
`Overview: Ober discloses a “system LSI” with ordinary
`operation modes for adjusting CPU frequency and
`Nakazato discloses a system that adjusts CPU frequency
`using a “clock control library” and an “application.”
`
`As explained above, Ober discloses a “system LSI” having a plurality of
`
`“ordinary operation modes,” “special operating modes,” and a “clock generation
`
`circuit” that receives a “plurality of standard clocks.” See Section IV.1. Ober
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`Inter Partes Review of US. Patent No. 6,895,519 32
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`further discloses a “system control circuit” that has a register that when changed,
`
`can switch between the “ordinary modes” and “special modes.” See id.
`
`With respect to switching among “ordinary modes,” Ober explains that it
`
`can adjust the frequency of the system clock during either sleep mode or “normal
`
`mode.” EX1004, 9:65-10:2; EX1003, ‘][87.
`
`While Ober goes into some detail as to how the clock is divided during
`
`SLEEP mode, Ober does not explicitly describe how it occurs during “normal
`
`mode.” EX1003, ‘][88. But it would have been obvious to a POSITA that the clock
`
`could be adjusted during “normal mode” similarly to how it is adjusted during
`
`“SLEEP mode”— by allowing software to adjust a field in a register. 1d. But
`
`beyond that, a POSITA would be forced to seek out details as to how and under
`
`what circumstances software would cause the CPU speed to be reduced. Id. Thus, a
`
`POSITA looking to implement the teachings of Ober would need to understand the
`
`circumstances under which the CPU speed would be reduced, while a computer is
`
`normally operating, and how such a system would control the CPU speed. Id. This
`
`would motivate a POSITA to seek out references that disclosed such techniques,
`
`and Nakazato is one such reference. Id.
`
`Nakazato discloses a “CPU speed control circuit 152” that “controls the
`
`processing speed of the CPU 11, and has a throttling controller for switching the
`
`CPU speed.” EX1008, 5:44-49.
`
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`Inter Partes Review of US. Patent No. 6,895,519 32
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`Like Ober, Nakazato discloses, “the CPU speed can be switched by writing
`
`necessary data in the internal register of the CPU speed control circuit 152.” Id.,
`
`6: 19-21. This writing of data, according to an embodiment of Nakazato, is
`
`controlled by a driver (i.e., a clock control library) installed in the OS of the
`
`computer. Id., 7:3-6. And the power-saving driver sets the processing speed of the
`
`CPU based on a user application, which allows for user—selection of processing
`
`speed. Id., 7:6-8; 7:19-24.
`
`A POSITA would have found it obvious to combine Ober and Nakazato for
`
`several reasons. First, both Ober and Nakazato explicitly relate to managing the
`
`power of a computing system. EXlOO3, ‘][91. Moreover, both Ober and Nakazato
`
`describe managing the power by adjusting the frequency of the CPU. Id. In
`
`addition, combining Ober and Nakazato would be nothing more than combining
`
`prior-art elements according to known methods to yield predictable results. Id. In
`
`particular, Ober and Nakazato both teach or suggest adjusting the frequency of
`
`their respective CPUs by changing the value in a register. Id. Thus, combining
`
`Ober and Nakazato would yield predictable results, because Nakazato’s driver and
`
`utility would merely be executed from Ober’s memory banks to adjust Ober’s CPU
`
`clock control register, resulting in an integrated system for adjusting CPU clock
`
`speed. Id. This would result in a reasonable expectation of success because
`
`Nakazato’s software is already described as modifying registers to change a CPU
`
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`Inter Partes Review of US. Patent No. 6,895,519 32
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`clock frequency and Ober’s system includes registers to change CPU clock
`
`frequency. Id.; see also KSR Int’l v. Teleflex Inc, 550 US. 398, 417 (2007).
`
`2.
`
`Claim 1
`
`The combination of Ober and Nakazato teaches or suggests every element of
`
`claim 1.
`
`
`1. A system LS1 having a plurality of ordinary operation modes and a plurality
`
`of special modes in response to clock frequencies supplied to a central
`
`processing unit, comprising
`
`
`Ober discloses a “system LSI” in the form of “a microcontroller or System
`
`on Chip (SOC) which can be utilized. . .with different numbers of subsystems.”
`
`EX1004, 3:45 -51. As explained above, the term “system LS1,” when properly
`
`construed is a “a “single integrated chip, which has a CPU, a memory, and I/O
`
`capability.” A “System on Chip” or SOC is a well-known example of a single
`
`integrated chip. EX1003, fl[93.
`
`Ober further explains that its SOC includes various subsystems such as
`
`“input/output (I/O) ports 30” and “memory banks 54 and 56.” EX1004, 5:41-53.
`
`These subsystems, along with the other subsystems of Ober’s system LS1 are
`
`shown below in Figure l:
`
`-19-
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`Inter Partes Review of US. Patent No. 6,895,519 32
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`Ober’s SOC also includes a “central processing unit” (“CPU”) as the term is
`
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