||l|l||II|||I|lllllllllllllllllllllll||||l||||ll|l|||||l|llllllllllllllllll
`U5005260979A
`5,260,979
`{11] Patent Number:
`{19]
`United States Patent
`
`Parker et a].
`{45] Date of Patent:
`Nov. 9, 1993
`
`[75]
`
`[54] CIRCUIT AND METHOD OF SWITCHING
`BETWEEN REDUNDANT CLOCKS FOR A
`PHASE LOCK LOOP
`Inventors: Lanny L. Parker, Mesa; Ahmad H.
`Atriss, Chandler, both of Aria; Dean
`W. Mueller, Portland, Oreg.
`[73] ASSiBT‘E'?‘ Codex 00"?" Marni-"31¢ ”355-
`[2]] Appl. No.: 705.351
`
`May 28» I?”
`F1193?
`[22]
`Int. CT.s ............................................... HML T/oo
`{51]
`[52] US. Cl. ____________________________________ 375/103; 375/120;
`331/13; 331 ,125; 371/211; 371 1'31
`[53] Field of Search ___________________ 331/7, 11, 13, 49’ 25;
`371 /68.1, 7’ 31‘ 24‘ 22.1, 411, 67.1, 5, 52;
`375/31, 32’ 103, 119, 120, 113
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4.144.443
`3/1979 Pisciotta et al.
`...................... 371/62
`4.392.226 7/1933 Cook .................
`
`31'1/62
`
`4.718.339
`1/1938 Ht‘inig eT a].
`..
`” 371/62
`4.908.841
`3/1990 Leis et a].
`......
`
`T... 375/31
`4.918.404 4/ 1990 Vitiello et al.
`........................ 331/11
`
`4364,11? 10/1990 Shier ................................... 375/120
`4,912.4“ 11/1990 Steierman ........................... 375/120
`Primary Examiner—Stephen Chill
`Assistant Examiner—Don N- V0
`Attorney, Agent, or Firm—Robert D. Atkins
`{57]
`ABSTRACT
`A phase lock 100p monitors the frequency of redundant
`input clock signals and switches back and forth therebe-
`tween should one or the other become invalid. Thus,
`the PLL may continue normal operation even with a
`failure of one input clock signal- If both the input clock
`signals fail, an internal reference signal maintains the
`PLL at a nominal operating frequency until one of the
`input clock signals is restored whereby the loop can
`quickly re-establish phase lock. To determined validity,
`the input clock signals are sampled and stored by the
`reference signal in a predetermined manner. The input
`clock signal is valid if the samples of the input clock
`signal each have the same logic state after the sampling
`Pemd‘ Otherw‘se’ the mpmdo‘i Signalismmid ”the
`samples of the input clock signal have at least one differ—
`ent logic state after the sampling period.
`
`18 Claims, 8 Drawing Sheets
`
`REFCLK1 -
`REFCLK2 . - MULTIPLEXER
`
`UP
`PHASE
`DETECTOR DOWN
`
`36
`
`I “Siéigfi
`
`DETECT
`
`LOCK DETECTOR
`AND FLOAT
`CIRCUIT
`
`:n
`a."n,—x
`,n—iH
`
`
`
`an:m 31111:”111333!
`
`EMU!"N1338
`
`MULTIPLEXER
`
`REDUNDANT
`CLOCK
`SELECTOR
`
`BY 1.!
`
`101mm
`
`minions
`
`DIVIDE
`BY N
`
`DIVIDE
`
`0001
`0001
`
`AMD EX1025
`AMD EX1025
`U.S. Patent No. 6,895,519
`US. Patent No. 6,895,519
`
`

`

`US. Patent
`
`m
`
`a
`
`8
`
`5,260,979
`
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`on,5.83
`No128.5953
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`
`REFCLKI ACTIVE
`
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`
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`
`0002
`0002
`
`

`

`US. Patent
`
`Nov. 9, 1993
`
`Sheet 2 of 3
`
`5,260,979
`
`FROM
`STEP 70
`FIG.
`3
`
`FROM
`STEP 84
`FIG. 3
`
`T0
`STEP 70
`FIG.
`3
`
`56
`
`POWER ON
`
`50
`
`APPLY RC_CLK 52
`T0 PLL
`
`NO
`
`54
`
`YES
`
`SELECT REFCLK1 AND
`ACHIEVE PHASE LOCK
`
`
`
`
`YES
`
`2
`
`FLOAT VCO
`
`
` REFCLK1
`
`REFCLK1
`QUICK
`PHASE
`
`
`
`RECOVERY
`LOCKED
`
`
` 64
`
`N0
`
`.Z7illC3F-
`
`.2?
`
`0003
`0003
`
`

`

`US. Patent
`
`Nov. 9, 1993
`
`Sheet 3 of 8
`
`5,260,979
`
`FROM STEP 54
`FIG. 2
`
`
`
`
`T0
`STEP 52
`FIG. 2
`
`72
`
`
`
`
`
`
`
`
`
`
`REFCLKZ
`QUICK
`RECOVERY
`
`REFCLKZ
`PHASE
`
`LOCKED
`
`
`80
`
`. FIG. 3
`
`0004
`0004
`
`

`

`US. Patent
`
`Nov. 9, 1993
`
`Sheet 4 of 8
`
`5,260,979
`
`nfiE.w6%th:0mm“$223-2.
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`REFCLKI TIMER
`
`
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`Emu:35.8
`
`0005
`0005
`
`
`
`
`
`
`
`
`

`

`US. Patent
`
`Nov. 9, 1993
`
`Sheet 5 of8
`
`5,260,979
`
`Ir ----------------- qI
`l
`130
`126
`132
`I
`:
`'
`
`
`
`REFCLK1
`
`REFCLK‘
`
`
`
`: I I I I I I i J
`
`
`REFCLK1
`120
`122
`I
`90.
`L ————————————————— J
`
`FIG. 5
`
`144
`
`FIG. 6
`
` - RC_CLK
`
`
`
`. CLK_A
`
`- CLKHB
`
`NON-OVERLAPPING
`CLOCK GENERATOR
`
`150
`
`0006
`0006
`
`

`

`
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`a:anI.as“as:
`
`w-0y.A.:5:an:
`
`0007
`0007
`
`
`

`

`US. Patent
`
`Nov. 9, 1993
`
`Sheet 7 0“!
`
`5,260,979
`
`REFCLK1_ERROR '
`
`0 REFCLK1_FAIL
`
`
`
`.REFCLK1SELECT
`
`
`
`278
`
`266
`
`264
`
`
`
`REFCLK1DIV
`
`0008
`0008
`
`FIG. 8
`
`

`

`U.S. Patent
`
`Nov. 9, 1993
`
`Sheet 8 of 8
`
`5,260,979
`
`236
`
`
`
` DATA
`
`SHIFT REGISTER
`
`RESETflFLOAT
`
`
`
`
`
`RESET_FDET
`
`
`RC_CLK_ACTIVE
`
`T
`
`236
`
`UP
`
`FLOAT
`
`DOWN
`
`238
`
`0009
`0009
`
`

`

`1
`
`5,260,979
`
`2
`PLL remain operational even if the primary input clock
`signal becomes invalid as a reference.
`Hence, what is needed is an improved phase lock
`loop which re-establishes Operation should the primary
`input clock signal become invalid.
`SUMMARY OF THE INVENTION
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`Briefly stated, the invention comprises a method of
`selecting between first and second input clock signals
`applied to a phase lock loop (PLL) comprising the steps
`of checking validity of the first input clock signal by
`counting pulses of a first reference signal during first
`and second states of one period of the first input clock
`signal and locking the PLL to the first input clock sig-
`nal if valid as indicated by a predetermined number of
`pulses of the reference signal occurring during the first
`and second states of the one period of the first input
`clock signal, switching to the second input clock signal
`if the first
`input clock signal becomes invalid, and
`checking validity of the second input clock signal by
`counting pulses of a second reference signal during first
`and second states of one period of the second input
`clock signal and locking the PLL to the second input
`clock if valid.
`
`In another aspect, the present invention is a phase
`lock loop (PLL) responsive to a first digital signal for
`generating a second digital signal operating substan-
`tially at frequency and in-phase with the first digital
`signal. A first circuit is responsive to first and second
`control signals for selecting between first and second
`input clock signals respectively applied at first and sec-
`ond inputs thereof for providing the first digital signal
`of the PLL at an output, while a second circuit monitors
`the validity of the first and second input clock signals
`and activating the first control signal when the first
`input clock signal
`is valid and activating the second
`control signal when the first input clock signal is in-
`valid.
`
`Thus, one advantage of the present invention is the
`technique of monitoring the input clock signal and sub-
`stituting a redundant clock signal therefor should the
`primary input clock signal become invalid. If both the
`primary and redundant input clock signals fail, an inter-
`nal oscillator maintains the PLL at nominal operating
`frequency until one of the input clock signal is restored
`whereby the loop can quickly reestablish phase lock.
`BRIEF DESCRIPTION OF THE DRAWING
`
`FIG. I is a simplified block diagram illustrating a
`phase lock loop with redundant input clocks;
`FIGS. 2 and 3 is a flow chart illustrating a method of
`switching between redundant input clocks;
`FIG. 4 is a simplified block diagram illustrating the
`redundant clock selector of FIG. 1;
`FIG. 5 is a schematic diagram illustrating the non-
`ovet’lapping clock generator of FIG. 4;
`FIG. 6 is a schematic diagram illustrating the RC
`oscillator circuit of FIG. 4;
`FIG. 7 is a schematic and block diagram illustrating
`the valid clock selector of FIG. 4;
`FIG. 8 is a schematic diagram illustrating the clock
`detector of FIG. 4;
`FIG. 9 is a schematic and block diagram illustrating
`the lock detector and float circuit of FIG. I; and
`FIG. 10 is a schematic diagram illustrating the charge
`pump circuit of FIG. 1.
`
`CIRCUIT AND METHOD OF SWITCHING
`BETWEEN REDUNDANI CLOCKS FOR A PHASE
`LOCK LOOP
`
`CROSS REFERENCE TO RELATED PATENT
`APPLICATIONS
`
`This application is related to copending US. patent
`application Ser. No. Oil/695,118, Attorney’s Docket
`CX07235, entitled “LOCK DETECTION FOR A
`PHASE LOCK LOOP”, filed May, 3, 1991 which are
`now abandoned, by Lanny Parker et al and assigned to
`the same assignee, Codex, Corp. This application is
`further related to copending U.S. patent application
`Ser. No. 07/705,862. Attorney’s Docket CX07236, enti-
`tled “CIRCUIT AND METHOD OF DETECTING
`AN INVALID CLOCK SIGNAL", filed May, 28,
`1991 Which are now US. Pat. No. 5.161.175. by Lanny
`Parker et al and assigned to the same assignee, Codex,
`Corp.
`
`FIELD OF THE INVENTION
`
`This inventiori relates in general to phase lock loops
`and, more particularly, to a phase lock loop capable of
`switching between redundant input clock signals.
`BACKGROUND OF THE INVENTION
`
`Phase lock loops (PLL) are found in a myriad of
`electronic applications. such as communication receiv-
`ers and clock synchronization circuits in computer sys-
`tems, for pr0viding a reference signal with a known
`phase for clocking incoming and out-going data. A
`conventional PLL comprises a phase detector for moni»
`toring the phase difference between an input clock sig-
`nal and the output signal of a voltage controlled oscilla-
`tor (VCO) and generating an UP coritrol signal and 3
`DOWN control signal for a charge pump circuit which
`charges and discharges a loop filter at the input of the
`VCO. The UP and DOWN control signals drive the
`VCO to maintain a predetermined phase relationship
`between signals applied to the phase detector. as is well
`understood.
`
`The output signal of the PLL must maintain a prede-
`termined frequency of operation to be useful as a refer-
`ence for clocking the incoming and outgoing data. If
`the frequency of the input clock signal should drift, or
`even change to a radically different rate, the output
`signal of the VCO follows along and attempts to re-
`achieve phase lock thereto. Such behavior is inherent in
`the operation of the PLL. Many prior art systems have
`ways of detecting and reporting a momentary loss of
`phase lock. Yet, most if not all conventional phase lock
`indicators cannot distinguish the input
`frequency.
`Therefore, the output signal of the VCO locks to the
`new, albeit incorrect, frequency of the input clock sig-
`nal and the lock indicator again reports a valid phase
`lock status. The reference signal thus clocks the incom-
`ing and out-going data at the wrong points resulting in
`errOneous communication.
`The input clock signal may also become stuck-at-one
`or stuck-at-zero causing the PLL to permanently lose
`phase lock. Since the PLL cannot lock to a DC signal,
`the lock indicator suspends the system operation. While
`it is informative to know of the permanent loss of phase
`lock,
`the phase lock indicator does nothing toward
`restoring operation of the system which may remain
`down until the input clock signal is repaired. In many
`applications, it is desirable and even imperative that the
`
`0010
`0010
`
`

`

`3
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`5,260,979
`
`4
`Charge pump 18 is responsive to the UP control signal
`and the DOWN control signal for charging and dis-
`charging loop node 20 under the influence of loop filter
`22. The voltage developed at loop node 20 drives VCO
`24 to generate the 24 MHz oscillator signal which is
`divided down by divide-by-N circuit 30, or divide-by-
`M circuit 32, for providing the OSCOUT signal at the
`second input of phase detector 16. Thus, phase detector
`16 monitors the phase difference between the REFCLK
`clock signal and the OSCOUT signal and generates UP
`and DOWN control signals as necessary for charge
`pump 18 to drive 100p node 20 and VCO 24 to maintain
`the predetermined phase relationship between the
`REFCLK and OSCOUT signals.
`PLL 10 also includes phase monitor 36 responsive to
`the REFCLK clock signal and the OSCOUT signal for
`comparing the phasa difference and generating a true
`DETECT signal if the phase difference occurs within a
`predetermined TIMESLOT window as established by
`divide-bynN circuit 30. The DETECT signal is false if
`the phase difference between the REFCLK and
`OSCOUT signals extends beyond the TIMESLOT
`window. The operation ofphase monitor 36 and divide-
`by-N circuit 30 is described in the copending patent
`application entitled “LOCK DETECTION FOR A
`PHASE LOCK LOOP“ as noted in the cross reference
`to related patent applications. The TIMESLOT signal
`operates at twice the frequency of the OSCOUT signal
`with its low state centered about the transitions of the
`OSCOUT signal. The low state of the TIMESLOT
`signal defines the TIMESLOT window having a dura-
`tion of say 20 nanoseconds compared to the overall
`period of the REFCLK clock signal of 250 nanosec—
`onds. The SAMPLE_CI.0CK signal Operates at the
`same frequency as the TIMESLOT signal with a posi-
`tive pulse just prior to the falling edge of the TIMES-
`LOT signal.
`Lock detector and float circuit 38 counts a predeter-
`mined number of repetitive true DETECT signals and
`generates a LOCK signal indicating PLL 10 is phase
`locked. The FLOAT signal from lock detector and
`float circuit 38 disables charge pump 18 immediately
`upon losing the input clock signal to maintain loop node
`20 stationary until the redundant input clock can take
`over.
`
`A key feature is the ability to detect the validity of the
`REFCLKI clock signal and the REFCLK2 clock sig-
`nal and route one or the other to phase detector 16 to
`maintain the operation of PLL II]. Thus,
`if the
`REFCLK] clock signal becomes invalid, such an oc-
`currence is detected by redundant clock selector 14 and
`the REFCLKz clock signal
`is promptly substituted
`therefor to allow continued operation of PLL 10. Since
`the external circuitry (not shown) generating the
`REFCLKI clock signal is separate and distinct from
`that generating the REFCLKZ clock signal. the likeli-
`hood of both REFCLKI and REFCLKZ clock signals
`becoming invalid at the same time is relatively low.
`However,
`should
`such
`a
`condition occur,
`the
`RC_CLK clock signal is routed through multiplexer 12
`to phase detector 16 for maintaining a nominal voltage
`at loop node 20 in the vicinity of that needed for the 24
`MHz oscillator signal from VCO 24 such that if and
`when the REFCLK! and/or REFCLKZ clock signals
`return, PLL 10 can re-achieve phase lock as rapidly as
`possible. The RC_CLK clock signal
`is generated lo»
`cally on chip and, therefore, known to be good, stable
`and very reliable. There is a high probability that at
`
`A phase lock loop (PLL) 10 in accordance with the
`present invention is shown in FIG. 1 suitable for manu-
`facturing as an integrated circuit using conventional
`integrated circuit processes. One usage for PLL 10 is in
`a communication system such as a telecommunications
`network manager. A primary REFCLK] input clock
`signal and a redundant REFCLKZ input clock signal
`are applied at first and second inputs of multiplexer 12
`and to first and second inputs of redunth clock selec-
`tor 14, the latter of which provides an RC..CLK refer-
`ence clock signal to the third input of multiplexer 12
`and control signals REFCLKIJCTIVE. REFCL-
`K.2__ACTIVE and RC_CLK_ACTIVE for control-
`ling multiplexer 12. The REFCLK! and REFCLK2
`clock signals operate at the same frequency, say about
`four megahertz (MHZ), although not necessarily in-
`phase. The RC_CLK clock signal is generated in re-
`dundant clock selector 14 and cycles at approximately
`500 kilo-hertz (KHz) $2096.
`The REFCLK1._ACTIVE, REFCLK2_ACTIVE
`and RC_CLK_ACTIVE control signals are mutually
`exclusive in that only one is asserted at a time for pass-
`ing one of
`the input clock signals REFCLK],
`REFCLKZ or RC_CLK through multiplexer 12 to the
`first input of phase detector 16. The REFCLKI clock
`signal is routed through multiplexer 12 becoming the
`REFCLK clock signal to phase detector 16 when the
`REFCLKI..ACTIVE signal
`is asserted. Alternately,
`the REFCLKZ clock signal
`is passed through as the
`REFCLK clock signal when the REFCLK2_AC~
`TIVE signal is active, while the RC_CLK_ACTIVE
`signal enables the RCECLK clock signal to become the
`REFCLK clock signal.
`The REFCLK clock signal applied at the first input
`of phase detector 16 generates an UP control signal and
`a DOWN control signal for charge pump 18 which
`charges and discharges loop node 20. Loop filter 22
`may comprise a capacitor (not shown) coupled between
`loop node 20 and ground potential. The voltage at loop
`node 20 controls VCO 24 for generating an oscillator
`signal at output 26 operating at say 24 MHZ. The VCO
`oscillator signal is divided through divide-by-N circuit
`30 in one path and through divide-by-M circuit 32 in
`another path for providing an OSCOUT signal at the
`output of multiplexer 34. The RC_CLK..ACTIVE
`signal controls multiplexer 34 for selecting the proper
`division of the VCO oscillator signal at the second input
`of phase detector 16 to lock to the 4 MHz REFCLKI-
`IREFCLKZ clock signal, or the 500 KHz RC_CLK
`clock signal. A typical value for “N“ is six to match
`with the 4 MHZ REFCLKI and REFCLKZ clock sig-
`nals, while “M" is set to forty-eight for aligning with
`the 500 KHz RC_CLK clock signal.
`The Operation of PLL 10 proceeds as f0110ws. The
`REFCLK clock signal applied at the first input of phase
`detector 16 in combination with the OSCOUT signal
`applied at the second input of the same generates an UP
`control signal, or 3 DOWN control signal, according to
`the phase relationship therebetween. The UP control
`signal pulses if the OSCOUT signal lags the REFCLK.
`clock signal, i.e, the frequency of the OSCOUT signal is
`too low relative to the REFCLK clock signal. Alter-
`nately, the DOWN control signal pulses to reduce the
`frequency of the oscillator signal from VCO 24 if the
`OSCOUT signal
`leads the REFCLK clock signal.
`
`ll}
`
`15
`
`20
`
`25
`
`3D
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`0011
`0011
`
`

`

`5
`least one of the three input clock signals is operating to
`drive PLL 1|].
`
`Before preceding with a detailed description of the
`circuit structure of PLL 10, it may be helpful to under-
`stand the logical
`steps of selecting between the
`REFCLKI clock signal, the REFCLK2 clock signal
`and the RC_CLK clock signal during the Operation of
`PLL 10. Referring to FIG. 2,
`the selection process
`begins with POWER ON step 50 where system power
`is initially applied to PLL 10, or system reset is actu-
`ated. At system reset, APPLY RC._CLK TO PLL step
`52 routes the RC_CLK clock signal through multi-
`plexer l2 and allows PLL 10 to train thereto. That is,
`the voltage at loop node 20 moves to a nominal value
`close to that needed for the REFCLKI and REFCLK2
`clock signals. CHECK REFCLKI step 54 determines
`the validity of the REFCLKl clock signal and precedes
`to SELECT REFCLK] AND ACHIEVE PHASE
`LOCK step 56 for a valid REFCLK] clock signal. The
`REFCLKI clock signal is routed through multiplexer
`12 allowing I’LL 18 to lock thereto and begin normal
`operation.
`CHECK REFCLKI step 60 continuously monitors
`the REFCLKI clock signal until an invalid status is
`detected at which time FLOAT VCO step 62 disables
`charge pump 18 to maintain loop node 20 in a floating
`condition.
`If the REFCLK] clock signal
`recovers
`quickly, say in less than seven RC_CLK cycles,
`REFCLK] QUICK RECOVERY step 64 verifies the
`recovery of the REFCLKI clock signal and proceeds
`to REFCLK! PHASE LOCKED step 66 which re-
`turns the loop to CHECK REFCLKI step 60 ifPLL 10
`is still phase locked with the REFCLK] clock signal.
`The logic assumes that by floating loop node 20, VCO
`24 keeps operating at substantially the same frequency
`for at least seven periods of the RC_CLK clock signal.
`Thus, if the REFCLKI clock signal recovers quickly,
`PLL 10 can continue operating at step 60 where it left
`off. Otherwise, if PL}. 10 is not phase locked with the
`REFCLKI
`clock
`signal, REFCLK]
`PHASE
`LOCKED step 66 returns to step 56 to re-achieve phase
`luck. If the REFCLKI clock signal does not recover
`quickly, the logic returns to step 54 to verify that the
`REFCLKI clock signal is indeed defective.
`Continuing onto FIG. 3,
`if the REFCLKI clock
`signal fails the initial check at step 54, or fails to recover
`in the allotted time at step 64. the logic checks the valid-
`ity of
`the REFCLKZ clock signal
`in CHECK
`REFCLK2 step 70. An invalid REFCLKZ clock signal
`returns PLL 10 to step 52 allowing the loop to maintain
`nominal operation with the RCWCLK clock signal until
`such time as one or both input clock signals REFCLKI-
`{REFCLKZ return. A valid REFCLKZ clock signal is
`routed through multiplexer 12 allowing PLL 1|] lock
`thereto as indicated in SELECT REFCLK2 AND
`ACHIEVE PHASE LOCK step
`72. CHECK
`REFCLK2 step
`76
`continuously monitors
`the
`REFCLKZ clock signal until an invalid status is de-
`tected at which time FLOAT VCO step 78 disables
`charge pump 18 to maintain loop node 20 in a floating
`condition.
`If the REFCLK2 clock signal
`recovers
`quickly, say in less than seven RC_CLK cycles,
`REFCLK2 QUICK RECOVERY step 80 verifies the
`recovery of the REFCLKZ clock signal and proceeds
`to REFCLKZ PHASE LOCKED step 82 which re-
`turns the loop to CHECK REFCLKZ step 76 if PL]. 10
`is still phase locked with the REFCLK2 clock signal.
`Again,
`if PLL 10 is not phase locked with the
`
`‘10
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`15
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`20
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`25
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`45
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`SO
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`5,260,979
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`6
`PHASE
`signal, REFCLK2
`clock
`REFCLKZ
`LOCKED step 82 returns to step 72 to re-achieve phase
`lock. If the REFCLK2 clock signal does not recover
`quickly, the logic returns to step ’78 to verify that the
`REFCLK2 clock signal
`is indeed bad and forces a
`switch to CHECK REFCLKI step 54 to see if
`REFCLK] has been operating for at
`least seven
`RC_CLK periods and, if so, returns control to steps
`56-60. An invalid REFCLKI clock signal brings the
`logic through step 70 back to step 52 where it cycles
`waiting for repair, although still Operating with the
`RC_C.LK clock signal.
`Turning to FIG. 4, there is shown further detail of
`redundant clock selector 14 including non-overlapping
`clock generator
`90
`coupled
`for
`receiving
`the
`REFCLKI clock signal and non-overlapping clock
`generator 92 coupled for receiving the REFCLK2
`cloclt signal. Non-overlapping clock generators 90 and
`92 each provide complementary output clock signals:
`one operating iii-phase with the respective input clock
`signal and one operating out-of-phase from the input
`signal. The output clock signals of non-overlapping
`clock generators 9i! and 92, such as REFCLKI and
`REFCLKI, are never logic one at the same time. The
`same is true for REFCLKZ and REFCLKZ. Divide-hy-
`64 circuit 94 divides the output clock signals of non-
`overlapping clock generator 90 for providing a
`REFCLK1_DIV clock signal operating at approxi-
`mately 64 KHz to valid REFCLKI detector 98. Like-
`wise, divide-by-64 circuit 100 receives the output clock
`signals of non-overlapping clock generator 92 and ap-
`plies the resultant 64 KHz REFCLK2_DIV signal to
`valid REFCLKZ detector 102.
`Redundant clock selector 14 also includes RC oscilla-
`tor 104 for providing a CLIC—A signal and a CLK_B
`signal to valid REFCLK] detector 93 and to valid
`REFCLKZ detector 102. The CLK_A and CLK_B
`signals are also applied to REFCLKI timer 108 and
`REFCLIQ timer 110. Clock selector 112 receives mul-
`
`tiple input signals from the output of REFCLKI timer
`108 and REFCLK2 timer 110, a SYSTEM RESET
`signal, the CLK_A and CLK_B signals, the REFCL-
`KIMFAIL signal from valid REFCLKI detector 98
`and
`the REFCLKJl—FAIL signal
`from valid
`REFCLK2 detector 102 for generating the REFCL-
`KL_ACTIVE signal, the REFCLKzaACTIVE signal
`and the RCLCLKJCTIVE signal for multiplexer 12
`of FIG. 1. Furthermore, clock selector 112 provides a
`REFCLK1_SELECT signal for valid REFCLKI de-
`tector 98 and a REFCLKZLSELECT signal for valid
`REFCLKZ detector 102.
`The clock signals REFCLKI and REFCLKI from
`non-OVerlapping clock generator 90 are shown in FIG.
`5 including NAND gate 120 having a first input cou-
`pled for receiving the REFCLK] input clock signal and
`an output coupled through inverter 122 for providing
`the in-phase REFCLKl clock signal. The output of
`inverter 122 is also coupled through inverter 124 to the
`first input of NAND gate 126, while the second input of
`the same receives the REFCLKI input clock signal
`complemented by inverter 130. The output signal of
`NAND gate 126 drives inverter 132 for providing the
`complemented REFCLKI clock signal which is also
`applied through inverter 134 to the second input of
`NAND gate 120.
`When the REFCLK] input clock signal is logic one,
`the in-phase REFCLK] clock signal is also logic one
`which produces logic zeroes at the first and second
`
`0012
`0012
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`

`5,260,979
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`7
`inputs of NAND gate 126. The output of NAND gate
`126 is logic one and the HEW clock signal is logic
`zero. The first and second inputs of NAND gate 120 are
`thus logic one and its output is logic zero leaving the
`in-phase REFCLK] clock signal at logic one as per the
`initial condition.
`As the REFCLK] input clock signal falls to a logic
`zero, the output of NAND gate 120 becomes logic one
`forcing the iii-phase REFCLK! clock signal to transi-
`tion to logic zero. The logic zero REFCLKI input
`clock signal produces a logic one at the second input of
`NAND gate 126. However, the output of NAND gate
`126 cannot change to logic zero until
`the iii-phase
`REFCLKI cloeksignal switches to logic zero. Hence,
`the REFCLKI clock signal remains logic zero until
`iii—phase REFCLKI clock signal becomes logic zero
`since the latter provides the second logic one at the first
`in at of NAND gate 126 necessary to switch the
`REFELKI clock signal to logic one.
`The non-overlapping period is determined by the
`delay through inverters 124 and 134 and may be ad-
`justed by sizing the transistors thereof. A similar logic
`operation is provided on the opposite edge wherein the
`in-phase REFCLKI clock signal cannot transition to
`logic one until the REFCLKI clock signal has changed
`to logic zero. Thus, the REFCLKI and REFCLKl
`clock signals are complementary and non-overlapping
`such that logic ones never appear simultaneously. Non-
`overlapping clock generator 92 is constructed in a simi-
`lar manner as described for non-overlapping clock gen-
`erator 90.
`RC oscillator 104- is shown in FIG. 6 including seri-
`ally coupled inverters 136, 138 and 140. Resistor 142 is
`coupled between input of inverter 136 and node 14-4,
`and resistor 146 is coUpIed between the input of inverter
`138 and node 144, while capacitor 148 is coupled be-
`tween the input of inverter 140 and node 14-4. Inverters
`136—140 in combination With resistors 142 and 146 and
`capacitor 148 form a monostable multi-vibrator for
`generating the RC_CLK clock signal at the output of 40
`inverter 140 operating at 500 KHz 120%. depending
`on the tolerances and temperature coefficients of resis-
`tors 142 and 146 and capacitor 148. The RC_.CLK
`clock signal is applied at the input of non-overlapping
`clock generator 150 for providing the CLK_A and
`CLK_B signals in a manner as described for non-over-
`lapping clock generator 90 in FIG. 5.
`Referring to FIG. 7, clock selector 112 includes
`NAND gate 154- having i'1rst and second inputs coupled
`for
`receiving REFCLKZJAIL signal
`and the
`REFCLK1_TIMER signal. The output of NAND
`gate 154 is coupled through inverter 156 to the first
`input of NOR gate 158. The REFCLK1_TIMER sig-
`nal is also applied to the first input of NOR gate 160,
`while the second input of the same is coupled for receiv-
`ing the REFCLK2_TIMER signal. NAND gate 164
`receives the REFCLKIHFAIL signal and the REFCL-
`K2_TIMER signal and provides an output signal
`through inverter 166 to the first input of NOR gate 168.
`The second and third inputs of NOR gate 158 receive
`the output signal of NOR gate 168 and the SYSTEM
`RESET signal. The output of NOR gate 158 is coupled
`to the second input of NOR gate 168 and to the first
`input of NOR gate 170. The output of NOR gate 168 is
`coupled to the first input of NOR. gate 174, while the
`output of NOR gate 160 is coupled to the second inputs
`of NOR gates 170 and 174. The third inputs of NOR
`gates 170 and 174 each receive the SYSTEM RESET
`
`60
`
`8
`signal. The output of NOR gate 170 provides the
`REFCLKIJCTIVE signal, and the output of NOR
`gate 174 provides the REFCLKLACTIVE signal.
`The REFCLK1_ACTIVE signal and the REFCL-
`K2_ACTIVE signal are applied at the first and second
`inputs of NOR gate 1'16 for providing the RC_CL-
`KJCTIVE signal at the output thereof.
`The output of NOR gate 158 is also coupled to the
`drain of transistor 1'18 which includes a gate coupled for
`receiving the CLK_B signal and a source coupled
`through inverters 180 and 182 to the drain of transistor
`184. The gate of transistor 184 is coupled for receiving
`the CLK_A signal and the source of the same is cou-
`pled through inverter 186 for providing the REFCL—
`Til—SELECT signal and again through inverter 188 for
`providing the REFCLK2_SELECT signal.
`Clock selector 112 also includes a clock status circuit
`190 for generating a RESET—FDET signal which re-
`moves the true lock status from lock detector and float
`circuit 38 upon detecting a switch between the
`REFCLKI, REFCLK2 and RC_.CLK clock signals.
`NAND gate 192 receives signals from the output of
`inverter 156,
`the output of NOR gate 168 and the
`REFCLK2_SELECT signal. The output of NAND
`gate 192 is applied at the first input of NAND gate 194.
`NAND gate 196 receives signals from the output of
`inverter 166,
`the output of NOR gate 158 and the
`REFCLKI_SELECT signal and provides an output
`signal to the second input of NAND gate 194. A third
`input of NAND gate 194 receives a RESETJLOAT
`signal from lock detector and float circuit 38 inverted
`by inverter 198, while the fourth input of NAND gate
`194 receives the output signal of NAND gate 200. In-
`verter 202 has an input coupled to the output of NOR
`gate 160 and an output coupled to the first input of
`NAND gate 200 and to the drain of transistor 204-. The
`gate of transistor 204 is coupled for receiving the
`CLK_B signal while its source is coupled through
`inverters 206 and 208 to the drain of transistor 210. The
`gate of transistor 21!]
`is coupled for receiving the
`CLK_A signal while its source is coupled through
`inverter 212 to the second input of NAND gate 200.
`The output signal of NAND gate 194 is the RESET—F-
`DET signal.
`Turning to FIG. 8, valid REFCLK] detector 98 is
`shown in further detail including 7-bit shift register 214
`coupled for receiving the CLK_A and CLK_B sig-
`nals. The most significant bit of shift register 214 is
`shown for illustration including transistor 216 having a
`drain coupled for receiving the REFCLKIJIV sig-
`nal. The gate of transistor 216 receives the CLK_A
`signal while its source is coupled through inverter 218
`to the drain of transistor 220 which includes a gate
`coupled for receiving the CLK_B signal and a source
`coupled to the gate of transistor 222 and through in-
`verter 224 to the gate of transistor 226. The drains of
`transistors 222 and 226 are coupled through resistors
`230 and 232, respectively. to power supply conductor
`236 operating at a positive potential such as VDD. The
`sources of transistors 222 and 226 are coupled to power
`supply conductor 238 operating at ground potential.
`The most significant bit of shift register 214 is pro—
`vided at the output of inverter 224. Bit 0, bit 1, bit 2, bit
`3. bit 4 and bit 5 of shift register 214 follow a similar
`construction as described for bit 6. The outputs of bit 6,
`bit 5 and bit 4 of shift register 214 are coupled to the
`inputs of NAND gate 240 and to the inputs of NOR
`gate 24-2. The output of NAND gate 240 is coupled
`
`45
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`0013
`
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`25
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`30
`
`9
`through inverter 24-4 to the drain of transistor 246, the
`latter of which includes a gate coupled for receiving the
`REFCLK1_DIV signal and a source coupled through
`inverter 248 to the first input of AND gate 250. The
`output of inverter 248 is also coupled through inverter 5
`254 and through the drain-to-source conduction path of
`transistor 256 back to the input of inverter 248. The gate
`of transistor 246 is coupled to the first input of AND
`gate 258 and through inverter 260 to the second input of
`AND gate 250 and to the gate of transistor 262. The 10
`output of NOR gate 242 is coupled to the drain of tran-
`sistor 262 while its source is coupled through inverter
`264 to the second input of AND gate 258. The output of
`inverter 264 is coupled through inverter 266 and
`through the drain-to-source conduction path of transis- 15
`tor 268 back to the input of inverter 264. The gates of
`transistors 256 and 268 are coupled for receiving a high
`signal from power supply conductor 236. The outputs
`of AND gates 250 and 258 are coupled to the first and
`second inputs of NOR gate 270, the output of which is 20
`applied at the first input of NAND gate 272.
`