|||||||||||||||||||||||||l|||||l|||||||||||||||||||||||||||||||||||||l|||||
`
`1.1300715561732
`
`(12) Umted States Patent
`00) Patent No.:
`US 7,155,617 132
`
`Gary et al.
`(45) Date of Patent:
`Dec. 26, 2006
`
`(54) METHODS AND SYSTEMS FOR
`
`_
`PERFORWSG DYNAMK} POWER
`“3VA(JM;:VT VIA l‘Rl‘QUI‘M'Y AM)
`‘ LIALB‘ k
`'ALITG
`
`(75}
`
`Inventors: Scott P. Gary. Santa Barbara. CA (US):
`Robert J. CW5.“3 Deimont. PA (US);
`Vijaya ll. 1’. Saratlly. Kamataka (1N)
`
`(T3) Assignee: Texas Instruments Incorporated.
`Dallas. TX (US)
`
`6.105.I42 A "
`
`$2000 (.ioffel at.
`
`6.131.|66 A
`6.425.086 Bl *
`6.519.?0? Bl ‘
`
`10-2000 Worrg—lnsley
`1-2002 Clark et a1.
`2.52003 Clark at at.
`
`6‘895'520 El 1
`6.921605 Bl '*
`
`552005 Ahmejd 6‘ 31'
`£02005 Fetzer et a].
`
`”Ill-324
`
`“3:322
`“3.5322
`
`“3324
`327.10]
`
`(Continued)
`
`( “‘ } Notice:
`
`Subject to any disclaimer. the tom of this
`Sign} titsixgenged .2}; :djusled under 3'5
`‘
`'L'
`‘
`( ]
`3 4‘
`ays.
`
`‘
`(2‘) APPL NO“ 10’4511947
`
`OTHER PUBLICATIONS
`Jiong Luo. et a1.; Battery—Aunt? Static Seitedtrt'tttgfor Distributed
`Rent—Time Embedded System. Dept. of Electrical Eng. Princeton
`Univ. Princeton. NJ. DAC‘ 200 I. .lurl.
`lit—22. I002. [as Vegas. NV.
`1:3. 200: am l—58I13—29T—2.-"t1|."0006:6 pgs.
`
`(22)
`
`(65}
`
`Filed:
`
`Jun. 13, 2003
`
`Prior Publication Data
`US 2004t0025069 Al
`F b. 5‘ 20,04
`9
`Related U.S. Application Data
`
`(Continued)
`
`Primary Examiner—Lynne I-I. Browne
`Assistant Exatttmer—Michae] J. Brown
`{74) Attornqt'. Agent. or Firm—Robert D. Marshall. Jr.: W.
`James Brady; Frederick J. Telecky. Jr.
`
`[60)
`
`[i’roztgsizonal application No. Got-100.426. filed on Aug.
`
`[57)
`
`ABSTRACT
`
`(5”
`
`213619106
`(2006 0]}
`0061-“ 1R2
`(200601)
`0061’ 9’214
`(2006-01)
`0061’ 13/10
`(200601)
`{1706F 9/45
`(200601)
`[52} U S CI
`713800 713810 713320
`'
`'
`'
`71%,:22. 1035? Tmflé
`._
`‘
`‘
`"
`‘
`"
`‘
`_
`_
`‘
`(58} held of Classificatlon 5:13;:th d"'3'2"1‘"'3'2"2 £38103).
`gm '1
`licatio file for m”; iete‘smrch him -' ‘
`‘
`‘ pp
`11
`P
`‘
`1
`ry.
`References Cited
`US. PATENT DOCUMENTS
`
`(56)
`
`5.201.059 A
`5.812.860 A
`
`491993 Nguyen
`9-"1998
`I'Iorden et al.
`
`Methods and systems are provided for dynamically manag-
`ing the power consumption of a digital system. These
`methods and systems broadly provide for varying the Ire-
`quency and voltage of one or more clocks ofa digital system
`upon request by an entity of the digital system. An entity
`may request that the frequency ofa clock oi'the processor of
`the digital
`system be changed. Alter the frequency is
`changed.
`tlte voltage point of the voltage regulator of the
`digital system is automatically changed to the lowest voltage
`point required for the new frequency ii'thereis asingle clock
`on the processor. If the processor is comprised of multiple
`processing cores with associated clocks. the frequency is
`changed to the lovvest voltage point required by all frequen-
`cies ot'all clocks.
`
`33 Claims, 5 Drawing Sheets
`
`
`
`0001
`
`AMD EX1018
`AMD EX1018
`U.S. Patent No. 6,895,519
`US. Patent No. 6,895,519
`
`

`

`US 7,155,617 32
`Page 2
`
`U .S. PATENT DOCUMENTS
`
`20030083355 A1
`20023013837? AI
`
`6:“2002 Clark etal.
`1232002 Buch
`
`0T1 IER PUBLICATIONS
`
`Seongsoo Lee. et al.; Rnrr-i’irrre Power- Corrtr'oi' Scheme Using
`Safiware Feedback Loop firr' Low-porter Real-lime Appiicatiorrs.
`Ctr. For Collaborative Research and Institrrte of Industrial Science.
`Univ. of Tokyo. 2000 IEEE ISBN 0-7803-5974-7. pp. 38| 3586.
`Luca Benini. et al.: Systerrr—Lmrei Power Optimization: Techniques
`and Toots. [SLPEDQ‘l San Diego. CA. USA. [999 AC M 168113-
`l33—X.-’99.-'0008. pp. 283-293.
`Seongsoo Lee, et al.; Rurr-l’irrre l'oitage Hopping for LownPower'
`Real-Time Systems. Ctr. for Collaborative Research and Institute of
`Industrial Science. Univ. of Tokyo. 2000 ACM l-SSIB-lSS-I’Oflr'
`00006; pp. 806-309.
`Tom Halfhill. inrei Spiii's the Beans About Barrios—New Mobile
`CPU and Chip Set HaveNnnrer'ora Power-Saving Featrtres. Micro-
`processor. Speciai Fxmnded [ssue Covering Microprocessor Forum
`2002. vol. 16. Archive 11. Nov. 2002. pp. 4-10.
`Gang Quan. et al.; Energy bficierrt fired-Priority Schedrttirrgfor'
`Rent—Time Systems on Variabte Foliage Processors. Dept. ofCom-
`
`puter Science and Eng. Univ. of Notre Dame. Notre Dame. IN.
`USA. DAC 200]. Jun. [8-22.1002.Las Vegas. NV. US. 2001 ACM
`l-SSll3-29?-2-"0l.-"0006; 6 pgs.
`Texas Instruments Incorporated. Agoiimrion Report: Analyzing
`Target System Energy Consumption in Code Cornposer'
`.S‘r‘rrcir'oTM
`iDE. Soflxvare Development Systems. pp.
`l—IZA.
`Dnngkun Shin. et at; Intro—Task Voltage Seirertuiing for Low—
`Errergy Hard Real-Tiara Appiicatiorts,
`IEEE Design 8: Test of
`Computers. Voltage Scheduling for Applications. Man-Apr. 200l.
`0740-74T5r'01. 200] [EEE. pp. 20-30.
`[997:6'MOS
`Jun.
`Texas Instruments Incorporated. SCAA035B.
`Power Consumption and CW. Madam... Soliware Development
`Systems. [6 pgs.
`Ami! Sinha. at 3.1.; Energy Efieie'rrt Rani—Time Seiseo’trit‘rig. Mass.
`Inst. of Technology. Presentation. [9 [335.
`Intel.
`t'rrtei'i‘C PCA Pou-‘er' Management. Sojirr'ar'e Design Guide.
`Sep. 4. 2002. Rev. 1.0. 72 pgs.
`Texas Instruments Incorporated. Anotr’catr'orr Report: Coirrrtatr’orr of
`W5320LC54X Power-Dissipation. Digital Signal Processing Solu-
`tions. 199?. 62 pgs.
`
`* cited by examiner
`
`0002
`0002
`
`

`

`US. Patent
`
`Dec. 26, 2006
`
`Sheet 1 of 5
`
`US 7,155,617 B2
`
`APPLICATION
`
`CONTROL
`
`THREAD
`
`
`
`
`APPLICATION
`
`
`
`APPLICATION
`
`
`THREAD
`THREAD
`
`
`
`
`
`
`POWER
`
`
`mos
`KERNEL
`MANAGER
`
`
`(PWRM)
`
`
`
`1002
`
`1005
`
`
`
`_RIVER
`
`o
`
`
`
`DRIVER
`
`1000
`
`1008
`
`1004— FIG 1
`
`DRIVER
`
`2004
`
`
`
`(E.G..
`
`DMA LINK
`
`
`DRIVER)
`
`2000
`
`APPLICATION
`
`CODE
`
`
`
`0003
`0003
`
`

`

`US. Patent
`
`Dec. 26, 2006
`
`Sheet 2 of 5
`
`US 7,155,617 B2
`
`3000
`
`
`PWRH— Power Manager Proerfies
`
`3001
`
`3002
`
`3003
`
`3004
`
`
`
`General . J’— Elli-ng‘ \ lgfi-Eco—Iigg_
`3005
`EnabIe PWHM Manager
`3005“ Call user hook function at boot time
`
`Function:
`
`w0EIVIJurn0MUttiirJfiunp
`
`3007
`
`Reprogram BIDS clock after frequency scaling
`
`
`
`
`
`'[ PWRH- Power Manager Properties
`
`3008
`
`EMIF
`
`CLKGEN
`
`PERIPHS
`
`CACHE
`
`DMA
`
`CPU
`
`0004
`
`

`

`US. Patent
`
`Dec. 26, 2006
`
`Sheet 3 of 5
`
`US 7,155,617 B2
`
`
`
`'PWRllt-P-owe—r Manager Properties
`
`
`
`
`
`
`
`
`
`
`lnitlal volyage (volts):
`
`Scale voltage along with frequency
`IE Wait while voltage is being scaled down
`
`FIG. 3C
`
`
`
`PWRM- Power Manager Properties
`
`
`
`
`
`
`
`
`
`
`EMlF
`
`CLKGEN
`
`PERlPHS
`
`CACHE
`
`DMA
`
`CPU
`
`Wakeup interrupt mask, lERU:
`
`Wakeup interrupt mask, lEFll:
`
`[WIN 0
`
`UXUOUU
`
`Enable sleep until restart
`3011f Enable snooze mode
`Timer to be used for snooze mode:
`
`ITifler l
`
`_
`
`'l
`
`0005
`0005
`
`

`

`US. Patent
`
`Dec. 26, 2006
`
`Sheet 4 of 5
`
`US 7,155,617 B2
`
`BUILD
`
`APPLICATION
`
`
`
`
`
`MEASURE
`
`POWER
`
`4004
`
`
`
`POWER OK?
`
`NO
`
`VISUALIZE
`
`POWER
`
`4006
`
`
`
`
`
`EXAMINE CPU
`LOAD
`
`
`EXAMINE
`
`PERIPHERAL
`
`ACTIVITY
`
`
`
`4008
`
`ADJUST
`
`
`DYNAMIC POWER
`MANAGEMENT
`
`PERIPHERAL
`
`ACTIVITY IN
`
`APPLICATION
`
`
`
`4010
`
`FIG. 4
`
`0006
`0006
`
`

`

`US. Patent
`
`Dec. 26, 2006
`
`Sheet 5 of 5
`
`US 7,155,617 B2
`
`5000
`
`FIG. 5
`
`POWER DATA
`
`TRIGGER DATA
` IEEE 488 AP!
`
`
`
`POWER
`ANALYZER
`
`
`PLUG-IN
`
`IEEE 433 DRIVER
`
`5014
`
`lEEE 488 CARD
`
`
`
`
`IEEE 488 CABLE
`
`5002
`
`0007
`0007
`
`

`

`US 7,155,617 32
`
`1
`METHODS AND SYSTEMS FOR
`PERFORMING DYNAMIC POWER
`MANAGEMENT VlA FREQUENCY AND
`VOLTAGE SCALING
`
`This application claims priority to provisional application
`Ser. No. 60l400,426 filedAug. l. 2002 {fl-34977PS}. This
`application is related to copending applications Ser. No.
`103161.289 entitled Methodology for Coordinating and Tun-
`ing Application Power (Tl-35526) and Ser. No. 10l461.025
`entitled Methodology for Managing Power Consumption in
`an Application (f1-35525).
`
`FIELD OF 'l‘l-ll'i INVliN'l’lON
`
`This invention generally relates to software development
`systems. and more specifically to improvements in software
`support for power management in systems and applications.
`
`BACKGROUND OF THE INVENTTON
`
`Power efficiency is a key requirement across a broad
`range of systems. ranging front small portable devices, to
`rack-mounted processor farms. Even in systems where high
`performance is key, power efficiency is still a care-about.
`Power efficiency is determined both by hardware design and
`component choice, and software-based runlime power man-
`agement tecluiiques.
`In wired systems power efficiency will typically enable a
`reduction in power supply capacity. as well as a reduction in
`cooling requirements and fan noise. and ultimately product
`cost. Power efficiency can allow an increase in component
`density as well. For example. a designer may be limited by
`the number of processors that can be placed on a board
`simply because the cumulative power consumption would
`exceed compliance limits for the bus specification. increased
`component density can result either in increased capacity, a
`reduction in product size. or both.
`In mobile devices. power efiiciency means increased
`battery life. and a longer time between recharge.
`It also
`enables selection of smaller batteries. possibly a different
`battery technology. and a corresponding reduction in prod-
`uct sixe.
`Power efficiency is a key product diflerentiaton A simple
`example is a buyer shopping for an MP3 player at an
`electronics store. in a side-by-side comparison of two play-
`ers with the same features, the decision will likely go to the
`player with the longest time between recharge. in many
`scenarios. the success or failure of a product in its market~
`place will be determined by its power elficiency.
`The total power consumption of a CMOS circuit is the
`sum of both active and static power
`consumption:
`Pmm=Pamve+PmW Active power consumption occurs
`when the circuit is active. switching from one logic state to
`another. Active power consumption is caused both by
`switching current (that needed to charge internal nodes). and
`through current (that which flows when both I" and N-cltart-
`
`1o
`
`21]
`
`25
`
`3t]
`
`4t}
`
`5t]
`
`55
`
`2
`
`transistors are both momentarily on). Active power
`neI
`consumption can be approximated by
`the
`equation:
`In"
`P,,m,.e,,,=CdeFXVRZXN
`where Cpd is
`the dynamic
`capacitance. F is the switching frequency. V“. is the supply
`voltage, and NW,
`is the number of bits switching. An
`additional relationship is that voltage (ij determines the
`maximum switching frequency ([7) for stable operation. The
`important concepts here are: l) the active power consump-
`tion is linearly related to switching frequency. and quadrati-
`cally related to the supply voltage, and 2) the maximum
`switching frequency is detemtined by the supply voltage.
`If an application can reduce the CPU clock rate and still
`meet its processing requirements. it can have a proportional
`savings in power dissipation. Due to the quadratic relation—
`ship.
`if the frequency can be reduced safely. and this
`frequency is compatible with a lower operating voltage
`available on the platfonn. then in addition to the savings due
`to the reduced clock frequency. a potentially significant
`additional savings can occur by reducing the voltage. How
`ever. it is important to recognize that for a given task set.
`reducing the CPU clock rate also proportionally extends the
`execution time of the same task set, requiring careful analy-
`sis ofthe application ensure that it still meets its real-time
`requirements. The potential savings provided by dynamic
`voltage and frequency scaling (DVFS) has been extensively
`studied in academic literature, with emphasis on ways to
`reduce the scaling latencies. improve the voltage scaling
`range. and schedule tasks so that real—time deadlines can still
`be met. For example. see Run-time Power Control Scheme
`Using Sofiware Feedback Loopfor Low-Poitier Real-time
`Applications.
`lEEE ISBN 0-?803-5974-i. Seongsoo Lee,
`Tukayasu Sakurai. 2000; intro-Fisk Voltage Schedulingfor
`Lou-'«Energy Htmi Real-lime Applications. IEEE Design &
`Test of Computers. Dongkuu Shin. Jihong Kim. Seongsoo
`Lee. 2001: and Run-time Voltage Hoppirrgfor low-power
`Rodi-time .St-‘srems. DACQOUO. ACM [-581 13-] 88-7, Setting-
`soo Lee. Takayasu Sakurai 2000.
`Static power consumption is one component of the total
`power consumption equation. Static power consumption
`occurs even when the circuit
`is not switching. due to
`reverse-bias leakage. Traditionally.
`the static power con-
`sumption of a CMOS circuit has been very small in cont—
`parisou to the active power consumption. Embedded appli-
`cations will typically idle the CPU clock during inactivity to
`eliminate active power. which dramatically reduces total
`power consumption. However, new higher-perfonnance
`transistors are bringing significant boosts in leakage cur-
`rents. which requires new attention to the static power
`constimption component of the total power equation.
`There are many known techniques utilized both in hard-
`ware design and at run-time to help reduce power dissipa-
`tion. Table 1 lists some tip-front hardware design decisions
`for reducing power dissipation. Table 2 lists common tech-
`niques employed at run-time to reduce power dissipation.
`Table 3 lists some fundamental challenges to utilising these
`power management techniqUCs in real-time systems.
`
`Decision
`
`Description
`
`TABLE 1
`
`Choose a low-power
`technology base
`Partition separate voltage
`and clock domains
`
`Choosing a pnwer-elIicieItl process tag. CMOSl is perhaps the most important up-
`front decision. and directly drives power efliciency.
`Fly panitioning separate domains. dilfercnl components can be. wired to the
`appropriate power mil and clock line. eliminating the need. for all circuitry to operate
`at the maximum required by any specific module.
`
`0008
`0008
`
`

`

`US 7,155,617 BZ
`
`TABLE l-contiuued
`Decision
`Description
`
`Enable scaling of voltage
`and frequency
`
`Enable gating of difi‘erent
`voltages to modules
`
`Ulilize interrupts to alleviate
`polling by soltware
`
`Designing in programmable clock generators allows application code a linear savings
`in power when it can scale down the clock frequency. A programmable voltage
`source allows the potential for an additioml quadratic power savings when the \vollage
`can be reduced as well. because of reduced frequency. Also. designing the hardware
`to minimize scaling latencies will enable broader usage of the scaling technique.
`Some static RAMs require less voltage in retention mode vs. normal operation mode.
`By designing Ln voltage gating circuitry. power consumption can be reduced during
`inactivity while still retaining state.
`Often software is required to poll an interface periodically to detect events. For
`example. a keypad interface routine might need to spin or periodically wake to detect
`and resolve a keypad input. Designing the interface to generate an interrupt on
`keypad input will not only simplify the software. but it will also enable event~drivcn
`processing and activation of processor idle and sleep modes while waiting for
`interrupts.
`Decreasing capacitive and DC loading on output pins will reduce lotal power
`consumption.
`Depending on the application utilizing cache and inm'uction bufi‘ers can drastically
`reduce ofi-chip memory accesses and subsequent power draw.
`Many systems boot in a fully active. state, meaning full power consumption. If certain
`sub-systems can be lefl un-powered on boot, and later turned on when really needed.
`it eliminates umieceeaary wasled power.
`Using shared clocks can reduce the number of active clock generators. and their
`corresponding power draw. For example, a processor’s on-board PLL can be
`bypassed in favor ofan external clock signal.
`Use clock dividers for last
`A common barrier to highly dynamic frequency scaling Ls the latency of re-loclting a
`selection of an alternate
`PLL on a frequency change. Adding a clock divider circuit at the output of the PLL
`
`frequency Will allow inslzntnneous selection ofa different clock frequency.
`
`Reduce loading of outputs
`
`Use hierarchical memory
`model
`Boot wilh resources on-
`powered
`
`Minimize uumber ol‘ active
`phase lock loops {PLLl
`
`TABLE 2
`
`Technique Description
`
`Gate clocks of when not
`needed
`
`Activate peripheral low-
`power modes
`
`Leverage peripheral
`activity detectors
`
`Utilize auto-refresh modes
`
`0n boot actively turn ofl‘
`un-necessary power
`consumers
`
`Gate power to subsystems
`only as needed
`
`Benchmark application to
`find minimum required
`frequency and voltages
`
`Adjust CPU frequency and
`voltage based upon gross
`activity
`
`As described above, active power dissipation in a CMOS circuit occurs only when the
`Circuit is clocked. By turning olTCIOCkS that are not needed. unnecessary aciiw
`power consumption is eliminated. Most processors incorporate a mechanism to
`temporarily suspend active power consumption in the CPU while waiting for an
`external event. This idling of the CPU clock is typically triggered via a 'lIalt‘ or ‘idle‘
`instruction, called during application or OS idle time. Some processors partition
`multiple clock domains. which can be individually idled to suspend active power
`consumption in unused modules. For example. in the Texas Instntments
`TMSJNCSSIO DSP. six separate clock domains. CPU. cache. DMA. peripheral
`clocks. clock generator. and external memory interface. can be selectively idled.
`Some peripherals have buil't‘in low power modes that can be activated when the
`peripheral is not immediately needed. For example. a device driver managing a codec
`over a serial port can command the codec to a low power mode when there is no
`audio to be played. or ifthe whole system is being transitioned to a low-power mode.
`Some peripherals have built-in aclivity detectors that can be programmed to power
`down the peripheral alter a. period of inactivily. For example. a disk drive can be
`automatically spun down when the drive is not being accessed. and spun backup
`when needed again.
`Dynamic memories and diiqalays will typically have a self or auto—refresh mode where
`the device will efficiently manage the refresh operation on its own.
`Processors typically boot up fully powered. a1 a maxinnnn clock rate. ready to do
`work. There will inevitably be resources powered that are not needed yet. or that may
`never be used in the course of the application. Al boot time. die application or 05
`may traverse Ihe systan. turning ofl‘lidling unnecessary power consumers.
`A system may include a powerhhungry module that need not be powered at all Times.
`For example. a. mobile device may have a radio subsystem that only needs to be OK-
`when in range of the device widi which it communicates. By gating power OFFION
`on demand. unnecessary power dissipation can be avoided.
`Typically. systems are designed with excess processing capacity built in. either for
`safety purposes, or for future extensibility and upgrades. For the latter case, a
`common development technique is to fully exercise and benchmark the application
`to determine excess capacity. and then ‘dial-down' die operating frequency and
`voltage to that which enables the application to fully meet its requirements. but
`minimises excess capacity. Frequency and voltage are usually not changed at
`runtime. but are set at boot time. based upon the benchmarking activity.
`Another technique for addressing excess processing capacity is to periodically
`sample CPU ulilizzuion at runtime, and then dynamically adjust Ihe frequency and
`voltage based upon the empirical utilization of the processor: This "interval-based
`scheduling" technique improves on the power-savings of the previous static
`benchmarking technique because it lakes advantage of Lhe dynamic variability of
`the application's processing needs.
`
`0009
`0009
`
`

`

`US 7,155,617 BZ
`
`TABLE 2-continued
`
`
`
`Optimize execution speed of
`code
`
`Use low-power code
`sequences and data patterns
`
`Technique Description
`Dynamically schedule CPU
`The "inten'al-hased scheduling" technique enables dynamic adjustments to
`frequency and voltage to
`processing capacity based upon history data, but typically does not do well at
`match predicted work load
`antiCipating the litmle moods of the application, and is therefore not acceptable for
`systems with hard real-time deadlines. An alternate technique is to dynamically
`vary the. CPU frequency and voltage based upon predicted workload. Using
`dynamic, fine-grained comparison of work completed vs. the worst—case execution
`time {WCET} and deadline of the next task. the CPU frequency and voltage can be
`dynamically tuned to the minimum required. This technique is most applicable to
`specialized systems with data—dependent processing requirements that can be
`accurately characterized. Inability to frilly characterize an application usually limits
`the general applicability of this technique. Study of efiicient and stable scheduling
`algorithms in the presence of dyururtic frequency and voltage scaling is a topic of
`much on-going research.
`Developers often optimize their code for execution speed. However. in many
`situations the speed may be good enough, and further optimizations are not
`considered. When comiderirlg power consumption, faster code will typically mean
`more time for leveraging idle or sleep modes. or a. greater reduction in the CPU
`frequency requirements. In some situations. speed optimizations may actually
`increase power consumption (eg. more parallelism and subsequent circuit activityl.
`but in others. more may be power savings.
`Difi‘erent processor instructions exercise difierent functional units and data paths.
`recruiting in dill'crent power requirements. Additionallyf because of data bus line
`capacitances and the inter-signal capacitances between bus lines, the amount of
`power required is afl‘emed by the data patterns that are transferred over the data
`buses. And. the power requirements are afl'octed by the signaling patterns chosen
`{is vs. Os) for external interfaces [e.g.. serial ports). Analyzing the affects of
`individual inslructions and data patterns is an extreme technique that is sometimes
`used to maximise power elficiency.
`Architecting application and 03 code bases to be scalable can reduce memory
`requirements and. therefore. the subsequent matitnc power rcquircments. For
`example, by simply placing individual functions or APIs into individual linkable
`objects. die linker can link in only the codei'data needed and avoid linking dead
`coderdata.
`For some applications. dynamically overlaying code from non-volatile to fast
`memory will reduce both the cost and power consumption of additional that
`memory.
`Accepting less accuracy in some calculations can drastically reduce processing
`requirements. For example, certain signal processing applications can tolerate more
`noise in the results. which enables reduced processing and reduced power
`consumption.
`When there is a change in the capabilities ofthe power source, cg, when going
`from AC to battery power. a common technique is to enter a reduced capability
`mode with more aggressive runtime power management. A typical example is a
`laptop computer, where the OS is notified on a switch to battery power, and
`activates a difi'erent power management policy. with a lower CPU clock rate. a
`shorter timeout before the screen blanks or the disk spins down. etc. The 05 power
`policy implements a tradcoii' between responsiveness and attending battery life. A
`similar technique can be employed in battery-only systems, where a battery monitor
`detects reduced capacity, and activates more aggressive power management, such
`as slowing down the CPU, not enabling image viewing on the digital camera‘s IJCD
`display. etc.
`
`Scale application and OS
`footprint based upon
`minimal requirements
`
`Use code overlays to reduce
`fast memory requirements
`
`Tradeofi' accuracy vs. power
`consumption
`
`Enter a reduced capability
`mode on a power change
`
`TABLE 3
`
`
`
`Challenge Description
`
`Scaling CPU frequency with
`workload often affects
`peripherals
`
`WF scaling latencies can be
`large. and platform-
`
`Might not have stable-
`operation during WF scaling
`
`For many processors the same clock Iltat feeds the CPU also foods on-chip
`peripherals, so scaling the clock based upon CPU workload can have sidewaffects
`on peripheral operation. The peripherals may need to be reprogrammed before
`andlor afler the scaling operation, and this may be difficult if a pro—existing (non
`power—aware} device driver is being used to manage the peripheral. Additionally,
`iflhc scaling operation eliects the timer generating the 05 system lick. this timer
`will need to be adapted to follow the scaling operation, which will affect the
`absolute accuracy of the time base.
`The latency for voltage and frequency scaling operations will vary widely across
`platforms. An application that runs fine on one platform may not be portable to
`another platform. and may not run on a revision to the same platfonn ifthc
`latencies change much. For example. the time for a down-voltage scaling
`operation is typically load-dependent. and if the load changes significantly on the
`revised platform the application may not run corredly.
`Some processor vendors specify a non-operation sequence during vollage or
`clock frequency changes to avoid instabilities during me transition. In these
`situations, "It. scaling code will need to wait for the transition to occur before
`returning. increasing the scaling latency.
`
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`

`US 7,155,617 BZ
`
`TABLE 3-corninued
`
`
`
`Challenge Description
`V.-'F scaling directly affects
`ability to meet deadlines
`
`Sealing the. CPU clock can
`affect ability to measure CPL‘
`utilization
`Watchdogs still need to be
`kept twain
`
`Idle and sleep modes
`typically collide with
`emulation. debug. and
`instrumentation
`
`Context ssver’nestore can
`become non—trivial
`
`Most advanced power
`management techniques are
`still in the research stage
`
`Different types of
`applications call for
`dilferent techniques
`
`Changing CPU frequency {and voltage when possible} will alter the execution
`time of a given task. potentially causing the task to miss a real-time deadline.
`Even if the new frequency is corrrpaliblc with Lin: deadline. there may still be :1
`problem if file latency to switch between WF setpoints is too big.
`lftlie clock that feeds the CPU also feeds the 05‘ timer, tlte OS timer will be
`scaled along with the CPU. which compromises meastuement oI‘CPU utilization.
`
`Watchdog timers are used to detect abnormal program behavior and either
`shutdown or reboot a system. Typically the watchdog needs to be serviced within
`a predefined time interval to keep it from triggering. Power management
`techniques that slow down or suspend pmmsssing can therefore inadvertently
`trigger application failure.
`Depending upon the processor and the debug tools, invoking idle and sleep modes
`can dismpt the transport of real-time ins1nunentation and debugging infonnation
`from the target. in the worst case it only perturb and even crash the debug
`environment. Similar concerns arise with VHF scaling. which may cause dificulty
`for the emulation and debug circuitry. it may be the case that power management is
`enabled when the system is deployed, but only minimally used during development.
`In :1 nun-power managed environment the OS or application framework will
`typically save and restore register values during a context switch. As register
`banks. memories, and other modules are powered OFF and back ON. the context to
`be saved and restored can grow drmnatically. also, il‘a module is powered down it
`may be difficult {and sometimes not possible} to fully restore the internal date of
`the module.
`Many of the research papers that demonstrate significant power savings use hiytly
`specialized application examples. and do not map well to general application cases.
`Or. they make assumptions regarding the ability To fully characterize an application
`such that it can be gtaranteed to be schedulable. These techniques often do not
`map to ‘real world‘, multi—thnction programmable systems, and more research is
`needed for broader applicability.
`Difi'erent hardware platforms have varying levels of support for the above listed
`techniques. Also. dilfercnr applications running on the same platform may have
`different processing requirements. For sortie applications. only the low-latency
`techniques leg... clock idling} are applicable. but for others the highenlrtteitcy'
`techniques can be used to provide significant power savings when the application
`switches between modes with significantly different processing requirements. For
`example, one mode can be run at low \’-"F. and another mode, with higher
`processing requirements. can be run at a higher VIF. If the WI: latency is
`compatible with die mode switch time. the application can use the technique.
`
`SUMMARY OF THE INVENTION
`
`The present invention provides methods and systems for
`dynamically managing power consumption in a digital sys-
`tem. Embodiments of the invention permit entities of the
`digital system to vary the frequency and voltage used to
`power a processor of the digital system. The processor of the
`digital system may be comprised ofa single processing core
`with a single clock or a multiple of processing cores. each
`with its own clock. An entity may request that the current
`frequency of a clock he changed to a new frequency and the
`change will be made. The voltage point of the voltage
`regulator in the digital system is then automatically changed
`to the minimum voltage required by that frequency if there
`is a single clock. If there are multiple clocks in the processor,
`the voltage point is automatically changed to the minimum
`voltage required by all frequencies of all clocks. An entity
`may request a frequency change for one clock or a multiple
`of clocks in a single request.
`Digital systems are provided operable to dynamically
`manage power consumption by providing for scaling of
`frequency and voltage during operation of the digital sys-
`tems. Embodiments of such digital systems comprise a
`processor. a voltage regulalor. and a memory storing a power
`scaling library executable to enable any entity of the digital
`system change the frequency and voltage of the digital
`system. The power scaling library is operable to cause the
`voltage to be automatically changed to the minimum voltage
`required by a frequency when an entity requests a frequency
`
`change. The power scaling library may be ftu‘ther executable
`to enable an entity to obtain a current frequency of the clock.
`to obtain a current voltage of the voltage regulator. to obtain
`all valid frequencies of the clock,
`to obtain a minimum
`required voltage for each of the valid frequencies of the
`clock, and to obtain a maximum latency for a change from
`a first frequency and voltage to a second frequency and
`voltage.
`In other embodiments. the processor of the digital system
`comprises multiple processing cores, each with an associ-
`ated clock. In such embodiments, the powor Scaling library
`is executable to permit an entity to cause the frequencies of
`two or more clocks to be changed. And, the power scaling
`library is executable to automatically changes the voltage to
`the minimum voltage required by all frequencies of all
`clocks when the frequencies of the two or more clocks are
`changed.
`
`BRIEF DESCRIPTION OF THE DRAWDJGS
`
`Particular embodiments in accordance with the invention
`
`Si]
`
`55
`
`on
`
`will now be described, by way of example only. and with
`reference to the accompanying drawings:
`FIG. 1 presents a logical architecture of an embodiment of
`a system that permits applications to utilize power manage
`ment techniques compatible with application requirements;
`FIG. 2 illustrates a registration and notification method of
`a power management system;
`0011
`0011
`
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`

`US 7,155,617 32
`
`9
`FIGS. 3A —31) illustrate the static configuration process of
`an embodiment of a power management system;
`FIG. 4 illustrates a method for application development
`that includes developing a power management strategy for
`the application: and
`1“ 1G. 5 presents an embodiment of a minimally intrusive
`system for power profiling of an embedded application that
`enables the method of FIG. 4.
`Corresponding numerals and symbols in the different
`figures and tables refer to corresponding parts unless other-
`wise indicated.
`
`DETAILED DESCRIPTION OF EMBODIMENTS
`OI? 'I‘IIIT. INVENTION
`
`The present invention provides systems and methods to
`pcrntit application developers to select and utilize power
`management techniques that are cotnpatible with specific
`application requirements. Although these systems and meth-
`ods are described below in relation to a real-time operating
`system (RTOS). they may be easily adapted by one skilled
`in the art to other operating systems or application environ—
`ments without an operating system.
`FIG. 1 presents a logical architecture ot‘an embodiment of
`a system that permits applications to utilize power manage-
`tnent techniques compatible with application requirements.
`Power management module (PWRM) 1000 is added to an
`application comprising real-time operating system (R'IUS)
`1002. processor 1004. and various device drivers 1006.
`Conceptually. PWRM 1000 is an adjunct to RTOS 1002.
`PWRM 1000 does not operate as another task in RTOS
`1002. Instead. PWRM 1000 pro