I|l|||||||||||||||||||l||||||l||||||||l|||||||||l||l|l||ll||||||||||||l|l||
`
`USIHJ6681336BI
`
`(12) United States Patent
`US 6,681,336 B1
`(10) Patent N0.:
`Nakazato et a].
`
`(45) Date of Patent: Jan. 20, 2004
`
`(S4) SYSTEM AND METHOD FOR
`IMPLEMENTING A USER SPECIFIED
`PROCESSING SPEED IN A COMPUTER
`SYSTEM AND FOR OVERRIDING THE
`USER SPECIFIED PROCESSING SPEED
`DURING A STARTUP AND SHUTDOWN
`PROCESS
`
`(75)
`
`Inventors: Ryu Nakazato, Yokohama (JP);
`Maynmi Maeda, Ome (JP)
`
`(73) Assignee: Kabushiki Kaisha Toshiba. Kawasaki
`(JI’)
`
`( ‘ ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 15403) by 586 days.
`
`(21) Appl. No: 09,695,931
`
`(22)
`
`Fiied:
`
`Jun. 16, 2000
`
`(30)
`
`Foreign Application Priority Data
`
`Jun. 18, 1999
`Oct.2l,1999
`
`(JP)
`(JP)
`
`Int. CL"
`(51)
`(52) US. Cl.
`(58) Field of Search
`
`11-17305
`11-299mm
`
`G061“ U32
`713(322; 713,31
`
`713t300, 320,
`713322, 500, 501, 502
`
`(56)
`
`References Cited
`U.S. I’AFEN'I' DOCUMENTS
`
`5,16102-1 A "
`5,546,568 A *
`5.?54,869 A
`5,768,602 A
`
`Ilt'1992 Smith ct al.
`Stl99ti Bland et al.
`5t'1998 IIolzhamnter et al.
`(#1998 Dhue)’
`
`713L322
`713.501
`
`$1998 Asghar
`5,768,613 A *
`Iitl‘J‘JS Lin
`5,835,885 A "
`5,845,111 A * 12.4908 Lin et al.
`6,044,“? A *
`SIZOUO Mttljono et al,
`6,442,?00 BI
`"
`812MB Cooper
`FOREIGN PATENT DOCUMENTS
`
`
`
`T12t'35
`T0299
`T135131
`710,652
`THBZU
`
`JP
`JP
`JP
`
`[OI-124200
`11—259162
`20le1th563 A *
`
`5.31998
`9.0009
`4t'2001
`
`Gt’hF.-'lt'04
`
`OTHER PUBLICATIONS
`
`Intel, Mobile Pentium III Processor in BGAZ and Mir-
`eo—PGA2 Packages, 2000f
`
`* cited by examiner
`
`Primary Examiner—Dennis M. Butler
`Assistant Examiner—M ark Connolly
`(74) Attorney, Agent, or Firm—Finnegan, Henderson,
`li'arabow, Garrett & Dunner, L.L.l’.
`
`(5?)
`
`ABSTRACT
`
`The CPU operates at the highest speed in start processing of
`an operating system. When a power-saving driver receives a
`start completion message from the operating system,
`the
`power-saving driver waits for a predetermined period until
`user operation to a computer system is enahied, a rid then sets
`the processing speed of the CPU to a user—designated speed.
`When the power-saving driver receives from the OS an OS
`termination start message representing the start of shutdown
`processing. [he power—saving driver cancels setting of the
`user-designated speed, and returns the CPU to, e.g., the
`highest speed. Hence, start processingtshuldown processing
`can be executed at a high speed regardless of the set value
`of [he user-designated speed.
`
`21 Claims, 16 Drawing Sheets
`
`USER—DES l GNATED
`SPEED IS SET
`
`SETTING OF USER-DESIGNATED
`SPEED IS CANCELED
`
`CPU SPEED
`
`HIGHEST SPEED
`
`USER—DES | GNATED SPEED
`
`: HIGHEST SPEED
`
`HIGHEST SPEED
`
`LOH SPEED
`
`
`
`
`
`:
`I
`
`08 START
`OS TERMINATION
`COMPLETION
`POWER OFF
`START MESSAGE
`:
`MESSAGE
`POKER 0N
`I———l—i——*—-—~—I—l
`08 START
`I
`03 SHUTDOIIN
`
`PROCESSING
`USER OPERABLE PERIOD
`PROCESSING
`"hv‘
`H W
`START
`PROCESSING
`SUCH AS APL
`
`TIME
`
`0001
`0001
`
`AMD EX1008
`AMD EX1008
`U.S. Patent No. 6,895,519
`US. Patent No. 6,895,519
`
`

`

`US. Patent
`
`4mm
`
`0
`
`US 6,681,336 B1
`
`
`
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`

`

`C) HIGHEST SPEED
`
`(3 HIGH SPEED
`
`C) MIDDLE SPEED
`
`C) LOW SPEED
`
`C) LOWEST SPEED
`
`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 2 0f 16
`
`US 6,681,336 B1
`
`CPU SPEED SETTING WINDOW
`
`CPU SPEED
`
`DESIGNATED:
`
`0003
`0003
`
`

`

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`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 4 0f16
`
`US 6,681,336 B1
`
`OS START
`PROCESSING-P
`START
`PROCESSING
`SUCH AS APL
`
`SET CALLBACK TIMER
`
`A11
`
`A13
`
`A
`
`14
`
`
`
`
`
`
`
`SET CPU SPEED TO USER-
`DESIGNATED PROCESSING
`SPEED USER USE
`
`USER USE
`
`A15
`
`OS TERMINATION MESSAGE
`(Sys_VM_Terminate)
`
`
`
`POWER—SAVING DRIVER
`
`POWER—SAVING DRIVER
`
`POWER—SAVING DRIVER
`
`POWER—SAVING DRIVER
`
`POWER ON
`
`
`
`
` POST PROCESSING
`(SET CPU SPEED T0
`HIGHEST SPEED)
`
`
`
`FIG.7
`
`E
`
`0005
`0005
`
`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 5 0f16
`
`US 6,681,336 B1
`
`OS
`
`POWER—SAVING
`DRIVING
`
`Hw
`(VIA BIOS OR DIRECTLY)
`
`Sys_Critical_lnit
`
`m E03
`
`
`
`:3
`LL!
`
`E7:
`%
`5:3
`
`C3
`UJ
`UJ
`CL
`00
`
`af—
`g(D
`EC:
`u':LU
`”:2
`
`C3
`UJ
`E09
`|._
`Q3:
`CD
`
`a
`
`CALL—BACK TIMER
`IS SET
`
`CPU SPEED IS
`SET TO USER-—
`
`DESIGNATED SPEED
`
`SYS—VM—Term'm'
`
`.
`
`CPU PE
`
`SET $0 E?GPIIEST
`
`SPEED
`
`
`
`FIG.6
`
`0006
`0006
`
`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 6 0f 16
`
`US 6,681,336 B1
`
`ms_H
`
`
`
`amh<zo_mmolmmm:omh<zo_mmolmmm:
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`
`
`
`

`

`US. Patent
`
`Jan. 20,2004
`
`Sheet 7 0f 16
`
`US 6,681,336 B1
`
`START OF SUSPEND
`
`A21
`
`SUSPEND START MESSAGE
`(APM_SUSPEND)
`
`Q§
`
`SUSPEND
`
`SET CPU SPEED T0
`HIGHEST SPEED
`
`A22
`
`A23
`
`POWER—SAVING DRIVER _
`
`CHANGE MACHINE T0
`SUSPEND STATE
`
`Q§
`BIOS
`
`RETURN FROM SUSPEND
`IN RESPONSE TO POWER
`BUTTON. ETC.
`
`A24
`
`A25
`
`BI S
`
`RETURN MESSAGE
`(APM_Resume_Suspend)
`
`95
`
`A26
`
`READ TIMER
`
`POWER:§AEJNG DRIVER
`
`RESUME
`
`A27
`
`SET CALLBACK TIMER
`
`POWER—SAVING_DRIMEB
`
`A28
`
`EQflER—SAVING DRIVER
`
`SET CPU SPEED TO
`USER—DESIGNATED
`PROCESSING SPEED
`
`END OF RETURN
`
`FIG.9
`
`0008
`0008
`
`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 8 0f16
`
`US 6,681,336 B1
`
`OS
`
`POWER—SAVING
`DRIVING
`
`HW
`(VIA BIOS 0R DIRECTLY)
`
`_
`
`APM_SUSPEND
`
`CPU SPEED IS
`SET TO HIGHEST
`
`USER—
`DESIGNATED
`
`SPEED
`
`HIGHEST
`SPEED
`
`- OFF
`
`
`APM_Resume_Suspend
`
`CALL—BACK TIMER
`Is SET
`
`HI
`EST
`39220
`
`CPU SPEED IS
`SET TO USER—
`DESIGNATED SPEED
`
`USER—
`DESIGNATED
`SPEED
`
`FIG.IO
`
`0009
`0009
`
`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 9 0f16
`
`US 6,681,336 B1
`
`“‘~— -~
`
`CPU SPEED IS SET
`T0 HIGHEST SPEED
`
`
`
`WM
`
`
`POWER 0N —*
`
`BIOS
`POST PROCESSING
`
`05
`BOOT PROCESSING
`
`03 OPERATION
`
`
`
`CPU:
`HIGHEST SPEED
`
`
`
`
`
`
`CPU=
`USEfifiDESIGNATED
`SPEED
`
`F |(3. I I
`
`0010
`0010
`
`
`
`WARNING EVENT
`
`SM! PROCESSING
`
`CPU SPEED IS
`DECREASED
`
`
`
`CPU=LOW SPEED
`
`
`
`

`

`US. Patent
`
`Jan. 20,2004
`
`Sheet 1001'16
`
`US 6,681,336 B1
`
`EXECUTE
`IN LOAD
`
`
`
`
`
`
` OS/DRIVER
`
`READ VALUE (TI) OF TIME STAMP COUNTER (TSC)
`
`aEmEmflmmmNM%NTmB
`
`READ VALUE (T2) OF TIME STAMP COUNTER (Tsc)
`
`CALCULATE TIME T PER INSTRUCTION JMP$
`(T2—TI)/N
`
`SAVE T AS REFERENCE VALUE OF LOOP
`COUNTER FOR COUNTING WAIT TIME
`
`FIG.12
`
`311
`
` BIZ
`
` 314
`
`
`
`3‘3
`
`BIS
`
`
`
`WARNING EVENT
`
`
`WARNING EVENT
`SHI PROCESSING
`
`321
`
`PROCESSING
`END ?
`
`NO
`
`
`
` OS BOOT
`YES
`
`
` TURN OFF AC
`
`
`
` FIG.I8
`
`322
`
`CHECK FACTOR ?
`
`ADAPTER
`
`TEMPERATURE RISE
`
`DECREASE CPU SPEED
`
`DECREASE CPU SPEED
`
`
`
`SET TIME—OUT FLAG TO "0N"
`
`0011
`0011
`
`

`

`US. Patent
`
`Jan. 20,2004
`
`Sheet 11 0f16
`
`US 6,681,336 B1
`
`
`
`BOOTPROCESSING
`
`8102
`
`START OS BOOT
`
`BIOS
`
`CONTINUE OS
`BOOT PROCESSING
`
`
`
`
`
`
`
`
`
`INSTALL DEDICATED
`Z UTILITY
`SM! BY
`UTILITY
`
`
`
`
`POST PROCESSING
`(SET CPU SPEED T0
`HIGHEST SPEED)
`
`
`
`WARNING €Y§.IIT.,(DECREASE :CPU SPEED)
`
`SMI PROCESSING #1
`
`3‘05
`III-III..-
`
`8104
`
`
`BIO? a
`SWITCH CPU SPEED i OS OPERATION
`
`SPEED-UP
`EVENT
`
`i
`
`SMI PROCESSING #2
`
` CHECK RUNNING OS
`03 CORRESPOND TO DYNAMIC
`SPEED—UP ?
`
`BIIO
`
`
`
`
`
`INCREASE CPU SPEED
`
`FIG.13
`
`0012
`0012
`
`

`

`US. Patent
`
`Jan. 20,2004
`
`Sheet 12 01‘16
`
`US 6,681,336 B1
`
`POWER ON —I-
`
`
`
`
`
`POST PROCESSMG
`(SET CPU SPEED T0
`HIGHEST SPEED)
`
`
`
`WARN ' “G a"-E—N-Ta-(DECREASE :CPU SPEED)
`
`
`
`I NSTALL/ACCESS
`DEDICATED DEVICE
`DR 1 VER
`
`
`
`BOOTPROCESSING
`
`
`
`
`
`SWITCH CPU SPEED
`
`
`
`OS OPERATION
`
`SPEED—UP
`EVENT
`
`5
`
`sm PROCESSING #2
`
`
`
` CHECK RUNNING OS
`08 CORRESPOND T0 DYNAMIC
`SPEED—UP ?
`
`
`
`
`I NCREASE CPU SPEED
`
`0013
`0013
`
`

`

`US. Patent
`
`Jan. 20, 2004
`
`Sheet 13 01'16
`
`US 6,681,336 B1
`
`
`
`BOOTPROCESSING
`
`POWER ON —*
`
`WARNING EVENT
`..... .SIDEcREASE:CPU SPEED)
`
`BIO]
`
`
`
`POST PROCESSING
`(SET CPU SPEED T0
`
`
`
`HIGHEST SPEED)
`
`3‘05
`SMI PROCESSING #1
`
`Ill-ll...-
`
`
`
`CHECK USER—DESIGNATED
`SPEED
`
`
`
`
`KB INPUT
`BY USER
`
`
`
` BIO?
`
`
`
`WARNINQ EVENT
`3108
`'4
`
`
`
`OS OPERATION
`
`E
`
`SNI PROCESSING #2
`
`SPEED-UP
`EVENT
`
` CHECK RUNNING 08
`OS CORRESPOND T0 DYNAMIC
`SPEED—UP ?
`
`
` BIIO
`
`
`
`INCREASE CPU SPEED
`
`F:I(3.'IES
`
`0014
`0014
`
`

`

`US. Patent
`
`Jan. 20,2004
`
`Sheet 14 01‘16
`
`US 6,681,336 B1
`
`
`
`
`POST PROCESSING
`(SET CPU SPEED T0
`HIGHEST SPEED)
`
`START OS BOOT
`
`WARNING Eygflt>(DECREASE:CPU SPEED)
`I
`
`CONT'NUE OS
`BOOT PROCESSING
`
`PROCESSING
`BOOT
`
`INSTALL DEDICATED
`UTILITY
`
`8301
`
`3106
`3107
`
`EEEIE
`'Iflaallllll
`WARNINgS EVENT I
`
`SWITCH CPU SPEED
`
`03 OPERATION
`
`SPEED—UP
`EVENT
`
`E
`
`SNI PROCESSING #2
`
` CHECK RUNNING OS
`08 CORRESPOND TO DYNAMIC
`SPEED—UP ?
`
`
`
`
`
`INCREASE CPU SPEED
`
`5
`
`IFIG.16
`
`0015
`0015
`
`

`

`US. Patent
`
`Jan. 20,2004
`
`Sheet 15 01'16
`
`US 6,681,336 B1
`
`POWER ON—’-
`
`
`
`POST PROCESSING
`
`:
`
`SET CPU SPEED TO
`HIGHEST SPEED
`
`START OS BOOT
`
` B402
` B403
`
`
`CONTINUE OS
`BOOT PROCESSING
`
`B404
`
`WARNING EVENT------------------ *-(DECREASE CPU SPEED)
`
`B405
`
`CHECK USERuDESIGNATED SPEED
`
`END OF BOOT
`
`B406
`
`B407
`
`
`
`N0
`
`YES
`
`B408
`
`
`
`SWITCH CPU SPEED
`
`
`
`
`
`
`HIGHEST SPEED? a
`
`
`INCREASE CPU SPEED
`
`SPEED—UP EVENT
`
`
`
`CHECK RUNNING 08
`OS CORRESPOND T0 DYNAMIC
`SPEED-UP'?
`
`FIG.17
`
`0016
`0016
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 16 0f 16
`
`US 6,681,336 B1
`
`CPU=USEH~
`DESIGNATED SPEED
`
`OS OPERATION
`
`SHUTDOWN EVENT
`
`
`‘
`
`T0 HIGHEST SPEED
`
`CPU SPEED IS SET
`
`SHUTDOWN
`PROCESSING
`
`CPU = HIGHEST
`SPEED
`
`POWER OFF
`
`FIG.19
`
`0017
`0017
`
`

`

`US 6,681,336 B]
`
`l
`SYSTEM AND METHOD FOR
`IMPLEMENTING A USER SPECIFIED
`PROCESSING SPEED IN A COMPUTER
`SYSTEM AND FOR OVERRIDING THE
`USER SPECIFIED PROCESSING SPEED
`DURING A STARTUP AND SHUTDOWN
`PROCESS
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is based upon and claims the benefit of
`priority from the prior Japanese Patent Applications No.
`11—173015, filed Jun. 18, 1999; and No. 11—2997th, filed
`Oct. 21, 1999, the entire contents of which are incorporated
`herein by reference.
`
`BACKGROUND 017 TIIE INVEN'I'ION
`
`The present invention relates to a computer system such
`as a personal computer and, more particularly, to a computer
`system capable of setting the processing speed to a process—
`ing speed designated by user operation, and a processing
`speed control method therefor.
`In recent years, various portable laptop or notebook type —
`battery-operable personal computers (to be referred to as
`PCs hereinafter) have been developed. For PCs of this type,
`high-speed (high-performance) CPUs have been developed.
`This allows the user to easily obtain a comfortable use
`environment.
`
`3-0
`
`However, a higher-speed CPU requires higher power
`consumption, increasing the power consumption amount of
`the whole PC and decreasing the battery operating time.
`Recently, in order to save power, a technique for setting
`the processing speed of the system to a predetermined
`processing speed designated by user operation has been
`developed. The processing speed of the system can be set to
`one of a plurality of speed levels from the highest to lowest
`speeds by, e.g., intermittently operating the CPU at a pre-
`determined period or switching the operating frequency or
`voltage of the CPU. Which of speed levels is to be used
`during the user job period is determined by user's designa-
`tion.
`
`However, in a conventional system, the processing speed
`designated by user operation effectively acts even during a
`period in which the user cannot actually operate the com-
`puter system, for example, during the start or shutdown
`period of the computer system. For this reason, start or
`shutdown processing of the computer system requires a long
`time.
`
`When the CPU speed is switched to the highest speed by
`user’s designation or another predetermined factor after the
`CPU operates at a low speed during system start processing,
`normal operation may not be assured depending on the
`operating system or drivers. This is because most of oper-
`ating systems and drivers obtain an absolute time necessary
`for a device response wait by software using a software loop
`counter.
`
`More specifically, the operating system or driver calcu—
`lates and registers in system start processing a time neces-
`sary for repetitively executing a specific instruction N times.
`In actually accessing a device,
`the repetitive execution
`number of the instruction necessary for a device response
`wait is determined using the registered information. If the
`CPU speed is set, e.g., twice as high as the speed in system
`start processing,
`the actual wait
`time becomes half the
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`expected value even when the specific instruction is repeti-
`tively executed the same number of times. To normally
`operate a device, at least a wait time equal to or longer than
`the wait time defined by the device must be assured.
`Even if system start processing is executed at a CPU
`speed which is not the highest, and then the CPU speed is
`increased by user's designation or another predetermined
`factor, device operation fails. In some cases, a serious error
`occurs such that an instruction or data cannot be normally
`read.
`
`BRIEF SUMMARY OF THE INVENTION
`
`it is an object of the present invention to
`Accordingly,
`provide a computer system for implementing high-speed
`start processing or the like, and a CPU speed control method
`therefor.
`
`15
`
`It is another object of the present invention to provide a
`computer system for improving the reliability of system
`operation, and a CPU speed control method therefor.
`According to one aspect of the present invention, there is
`provided a computer system comprising: means for desig-
`nating a user to designate a processing speed of a processor;
`means for controlling the processing speed of the processor;
`and means for setting the processing speed by the means for
`controlling, setting the processing speed to a highest speed
`during a period for start processing of an operating system
`for the computer system, and the processing speed to the
`user-designated speed during a period other than that for the
`start processing of the operating system.
`invention,
`According to another aspect of the present
`there is provided a computer system comprising: means for
`designating a user to designate a processing speed of a
`processor; means for setting the processing speed of the
`processor; and means for setting the processing speed by the
`means for controlling, setting the processing speed to a
`highest speed during a period for shutdown processing}
`suspend processing of the computer system, and the pro—
`cessing speed to the user-designated speed during a period
`other than that for the shutdown processingfsuspend pro-
`cessing.
`According to still another aspect of the present invention,
`there is provided a processing speed control method applied
`to a computer system, comprising the steps of: designating
`a user to designate a processing speed of a processor; and
`operating the processor at :1 highest speed during a period for
`start processing of an operating system for the computer
`system, and operating the processor at the user—designated
`speed during a period other than that for the start processing
`of the operating system.
`According to still another aspect of the present invention,
`there is provided a processing speed control method applied
`to a computer system, comprising the steps of: designating
`a user to designate a processing speed of a processor; and
`operating the processor at a highest speed during a period for
`shutdown processing-“suspend processing of the computer
`system, and operating the processor at the user-designated
`speed during a period other than that for the shutdown
`pmcessingisuspend processing.
`Additional objects and advantages of the invention will be
`set forth in the description which follows, and in part will be
`obvious from the description, or may be learned by practice
`ofthe invention. The objects and advantages of the invention
`may be realized and obtained by means of the instrumen-
`talities and combinations particularly pointed out hereinaf~
`ter.
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`
`The accompanying drawings, which are incorporated in
`and constitute apart ofthe specification, illustrate presently
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`US 6,681,336 B1
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`3
`preferred embodiments of the invention. and together with
`the general description given above and the detailed descrip-
`tion of the preferred embodiments given below, serve to
`explain the principles of the invention in which:
`FIG. 1 is a block diagram showing the arrangement of a
`computer system common to both the first and second
`embodiment of the present invention;
`FIG. 2 is a view showing an example of a CPU speed
`setting window for the user in the first embodiment;
`FIG. 3 is a view for explaining the principle of system
`control method used in the first embodiment;
`FIGS 4A and 4B are block diagrams each showing the
`logical relationship between a power—saving driver, 08,
`BIOS, and hardware used in the first embodiment;
`FIG. 5 is a flow chart showing the flow of a series of
`control operations executed from the start to the termination
`of the system in the first embodiment;
`FIG. 6 is a view showing a processing sequence when
`attention is given to exchange of messages between the OS
`and power-saving driver used in the system of the first
`embodiment;
`FIG. 7 is a flow chart showing processing procedures
`when the CPU processing speed in start processing is set to
`the highest speed by a BIOS used in the system of the lirst
`embodiment;
`FIG. 8 is a view for explaining the principle of system
`control method in suspendiresume processing in the system
`of the first embodiment;
`FIG. 9 is a flow chart showing the flow of a series of
`control operations executed in suspendfresume in the system
`of the first embodiment;
`FIG. 10 is a view showing a processing sequence when
`attention is given to exchange of messages between the OS
`and power—saving driver used in the first embodiment;
`FIG. 11 is a view for explaining the principle of system
`control method used in the second embodiment of the
`present invention;
`FIG. 12 is a flow chart showing an example of software
`loop counter setting processing executed by an OS or driver
`used in the second embodiment in loading the OS or drive
`FIG. 13 is a flow chart showing the first example for
`implementing the system control method of the second
`embodiment
`
`FIG. 14 is a flow chart showing the second example for
`implementing the system control method of the second
`embodiment;
`FIG. 15 is a [low chart showing the third example for
`implementing the system control method of the third
`embodiment;
`FIG. 16 is a low chart showing the fourth example for
`implementing the system control method of the fourth
`embodiment;
`FIG. 17 is a [low chart showing the fifth example for
`implementing the system control method of the fifth
`embodiment;
`FIG. 18 is a flow chart showing the procedures of warning
`event SMI prtwcssing used in the second embodiment; and
`FIG. 19 a view showing CPU speed control during
`shutdown processing in the second embodiment.
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`Preferred embodiments of the present invention will be
`described below with reference to the several views of the
`
`accompanying drawing.
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`I shows the arrangement of a computer system
`FIG.
`common to both the lirst and second embodiments of the
`present invention.
`This computer system is a battery—operable notebook type
`personal computer (PC). When power is externally supplied
`via an AC. adapter 181, the PC operates by the external
`power, and a battery 182 is charged. When the AC adapter
`181 is not connected to the PC main body, e.g.. the PC is
`used in a mobile environment, the PC operates by power
`from the battery 182.
`the PC main body includes a
`As shown in FIG. 1,
`processor bus 1, PCI bus 2, ISA bus 3. CPU 11, host-PCI
`bridge 12, main memory 13, display controller 14, PCI-ISA
`bridge 15, U0 controller 16, BIOS-ROM 17, power supply
`controller 18, keyboard controller (KBC) I9. and CMOS
`memory 20.
`The CPU 11 controls the operation of the whole PC, and
`executes the BIOS in the BIOS-ROM 17, an operating
`system loaded to the main memory 13, and various other
`programs. This system can control the processing speed of
`the CPU 11 at multiple stages (a plurality of levels). The
`CPU speed is controlled using a CPU throttling function (to
`be described later) and a function called a speed~step or
`GEYS ERVI LLE function.
`
`The CPU speed level to be used is determined by user’s
`designation or another predetermined factor. This system
`operates the CPU 11 at a predetennined arbitrary processing
`speed (e.g., highest speed) regardless of the user-designated
`processing speed during a period except for a user operable
`period. The CPU speed variably-setting function will be
`described in detail below.
`
`The CPU 11 in FIG. 1 includes the following system
`management functions.
`That is, the CPU 11 includes a real mode. protected mode,
`and virtual 86 mode for executing an application program or
`a program such as an OS, and in addition an operation mode
`called a system management mode (SMM) for executing a
`system management program.
`In the real mode, a maximum ofa l-Mbyte memory Space
`can be accessed. A physical address is determined by an
`offset value from a base address represented by a segment
`register. In the protected mode, a maximum of a lfi-Mbyte
`memory space can be accessed. A linear address is deter
`mined using an address mapping table called a descriptor
`table. This linear address is finally converted into a physical
`address by paging. In the virtual 86 mode, a program written
`to operate in the real mode is operated in the enhanced mode.
`A program in the real mode is processed as one task in the
`enhanced mode.
`
`The system management mode (SMM) is a pseudo teal
`mode in which no descriptor table is referred to and no
`paging is executed. When a system management interrupt
`(SMl) is issued to the CPU 11, the operation mode of the
`CPU 11 is switched from the real, protect, or virtual 86 mode
`to the SMM. In the SMM, a system management program is
`executed.
`
`The SMI is a kind of non-maskable interrupt NMI. which
`is an interrupt having the highest priority, compared to a
`normal NMI or maskable inten'upt lNTR. This SMI can be
`issued to start various SMI service routines prepared as
`system management programs independently of a Winning
`application program or the 08 environment.
`The host-PCI bridge 12 is a bridge device for bidirection-
`ally connecting the CPU bus 1 and PCI bus 2. The host-PCI
`bridge 12 incorporates a memory control
`function for
`access-controlling the main memory 13.
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`US 6,681,336 B1
`
`5
`The main memory 13 stores an operating system, appli-
`cation programstutilities to be processed, drivers, data cre-
`ated by these programs, and the like. When the CPU 11
`shifts to the SMM, the CPU status, i.e., the register of the
`CPU 11 upon generation of an SMI is saved with a stack
`format in an SMRAM mapped into a predetermined address
`space in the main memory 13. This SMRAM stores an
`instruction for calling the system management program of
`the BIOS-ROM 1?. This instruction is executed first when
`the CPU 11 shifts to the SMM. By executing this. instruction,
`the control shifts to the system management program.
`The display controller 14 displays display data stored in
`an image memory (VRAM) 141 on one or both of an LCD
`142 and external CR‘I‘ 143 attached to the PC main body. The
`display controller 14 can operate as the bus master of the
`PCI bus 2.
`
`The PCI-ISA bridge 15 connects the PCI bus 2 and ISA
`bus 3, and can operate as the bus master of the PCI bus 2.
`The POI-ISA bridge 15 includes an SMI generation circuit
`151 and CPU speed control circuit 152.
`The SMI generation circuit 151 generates an SMI signal
`to the CPU 11. The SMI signal is generated by a software
`SMI, an 110 trap SMI, or an SMI caused by a specific
`hardware event.
`
`The software SMI is generated using a register or down
`counter accessible by software. That
`is, when software
`writes data in the internal register of the SMI generation
`circuit 151, an SMI signal
`is generated. Further, when a
`value corresponding to a time till generation of an SMI
`signal
`is set
`in the internal down counter of the SMI
`generation circuit 151, an SMI signal is generated in time—
`out.
`
`The IEO trap SMI is generated by executing an IN or OUT
`instruction by software using a predetermined IiO address.
`An lr’O address value to be monitored at which an [3‘0 trap
`SMI is wanted to be generated is set in the SMI generation
`circuit 151. Then, when this It'O address is accessed, the HO
`trap SMI can be generated.
`The SMI by a specific hardware event is generated by
`hardware upon occurrence of an event necessary for system
`management, e.g., upon a change in CPU temperature or
`inscrtiontremoval of the AC adapter 181.
`The CPU speed control circuit 152 controls the processing
`speed of the CPU 11, and has a throttling controller for
`switching the CPU speed using the "CPU throttling
`function“, and a frequencyflvoltage controller for switching
`the CPU speed using the “GEYSERVILLE” function.
`These functions are used to variably set
`the processing
`speed of the CPU 11 using the “CPU speed variably-setting
`function“ according to the present invention.
`
`1) “CPU Throttling Function”
`
`The “CPU throttling fir nction" is a function of switching
`the average CPU processing speed by performing intermit-
`tent operation of operatingtstopping the CPU 11 at a prede-
`termined interval. This function may be called an interval
`stop clock function or intermittent operation function.
`Astate in which the “CPU throttling function" is disabled,
`i.c., the CPU It always operates corresponds to the highest
`speed of the CPU 11. Astate in which the "CPU throttling"
`is enabled at an arbitrary % (ratio of the stepped state to the
`operating state) corresponds to a speed which is not
`the
`highest speed. By changing the ratio of the stopped state to
`the operating state,
`the CPU speed can be controlled at
`multiple stages.
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`In this system, a state in which the CPU [1 always
`operates is defined as a default state. The CPU 11 always
`operates at
`the highest speed until
`the "CPU throttling"
`starts. The operatingfstopped state of the CPU 11 is switched
`using a stop clock signal (STPCLK). The stop clock signal
`(S'I‘PCLK) is a clock state control signal supported by CPU
`486SL or Pentium“ available from INTEL Corp.
`
`2) "GEYSERVII..LE Function"
`The “GEYSERVIIJE function“ is the function of CPU
`
`MobilePentiumlITM available from INTEL Corp, and
`dynamically switches the operating frequency and voltage of
`the CPU. A state in which the operating frequency and
`voltage are set
`to high-order ones supported by the CPU
`corresponds to the highest speed of the CPU. A state in
`which the operating frequency and voltage are set to low—
`order ones corresponds to a speed which is not the highest
`speed.
`In the use of either the function I) or 2), the CPU speed
`can be switched by writing necessary data in the internal
`register of the CPU speed control circuit 152.
`The PCI-ISA bridge 15 has a function of monitoring the
`CPU temperature using a temperature sensor 21 and its drive
`circuit 22, and a function of monitoring insertion!rremoval of
`the AC adapter via the poorer supply controller 18. When the
`CPU temperature reaches a predetermined temperature or
`more, or the AC adapter is removed to turn off the AC
`adapter power supply, the PCI-ISA bridge 15 notifies the
`system BIOS by an SMI of occurrence of a warning event
`which influences the safety of system operation. In this case,
`processing of forcibly decreasing the CPU speed is done
`under the control of the system BIOS.
`The It'O controller 16 incorporates a bus master IDE
`controller for controlling an IDE device such as an HDI)
`161. The bus ntaster IDE controller can operate as a bus
`master for data transfer between the IIDD 161 and the main
`memory 13. The NO controller 16 can also control DVD and
`(ID-ROM drives. The IIDD 161 records setting information
`managed by the operating system, in addition to various
`programs and data.
`The BIOS-ROM 17 stores a system BIOS (Basic Input;f
`Output System), and is constituted by a flash memory so as
`to rewrite a program. The system BIOS operates in the real
`mode. This system BIOS includes a POST (Power-On Self
`Test) routine executed in powering on or restarting the
`system, a device driver for controlling various It'O devices,
`a BIOS setup routine for setting the system environment,
`and a system management program ( run time) for executing
`various SMI processes.
`The BIOS setup routine presents to the user a setup
`window including various setting items such as setting of the
`CPU speed, thereby setting the system to a user-designated
`environment.
`
`The power supply controller 18 controls power-onioff
`operation of the PC, and has a state monitoring function of
`monitoring ONg‘OFF operation of a power switch 183, the
`residual capacity of the battery 182, insertionlremoval of the
`AC adapter 181, and ONIOFF operation of the openr‘close
`detection switch of the display panel.
`The keyboard controller (KBC) 19 controls the keyboard
`and mouse. The CMOS memory 20 holds various pieces of
`system setting information, and is backed up by its own
`battery. CPU speed information designated by the user is
`saved in, e.g., the CMOS memory 20.
`The above-described arrangement is common to both the
`first and second embodiments.
`
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`US 6,681,336 B1
`
`7
`Next, the arrangement related to the first embodiment will
`be described below.
`
`In the first embodiment, variable setting of the processing
`speed of the CPU 11 in the CPU speed control circuit 152 is
`executed by, e.g., a power-saving driver (program) which
`runs on the operating system. This power-saving driver
`originally sets the processing speed of the CPU 11 to a
`user-designated speed. In the first embodiment, the power-
`saving driver has the above-mentioned CPU speed variably-
`setting function of operating the CPU 11 at a predetermined
`arbitrary processing speed (e.g., highest speed) regardless of
`the user-designated processing speed during a period except
`for a user operable period. The power—saving driver controls
`the CPU speed control circuit 152 via the system BIOS or
`directly without the mediacy of the system BIOS.
`Setting processing of the CPU speed by the user may be
`done using the above-described BIOS setup routine. The
`first embodiment assumes. that setting processing of the CPU
`speed by the user is done using the power-saving driver. In
`practice. the power-saving driver itself does not present a
`setting window including various power-saving setting
`items to the user, but a setting window like the one shown
`in FIG. 2 is presented via a dedicated program such as a
`power-saving utility. CPU processing speed information set
`by GUI operation by the user is recorded in a predetermined
`area (e.g., registry area) of the Mm) 161 to which the
`power-saving driver can refer.
`<Principle of System Control Method in First Embodiment)
`The principle of system control method used in the first
`embodiment will be explained with reference to FIG. 3.
`If a system start event (power-on operation, reset, restart,
`or the like) occurs, POST processing (hardware check and
`initialization processing) is executed by the system BIOS,
`and start processing (OS bootstrap sequence) of the operat-
`ing system (OS) starts. At this time, the CPU 11 operates at
`a predetermined default speed. In the first embodiment, the
`highest speed is selected as the default speed of the CPU 11,
`and the CPU It automatically operates at the highest speed
`until the power-saving driver performs setting processing.
`The OS bootstrap sequence has several stages. Start
`processing of the OS itself is completed via load of a kernel,
`load of various device drivers, and their initialization pro-
`cessing. In loading device drivers, the power—saving driver
`of this embodiment is also loaded.
`The power—saving driver detects completion of start pro
`cessing of the OS itself upon reception of a start completion
`message from the OS. The start completion message
`changes depending on the type of OS in use. In many cases,
`a plurality of messages are issued from the OS at an interval
`in accordance with the stage of start processing. Thus, the
`final detectable message is detected as an OS start comple—
`tion message. For example, in Windows 9538““ avail