O
`(12) United States Patent
`(16) Patent N0.:
`US 6,665,802 B1
`
`Ober
`(45) Date of Patent:
`Dec. 16, 2003
`
`USOO6665802B1
`
`5,041,964 A
`5,083,266 A
`5,142,684 A
`
`.................. 364/200
`8/1991 Cole et al.
`.. 395/275
`1/1992 Watanabe .....
`
`. 395/750
`8/1992 Perry et al.
`
`.....
`. 395/375
`11/1992 Smith et al.
`5,167,024 A
`. 395/750
`6/1993 Watts, Jr. et al
`5,218,704 A
`.......
`. 395/750
`8/1993 Cole et a1.
`5,241,680 A
`
`
`. 364/489
`.
`4/1994 Storandt et al.
`5,307,285 A
`.
`9/1994 Hopkins et al.
`360/71
`5,345,347 A
`
`,,,,,
`, 395/750
`10/1994 soffe] et a1,
`5,355,503 A
`3/1995 Fung ........................... 39/800
`5,396,635 A
`4/1995 Stewart
`...................... 395/750
`5,404,546 A
`4/1995 Blood et al.
`..
`. 379/147
`5,410,590 A
`6/1995 Kannan et a1.
`. 395/750
`5,423,045 A
`6/1995 Walker et al.
`307/64
`5,428,252 A
`9/1995 Yach etal.
`. 395/750
`5,454,114 A
`-
`“1996 Brown et al-
`- 395/750
`52481739 A
`“996 Stewart et al' """"""" 395/750
`5504390? A
`4/1996 Kannan ct al.
`............. 395/750
`5,511,205 A
`
`.. 395/750
`8/1996 Pierce
`5,546,390 A
`2/1997 Pierce et a1.
`................ 395/750
`5,606,704 A
`9/1998 Diewald
`5,805,909 A
`7/1999 Yoshida ...................... 713/324
`5,928,363 A *
`9/2000 Velasco et al.
`. 713/322
`6,115,823 A *
`
`2&3332 31 : $83: if e‘ :1“ {"i‘
`‘ 710/222
`=
`7
`erg“ e a‘
`FOREIGN PATENT DOCUMENTS
`_
`0 /08 398 A2
`EP
`* cited by examiner
`.
`.
`.
`.
`Prtmary Exam‘mr—Dem“? M‘ Elmer
`(74) Attorney, Agent, or Fer—Fish & Richardson P.C.
`(57)
`ABSTRACT
`
`..
`
`
`
`4/1995
`
`A power management system for a microcontroller. The
`power management system includes a power management
`state machine for controlling a power mode of a central
`processing unit (CPU) and each subsystem within the micro-
`controller. Each microcontroller subsystem is connected to
`.
`.
`the systemthrough a configurable peripheral interface (FPI).
`Each FPI includes a software configuration register.(SER)
`that can be configured by an Operatmg System Of apphcatlon
`program. The SFR for the various FPIs can be preconfigured
`to allow the response to each of the power modes of the
`power management state machine to be independently con-
`trolled for each subsystem.
`
`24 Claims, 4 Drawing Sheets
`
`(54) POWER MANAGEMENT AND CONTROL
`FOR A MICROCONTROLLER
`
`(75)
`
`Inventor: Robert E. Ober, San Jose, CA (US)
`
`(73) Assignee:
`
`Infineon Technologies North America
`Corp., San Jose, CA (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U .S.C. 154(b) by 0 days.
`
`(21) Appl. No.1 09/516,447
`-
`,
`Feb' 29’ 2000
`Ffled‘
`(22)
`Int. Cl.7 .................................................. G06F 1/32
`(51)
`(52) US. Cl.
`........................................ 713/320; 713/324
`
`58) Field of Search
`713/300 310
`(
`I
`’
`’
`’
`713329 323> 324
`
`(56)
`
`References Cited
`, H
`,
`,
`‘
`,
`,
`‘
`V
`‘
`U~5~PAUIN1 DOLUMleb
`4,128,771 A
`2/1978 Domenico ................... 307/52
`4,151,611 A
`4/1979 Sugawara etal.
`.......... 365/227
`4,204,249 A
`5/1980 Dye et al. ................... 364/200
`4,293,927 A
`0/1981 Hoshii
`364/900
`4,317,180 A
`2/1982 Lies ......
`364/707
`4,317,181 A
`2/1982 Teza et al.
`364/707
`4,365,290 A
`2/1982 Nelms et al.
`364/200
`.
`4,381,552 A
`4/1983 Nocilini et al.
`364/900
`
`4,409,665 A
`0/1983 Tubbs
`________________________ 364/707
`4,422,163 A
`2/1983 Oldenkamp ................. 365/229
`4,611,289 A
`9/1986 Coppola .........
`364/492
`4,615,005 A
`9/1986 Maejima et al.
`.. 364/200
`4,665,536 A
`5/1987 Kim ......
`. 377/16
`-
`49698748 A
`0/1987 JUZSWik et al-
`-- 364/200
`47719463 A
`2(1987 Stacy 6t a1~ ~~~~~
`358/:190
`4’787’041 A
`5/,1988 Engel 8t a1.
`364’200
`4,738,945 A
`7/1988 Remedi
`364/200
`4,780,843 A
`0/1988 Tietjen ...........
`364/900
`4,809,163 A
`2/1989 Hii‘osawa et a1.
`........... 364/200
`4,823,292 A
`4/1989 Hillion ....................... 364/707
`4,843,592 A
`6/1989 Tsuaki et a1,
`364/900
`
`7/1989 Day ...............
`.. 364/200
`4,851,987 A
`3/1990 Arroyo et al.
`..
`4,907,150 A
`364/200
`
`379/98
`8/1990 Gross et al.
`4,951,309 A
` 12/1990 Carter et al.
`364/483
`.
`4,980,836
`5,025,387
`6/1991 Franc ......................... 364/493
`
`
`
`
`
`
`
`AA
`
`54v Mammy
`58x DRAM Retresh
`
`22\
`
` 31in
`(24
`
`
`
`
`
`92
`
`
`Fil’BUS
`>
`
`
`
`
`
`
`
`:1FPI
`tr
`
`
`
`
`AppSpeufic
`
`Peripheral
`l 40
`
`
`JTAG
`I
`
`52
`38
`
`
`
`
`
`ICU
`67
`60 ~ DRAM Relresh
`
`56 2 Memory
`
`I
`
`aa\
`
`PORTS
`42 FPI
`
`32 \
`I DMA/PCPI
`44 FPI
`
`34 \
`$2:er
`46 FPI
`
`JTAG
`EEC
`FPI
`
`l
`
`4a
`
`
`
`36
`
`f 20
`
`Maln Crystal
`
`F6»?
`
`NMI, Fault etc.
`
`0001
`0001
`
`AMD EX1004
`AMD EX1004
`U.S. Patent No. 6,895,519
`US. Patent No. 6,895,519
`
`

`

`US. Patent
`
`Dec. 16, 2003
`
`Sheet 1 0f 4
`
`US 6,665,802 B1
`
`G<
`
`3
`
`aa
`'”
`2
`.3
`u.
`E22
`
`a:
`IOCL
`
`3
`m
`E"
`o
`=
`“:6
`E
`
`‘—-
`.
`( £5
`.—
`LL
`
`CD
`N
`
`\
`
`V
`
`N
`
`co
`00
`
`‘5
`Is 8 E
`W
`LLI
`“-F-
`D-
`3|»-
`
`Ll
`
`$9 4-
`Q)
`E5 9—b-
`:30): col.-
`V"
`
`D.
`II
`E
`cu
`E
`m g LL»-
`0 “lb-
`‘r
`
`$2 _.I
`(5
`lg n:
`a.
`7 0 LL)-
`CL
`>-
`g’lb-
`
`
`
`
`
`
`
`.2_
`to:
`
`332 3
`U).E-l—.
`€1.33
`fl
`QCL
`N
`<
`LO
`
`gg
`=3
`(U:—
`cv—
`“co
`”’0-
`
`0
`
`-—
`g
`I
`_1 m
`.s:
`O—JE
`8“ 8
`O
`
`J:
`U?
`93
`a.
`75
`c,
`CC
`E
`:E
`“D
`3:: E
`0
`
`56
`
`OC
`
`O
`
`2
`(\1
`5-2 “3'
`
`
`
`
`
`
`
`>2
`3123'
`a:
`CL 0°
`a LLE
`(J
`._
`&
`
`NN
`
`5
`co
`a .‘i.’
`C)
`a:
`E
`(I
`a:
`:E
`E E
`o
`
`54
`
`58
`
`OC
`
`O
`
`0002
`0002
`
`

`

`US. Patent
`
`Dec. 16, 2003
`
`Sheet 2 0f 4
`
`US 6,665,802 B1
`
`x020Hog;
`
`55
`
`6QOBasra”.
`
`
`
`ammom_o”:bm.
`
`Pa#8215
`
`3520gas.
`qvm
`8:23:5088
`
`”fig
`
`mm
`
`Em
`
`m:m_mu
`
`mm3222
`
`5:8
`
`35QO
`
`on_'-'ll-lEI32%
`
`cm
`
`25
`
`m.9”—
`
`
`
`.05:23.32SmogEmma:
`
`
`
`
`0003
`0003
`
`
`
`
`
`

`

`U.S. Patent
`
`Dec. 16, 2003
`
`Sheet 3 0f 4
`
`US 6,665,802 B1
`
`System
`Clock
`
`Management
`Clock
`
`/ 54
`
`Management Clock
`
`108
`
`
`
`106
`
`104
`
`
`Optional
`Real Tame Clock
`
`Oscillator
`
`Oscillator
`
`
`
`
`
`
`Main Crystal
`
`32 kHz Crystal
`
`FIG. 3
`
`31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
`
`DivClk
`
`PSSM
`
`1514131211109876543 210
`“HI-lull
`
`K116
`
`FlG 4
`
`UPC SME
`
`/ 62
`
`31
`
`30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
`Im—
`
`1
`0
`1514131211109876543 2
`mm—
`
`FIG. 5
`
`0004
`0004
`
`

`

`US. Patent
`
`Dec. 16, 2003
`
`Sheet 4 of 4
`
`US 6,665,802 B1
`
`
`.
`Want for
`
`
`interrupt or
`Watchdog
`
`
`
`Power Management State Machine
`
`IDLE = True
`134
`
`Idle
`REQUESI
`
`Watchdog or
`Interrupt
`
`132
`
`Timeout or
`Osc/PLL 0K
`
`/ 130
`
`Negation
`of Reset
`(PORST)
`
`1 48
`
`144
`
`@
`
`Fautt
`
`Timeout
`
`
`or
`Power OK
`
`
`
`142
`
`Fault
`
`
`- POWERUP
`
`Wait for
`
`
`
`
`(Interrupt & IFauIt)
`0R
`Soft Reset
`OR
`Watchdog & Contig
`
`Qurescant
`
`System
`
`START
`SH UTDOWN
`
`Request
`
`136
`
`146
`
`FA“ LT
`
`138
`
`SHUTDOWN
`
`140
`
`SLEEP
`(DEEP SLEEP)
`.
`Wait
`for
`Interrupt
`
`FIG. 6
`
`0005
`0005
`
`

`

`US 6,665,802 B1
`
`1
`POWER MANAGEMENT AND CONTROL
`FOR A MICROCONTROLLER
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a power management
`system for a microcontroller that provides decentralized
`power management of the microcontroller subsystems while
`providing a modular architecture that can be used for
`microcontrollers having different numbers of subsystems
`and more particularly to a modular power management
`architecture for a microcontroller which includes a power
`management state machine for controlling the power modes
`of the various microcontroller subsystems as well as a
`programmable peripheral
`interface for each of the sub-
`systems which allows the response of the various sub—
`systems to the various power modes to be preconflgured,
`thereby providing optimal power management of the sub-
`systems.
`2. Description of the Related Art
`Various microcontrollers are used in numerous portable
`battery powered devices, such as portable personal comput—
`ers and cellular phones. An important concern in any por-
`table battery powered device is extending the amount of
`time the device can be used before the battery requires
`recharging. It is known to provide power management of the
`various subsystems within such portable devices in order to
`conserve battery power. Computer systems, for example, as
`disclosed in US. Pat. No. 4,980,836, utilize centralized
`power management control of various peripheral devices,
`such as the floppy disk drive and hard disk drive in order to
`conserve battery power. More particularly,
`in the system
`disclosed in the ”836 patent, accesses to the various periph—
`eral devices, such as the floppy disk drive and the hard disk
`drive are monitored. If the peripheral devices have not been
`accessed for a predetermined amount of time, the computer
`system including the peripherals are placed in a low power
`state by way the centralized power management control
`logic. In such a low power state, the system clock frequency
`may be either stopped or reduced in order to reduce the
`power consumption of the device. By stopping the system
`clock, the power consumption is significantly reduced since
`CMOS devices, typically used in such applications, utilize
`extremely low power at zero frequency. Other known com-
`puter power management systems are disclosed in US. Pat.
`Nos. 4,611,289; 4,041,964; 5,218,704; 5,396,635; and
`5,504,907.
`The drawbacks of centralized power management control
`for peripheral devices are recognized by peripheral device
`manufacturers. In particular, it is recognized that the power
`management of a particular peripheral for a computer sys-
`tem may be best optimized at the peripheral device itself.
`Thus, various peripheral manufacturers have developed
`decentralized power management systems for various
`peripheral devices in order to optimize battery power con-
`servation. For example, US. Pat. No. 4,151,611 discloses a
`power management system for memory systems. US. Pat.
`No. 4,951,309 discloses a power management system for a
`modem. US. Pat. No. 5,345,347 discloses a power manage-
`ment system for a disk drive. US. Pat. Nos. 5,546,590 and
`5,606,704 disclose power management system for PC MCIA
`cards.
`
`As mentioned above, microcontrollers are used in various
`applications for portable devices, such as cellular phones
`and automotive systems. In all such applications, there is an
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`0006
`0006
`
`2
`ever increasing trend to reduce the size of the device. For
`example, in newer cellular phone systems, unlike the “bag"
`phones in which the battery is carried in a bag separate from
`the phone, the newer portable cellular telephone include an
`integral battery and are becoming smaller and smaller. As
`such, reduction of the size of the cellular phone typically
`results in a reduction of the battery size. In general, for a
`given battery chemistry, for example, nickel cadmium or
`nickel metal hydride, reducing the size of the battery results
`in a reduced battery capacity. As such, reduced cellular
`phone size and increased battery capacity have become
`competing design tradeoffs in such devices. In order to
`optimize the tradeoff, power management techniques, uti-
`lized on a system level, for example, for computer systems,
`as discussed above, have been implemented on a microcon-
`troller level in order to minimize battery power consump-
`tion. In general, power management techniques at the micro-
`controller level are known to utilize centralized control to
`
`control the power to the central processing unit (CPU) by
`reducing the speed or stopping the system clock.
`There are several disadvantages in utilizing such central-
`ized control at the microcontroller level. First, such central-
`ized systems do not optimize the power usage of the various
`subsystems of the microcontroller. In general, the microcon-
`roller subsystems are treated equally with the CPU from a
`Jower management standpoint and are thus not optimized.
`Secondly, the architecture of the power management system
`in known microcontrollers varies as a function of the num-
`
`
`
`3er of subsystems included in the microcontroller for a given
`nicrocontroller family. For example, lower cost microcon-
`rollers are normally provided without analog and digital
`converters (ADC) and corresponding ADC ports requiring
`one power management architecture, while higher level
`nicrocontrollers within the same family may include an
`ADC as well as other subsystems which require a different
`aower management architecture. Thus, for a given family of
`microcontrollers, multiple power management architectures
`nay be required, which increases the cost and complexity of
`he microcontrollers.
`
`SUMMARY OF THE INVENTION
`
`It is an object of the present invention to solve various
`problems in the prior art.
`It is yet a further object of the present invention to provide
`a power management system for a microcontroller which
`enables the microcontroller subsystems to be independently
`controlled.
`
`It is yet a further object of the present invention to provide
`a modular architecture for a power management system for
`a microcontroller which enables the power management of
`the microcontroller subsystems to be controlled indepen—
`dently of the central processing unit (CPU).
`Briefly, the present invention relates to a power manage-
`ment architecture for a microcontroller. The power manage—
`ment architecture includes a power management state
`machine for controlling the power mode of the central
`processing unit (CPU and each of the subsystems within the
`microcontroller.
`
`and application
`specific applications. Each of the microcontroller sub-
`systems is connected to the system by way of a flexible
`peripheral interface (FPI)(the system bus . The FPI is a 32
`bit de-multiplexed, pipelined bus.I
`
`

`

`US 6,665,802 B1
`
`4
`an architecture allows the power management subsystem to
`control the various subsystems from a power management
`
`standpoint with a few global commands. The use of the FPI
`
`thus
`3us and FPI peripheral interfaces for each of the subsystems
`enabling each subsystem to be independently controlled by
`3rovides for a modular architecture which can be used with
`the power management state machine in order to optimize 5
`virtually any number of subsystems;
`thus decreasing the
`the power management of the various subsystems. Each of
`complexity and the COSt 0f the microcontrollers. AS SUCh,
`the FPI interfaces as well as the power management state
`such systems can be added to the microcontroller without
`SFR are connected to an FPI bus which interconnects the
`he need to design an entirely new integrated circuit. In
`FPI interfaces with the central processing unit (CPU) and
`power management state machine 5FR. The pp] bus enables 10 addition, it should be understood that the modular architec-
`reads and writes of the power management state machine
`ure in accordance with the present invention can be used in
`SFR and peripheral interface SFRs. Such a configuration
`applications other than power management to provide opti-
`allows subsystems to be added or deleted without changing
`mal control of the microcontroller subsystems. It is noted
`the basic architecture of the power management system, thus
`hat, the term “microcontroller” is deemed interchangeable
`forming a modular power management architecture which 15 With any System-on-Chip (SOC)~
`reduces the cost and complexity of the microcontrollers.
`As Will be discussed in more detail below, the power
`nana ement subs stem in accordance with the
`resent
`
`
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`invention are
`These and other objects of the present
`readily understood with reference to the following specifi-
`cation and attached drawings.
`
`Ill!
`
`depending on the instantaneous requirements of the particu—
`lar subs stem.
`
`{11a:O{27‘ Or—e
`
`.—>CF0m0
`
`OQ0m H.m 9..H.gx:U1m0D.
`
`H.D
`
`OHO 9..O.—»m3
`
`FIG 1 is a block diagram Of a power management
`architecture for a microcontroller or system on chip (SOC) in
`accordance with the present invention, shown with only .
`those subsystems necessary for a complete understanding of
`the invention for clarity.
`FIG. 2 is an expanded block diagram of the power
`management subsystem of the microcontroller illustrated in
`FIG~ 1~
`FIG. 3 is a block diagram of the clock subsystem in
`accordance with present invention which forms a part of the
`invention.
`
`FIG. 4 is a bit diagram of a peripheral interface power
`control special function register (SFR) in accordance with I
`the present invention.
`
`below.
`As discussed above, the response of each of the sub-
`30 systems in the states can be preconfigured by the operating
`system or application program to provide optimum sub-
`S stem erformance.
`
`
`
`the
`FIG. 5 is a bit diagram of an SFR for a power management— As such,
`.
`state machine in accordance with the present invention.
`.
`.
`.
`
`microcontroller With the power management architecture in
`_
`_
`_
`_
`FIG' 6 15 a state diagram for the state machine according 40 accordance with the present invention is able to provide
`to an embodiment 0f the present invention.
`increased battery life for portable microcontrolled devices,
`DETAILED DESCRIPTION OF THE
`such as cellular phones, as well as power loss in a recov-
`INVENTION
`erable fashion. In addition, the system can be used to limit
`peak power during turn-on and reset of the portable device
`The present invention relates to a modular power man- 45 which can cause battery power fault condition, resulting in
`agement architecture for a microcontroller or System on
`shutdown of the device. During such conditions, the power,
`Chip (SOC) which can be utilized for microcontrollers or
`oscillator and phase lock loop (PU) functions may be
`SoC’s with different numbers of subsystems and which
`ramped in order to lower the peak power (Ich) and
`allows an operating system or application program to inde-
`startup surge which allows a more efficient
`low-power
`pendently control the subsystems within the microcontroller 50 power supply to be used thus lowering the cost while
`to optimize power management of the subsystems.
`In
`dramatically lowering the average power Icch of the
`particular, the microcontroller architecture includes a power
`microcontroller. Other advantages of the system in accor-
`management subsystem which includes a configurable
`dance with the
`resent invention include:
`power management state machine for controlling the power
`modes of the central processing unit (CPU) and the various 55
`microcontroller subsystems. Each microcontroller sub-
`system is interconnected to the power management sub-
`system and the CPU by way of a flexible peripheral interface
`FPI and an FPI bus
`
`
`
`rltc:
`
`power supply can maintain regulation, and
`
` In addition, the system
`
`H.H
`
`l
`
`65 can be used to limit peak power during turn-on and reset of
`the portable device which can cause battery power fault
`condition, resulting in shut down of the device. During such
`
`(I)sn:r‘
`
`0007
`0007
`
`

`

`US 6,665,802 B1
`
`5
`conditions, the power, oscillator and phase lock loop (PLL)
`functions may be ramped in order to lower the peak power
`(Ich) and startup surge which allows a more efiicient
`low-power power supply to be used thus lowering the cost
`while dramatically lowering the average power IchYP of the
`microcontroller. Other advantages of the system in accor-
`dance with the present invention include: the ability of the
`system to maintain its state without data loss during battery
`discharge conditions such that, for example, the system can
`enter a static mode at the first sign of a power failure, the
`power supply can maintain regulation, and the device’s state
`is maintained until a new battery is inserted or recharged; the
`ability to shut off entire subsystems during the SLEEP mode
`in order to minimize power supply losses at low power; and
`a soft RESET that does not disturb external devices or
`
`memory, which allows reset of only those components of the
`system which were powered down, leaving the external
`system unaware of the reset.
`SYSTEM BLOCK DIAGRAMS
`
`A block diagram for the microcontroller power manage-
`ment architecture in accordance with the present invention is
`illustrated in FIG. 1 and generally identified with the refer—
`ence numeral 20. The power management architecture can
`be implemented on virtually any microcontroller. For clarity,
`only those elements and subsystems of the microcontroller
`necessary for a complete understanding of the invention are
`shown. As shown, the microcontroller includes a CPU core
`22, which may be any of a variety of CPU cores, such as a
`32-bit RISC-like core, a digital signal processor core, or a
`16-bit [microcontroller core. The CPU core 22 is coupled to
`a system bus, for example, a multiplexed address/data FPI
`bus 24, for example, 32 bit,—
`
`the
`
`
`
`A management subsystem 26 is also provided and
`coupled to the FPI bus.
`
`—to be
`controlled as will be discussed in more detail below. Also
`attached to the FPI bus 24 are various microcontroller
`subsystems including input/output (I/O) ports 30, direct
`memory access (DMA) 32, system timers 34, and external
`bus controller (EBC) 36. Other standard subsystems are
`identified with the reference numeral 38, while applications
`specific subsystems are identified with the reference numeral
`40. Each of the major subsystems 30—40 are connected to the
`FPI bus 24 by way of a FPI peripheral interface 42—52,
`respectively. The microcontroller may also include memory
`banks 54 and 56, which may be dynamic random access
`memory (DRAM) and include refresh circuitry 58 and 60,
`respectively. As will be discussed in more detail below, an
`interrupt control unit (ICU) 62 is kept active (i.e. powered
`up) during all power modes. An Interrupt control signal from
`the ICU 62 is tied to both the power management subsystem
`28 as well as the CPU core 22.
`
`An expanded block diagram of the management sub-
`system 26 is illustrated in FIG. 2. As shown,
`the power
`
`management subsystem 26 includes
`
`_ The reset subsystem 66 may be a
`
`conventional reset circuit which is responsive to an external
`hardware reset HDRST! 68 and a power on reset PORST!
`70. (As used herein the symbol
`!
`is used to designate a
`
`
`
`6
`logical complement of a signal or in other words that the
`signal
`is active low.) The reset PORST! 70 resets the
`complete chip; the complete system is held in reset until the
`PLL 85 indicates a lock to an external crystal. The reset
`HDRST! is constantly sampled by the power manager 28 at
`he power clock frequency to detect the external hardware
`reset request. The power manager 28 will reset the chip and
`iold it in reset until it detects an inactive HRDSTE. Each of
`hese resets HDRST! and PORST! may be pulled up by pull
`up resistors 72 and 74, respectively. The management sub-
`system 26 may also include a watchdog timer 76 as well as
`he ability for external signals, such as non-maskable inter-
`upt (NMI) and battery fault, identified as special pins with
`he reference numeral 78, shown connected to an external
`3in 80 to interface with the power system state machine 28.
`According to one embodiment, the FPI bus is a demulti-
`3lexed 32-bit address/data bus. It is noted, however, that any
`system bus could be employed. Thus, the figures are exem-
`3lary only.
`
`SYSTEM [/0 PINS
`
`Table 1 illustrates the dedicated I/O pins for the power
`nanagement subsystem 26. The pins for main crystal, iden-
`ified with the reference numeral 84, provide the main clock
`source. The pins for the 32 KHZ crystal, identified with the
`reference numeral 86, are optional and are used for those
`microcontrollers which include a real time clock (RTC). The
`iard reset HDRST! and power on PORST! reset pins 88 and
`90 are used in conjunction with the reset subsystem 66. As
`discussed above, special interrupt pins, generally identified
`with the reference numeral 78, enable the management
`subsystem 26 to interface with external interrupts, such as a
`non-maskable interrupt (NMI) and a battery power fault.
`The management subsystem 26 may also be provided with
`output pins, identified in FIG. 2 as boot configuration pins
`82, for core powcr enable and sleep. Thcsc pins are dis-
`cussed in Table 1 and are configured during boot up and read
`from the SFR register to control external devices.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`TABLE 1
`
`Optional When Unused
`
`40
`
`Signal
`
`Main CrysLal
`
`PORST!
`
`HDRST!
`
`45
`
`[/0
`I/O
`
`Input
`
`I/O
`
`Power Fault
`
`Input
`
`Yes
`
`Negated
`
`NMI
`
`50
`
`Input
`
`Yes
`
`Negated
`
`Function
`Main Oscillator
`Source
`Power on
`Reset Pin
`External Hard
`Reset
`Pending Battery
`or Power Fault
`(Signal must go
`to [CU as well)
`Non-Maskable
`Interrupt (Signal
`must go to ICC
`as well)
`Asserted =
`Supply Power
`to Device Core,
`Negated =
`Remove Core
`Power
`Assert SLEEP
`signal to
`external devices
`32 KHz
`oscillator
`Source
`
`Core Power
`Enable
`
`Output
`
`Yes
`
`Sleep
`
`Output Yes
`
`32 KHZ Crystal
`
`I/O
`
`Yes
`
`55
`
`60
`
`65
`
`SYSTEM CONTROL SIGNALS
`
`Table 2 is a list of the signals generated by the power
`management subsystem 26 used in the overall power man-
`agement system. These signals are discussed below.
`
`0008
`0008
`
`

`

`US 6,665,802 B1
`
`7
`
`TABLE 2
`
`SIGNAL
`
`SOURCE
`
`FUNCTION
`
`Management subsystem 26
`
`FPI RESETiN Management subsystem 26 Hard reset to all
`[1:0]
`FPI subsystems
`RESET
`software reset to
`[n:0]
`individual subsystems
`CPU RESET Management subsystem 26
`reset CPU core
`SYSTEM
`Management subsystem 26 Full system clock
`CLOCK
`(distribution)
`IDLE
`asserting during IDLE
`mode to CPU
`asserting when pipe
`line is flushed
`asserting during SLEEP
`mode to system
`CPU supervisory
`mode instruction.
`
`Management subsystem 26
`
`IDLE Ack
`
`CPU 22
`
`SLEEP
`
`Management subsystem 26
`
`FPI SVN
`
`Bus masters
`(Debug included)
`
`8
`particular, this signal may be an output from states SLEEP
`140, POWER UP 142, Wait PLL 144, and RESET 148.
`
`Various software entities may request a reset by writing to
`the SFR 62. The Reset Unit reset unit 66 reads the soft reset
`
`signal and issues a reset control signal to the OR gates 98,
`100.
`
`10
`
`15
`
`The power management state machine 28 can also gen—
`erate a CPU reset by way of a CPU reset signal, available at
`the output of an OR gate 100. from the reset unit 66.
`
`Several signals can be used to reset the complete system
`or individual subsystems 30—40 including: a power on reset
`PORST!; a hardware reset HDRSTl; a watchdog timer reset;
`and a wakeup reset from a SLEEP mode. Table 3 indicates
`the reset sources and the results.
`
`TABLE 3
`
`RESET RESULTS
`
`FPILResetin
`(1:0)
`00
`00
`00
`00
`RS FPI
`
`HDRST!
`Out
`X
`X
`X
`
`RS OUT
`
`CPU Memory
`Reset
`Reset
`X
`X
`X
`X
`X
`X
`X
`X
`X
`selectable
`
`PLL
`Reset
`X
`X
`X
`X
`RS CLK
`
`Boot
`Config
`X
`
`Manager
`Block
`X
`X
`X
`
`Debug
`X
`X
`X
`
`RS DBG
`
`Reset Source
`PORST!
`HDRST!
`Watchdog
`PMSM
`Soft Reset
`RSTREQ
`
`As illustrated in Table 2, the management subsystem 26
`also generates a system clock signal, an IDLE signal, and a
`SLEEP signal. The IDLE signal is asserted by the power
`management state machine only to the CPU core 22 to hold
`its internal clocks. More particularly, when the IDLE signal
`is asserted, the CPU flushes its pipeline and shuts down its
`internal clocks until the IDLE signal is removed. The IDLE
`signal is asserted in the IDLE, SLEEP and DEEP SLEEP
`modes. Once the IDLE signal is asserted, the CPU core 22
`asserts the IDLE acknowledge signal when the pipeline is
`flushed and halts or disables the internal CPU clock. During
`the time the IDLE time is asserted, all interrupts from the
`interrupt controller unit 62 are ignored. The SLEEP signal is
`an assertion from a power management state machine to all
`subsystems to switch to their respective SLEEP mode con-
`figurations as will be discussed in more detail below.
`CLOCK SUBSYSTEM
`
`_—
`
`An exemplary
`clock subsystem 64 is illustrated in FIG. 3 and includes: a
`system oscillator 104; a phase lock loop (PLL) 106; and a
`clock 108, which are used to generate a system clock signal
`SYSTEM CLOCK.—
`
`
`
`
`
`
`
`ivides
`the oscillation frequency to provide the system clock
`frequency, for example 75 MHZ.
`The clock subsystem 64 also includes a management
`clock110.—
`— such as a real
`time clock (RTC)
`
`is
`that
`is a supervisory signal
`The FPIiSVN signal
`asserted by a bus master (i.e. CPU core). More particularly,
`as mentioned above, each of the subsystems 30—40 include
`a FPI peripheral interface 42—52, respectively, which,
`in
`turn, include an SFR register which enables the individual
`subsystems 30—40 to be configured by the operating system
`on how to respond to the power management commands
`from the power manager 28. The management subsystem 26
`also includes an SFR register 62 that allows the management
`subsystem to be configured during boot up by way the
`operating system for a specific application. The signal
`FPIiSVN is asserted during a supervisory mode to enable
`the SFRs to be configured.
`The reset signal [n20] RESET is used for resetting the
`individual subsystems 3W40. One bit per subsystem is
`provided to enable individual software reset control of each
`of the subsystems independent of the other systems. The
`software reset signal RESET [n:0] is connected to a reset bus
`92 as well as a hardware reset signal FPIiRESETiN [1:0].
`The reset bus 92, is an n bit bus, for example, a 8 bit bus. One
`bit is connected to each of the major subsystems 30—40. For
`example, the Reset on Wake Up bit of the state machine SFR
`is used to configure the software reset signal for a global
`reset when persistent memories are not possible. In addition
`to the software reset signal, RESET [n20], a hard reset signal
`FPIiRESETiN [1:0] is also applied to each of the major
`subsystems 30—40 by way of the reset bus 92 to provide a
`hardware reset
`to all subsystems 30—40. The hard reset
`signal FPIiRESETiN [1:0] is available at the output of the
`OR gate 98 and generated by various sources as indicated in
`Table 3 below including the power management state
`machine. The power management state machine generates
`this signal, for example, as the output of various states, as
`seen in FIG. 6 and is explained in greater detail below. In
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`0009
`0009
`
`

`

`US 6,665,802 B1
`
`9
`the
`oscillator 114, connected to the 32 KHZ crystal 86;
`system clock oscillator 104; or the system clock signal
`
`SYSTEM CLOCK.
`
`The man-
`
`10
`during a SLEEPH10de—
`— The periph-
`eral interface control SFR register 116 may also provide for
`a peripheral Specific configuration of a peripheral specific
`sleep mode which would be active when the Sleep mode
`enable signal SME is set.
`
`5
`
`
`agement clock is used to run the power management system,
`a reset clock, and the watchdog timer.
`During normal operations, the management clock may be
`sourced by the system clock signal SYSTEM CLOCK.
`
`During low power operation, START-UP and DEEP SLEEP
`ement clock 110 ma
`be
`mode of operation,
`the manag
`driven by the main oscillator 104* I
`
`10
`
`
`
`As mentioned above,—
`
`— The register 62 is illustrated in FIG. 5. A
`definition of the bits in the register 62 is provided in table 5
`below.
`
`TABLE 5
`VAL-
`R/
`BITS UE
`VV
`
`REQ/O/
`REC
`
`PURPOSE
`
`NAME
`
`SOFTWARE CONFIGURATION REGISTERS
`
`(SFR)
`
`Software configuration registers (SFR) are provided in
`each of the subsystems to 30—40 in order to control the
`response of each subsystem 30—40 during the different
`power modes of operation. In particular, each subsystem
`30—40 is provided with a peripheral interface power control
`SFR register 116 as illustrated in FIG. 4.
`
`20
`
`25
`
`30
`
`TABLE 4
`
`Req/
`
`Name
`Bits
`Value
`R/W O/Rec
`Purpose
`
`r,’w
`
`r,’w
`
`r,’w
`
`0
`
`1
`
`15:8
`
`SME
`(Sleep
`Mode
`Enable)
`
`DPC
`(Disable
`Peripheral
`Clock)
`SDClk
`(Sleep
`Divide
`Clock)
`
`0
`1
`
`0
`1
`
`0000000
`0
`0000000
`1:
`1111111
`1
`
`Required
`
`No SLEEP Mode
`(Default) Enable
`SLEEP Mode when
`“SLEEP” signal
`assert
`Required Disable Peripheral
`during RUN Mode
`(Default) RUN,
`Clock enabled
`Disable During
`SLEEP (Default)
`Divided Clock
`During SLEEP as
`defined by
`Peripheral
`
`Optional
`
`No Sleep Request
`(Default)
`Idle Request
`Sleep Request
`Deep Sleep Request
`(DEEP SLEEP bit)a
`Note: this field is
`cleared upon return
`to RUN state
`No Reset on Wake
`Up(Default)
`Reset on Wake Upb
`Core Powered during
`DEEP SLEEP (De-
`fault) Core Powered
`Off in DEEP SLEEP
`As defined in the
`implementation
`
`Norrnal PLL (Default)
`Oscillator Pass
`Through/PLL on
`Oscillator Pass
`Through/PLL off
`32 KHz/Osc & PLL on
`32 KHz/Osc & PLL
`01f
`Normal PLL/No Sys
`Clk
`Oscillator Pass
`Through/PLL
`on/No Sys Clk
`Oscillator Pass
`Through/PLL off/No
`Sys Clk
`32 KHz/Osc & PLL
`on/No Sys Clk
`32 KHz/Osc & PLL
`off/No Sys Clk
`Reserved
`Watchdog Operates
`during Sleep and Idle
`and overflow can
`cause reset (Default)
`Watchdog operates
`during Sleep and Idle
`and causes wake-up
`Watchdog Timer clock
`stopped during Sleep.
`Note: The Watchdog
`timer will be unable to
`cause a reset or wake
`up from Sleep in this
`mode.
`Reserved
`
`00
`
`r/w Required
`
`4
`
`RW
`(Reset on
`Wake-Up)
`
`r/w Required
`
`r/w Optional
`
`0
`
`1
`
`1
`
`15:8
`
`r
`
`Required
`
`35
`
`PMSt (Power
`Management
`State)
`
`40
`
`45
`
`
`
`r/w {equired
`{ecom-
`mended
`Recom-
`mended
`Optional
`Optional
`
`Required
`{ecom-
`mended
`
`Recom-
`mended
`
`- 00000010
`0011
`0100
`0101
`1000
`1010
`
`1011
`1100
`1101
`
`all
`oth-
`ers
`
`50
`
`55
`
`These peripheral interface power control SFR registers
`116 allow the operating system to control each of the
`subsystems 116 independently. Subsystems 30—40 that are
`not used may be either powered down or have their clock
`forced into a static state. As mentioned above, the peripheral
`interface power control SFR register 116 is only accessible
`in the supervisory mode of the CPU core 22 or other
`privileged modes. These registers 116 may be reset to a
`default value when the reset signal FPI RESETiN [1:0]=00
`or 01 or during