(12) United States Patent
`En do
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006895519B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,895,519 B2
`May 17,2005
`
`(54) SYSTEM LSI
`
`(75)
`
`Inventor: Hitoshi Endo, Tokyo (JP)
`
`(73) Assignee: Oki Electric Industry Co., Ltd., Tokyo
`(JP)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`
`09-062397
`10-149237
`11-073237
`11-194849
`2000-091976
`2000-116887
`2001-202155
`2001-238190
`2002-182776
`
`3/1997
`6/1998
`3/1999
`7/1999
`3/2000
`4/2000
`7/2001
`8/2001
`6/2002
`
`* cited by examiner
`
`(21) Appl. No.: 10/251,755
`
`(22) Filed:
`
`Sep. 23, 2002
`
`(65)
`
`Prior Publication Data
`
`US 2003/0163743 A1 Aug. 28, 2003
`
`(30)
`
`Foreign Application Priority Data
`
`Feb. 25, 2002
`
`(JP) ....................................... 2002-047696
`
`Int. Cl? .................................................. G06F 1/26
`(51)
`(52) U.S. Cl. ........................................ 713/322; 713/320
`(58) Field of Search ................................. 713/322, 300,
`713/320, 600
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,630,148 A * 5/1997 Norris ........................ 713/322
`5,811,987 A * 9/1998 Ashmore et a!.
`............. 326/39
`6,574,739 B1 * 6/2003 Kung et a!. ................. 713/322
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`
`06-119079
`06-217049
`
`4/1994
`8/1994
`
`Primary Examiner-Jeffrey Gaffin
`Assistant Examiner-Harold Kim
`(74) Attorney, Agent, or Firm-Valentine Francos & Whitt,
`PLLC
`
`(57)
`
`ABSTRACT
`
`A system LSI dynamically and speedily controls clocks of
`various frequencies as used in a wide range of operation
`modes from high-speed to low-speed operation modes,
`enabling user selection of a system of power consumption
`type most suitable. The system LSI includes a ROM that
`stores a clock control library for carrying out clock state
`transitions between ordinary operation modes; and a system
`control circuit having a register for carrying out clock state
`transitions between ordinary operation modes and special
`modes responsive to changes in value of the register, and
`also carrying out clock state transitions among ordinary
`operation modes responsive to the clock control library.
`Calling of the clock control library and changing of the
`register value are controlled by an application program. The
`main library of the clock control library is described and
`called using C language.
`
`11 Claims, 10 Drawing Sheets
`
`I
`
`' '
`-~~j~~~~~~~~~~~~~I~~~~~~~~~~~;;~~:~;;;-
`
`I
`
`AMD EX1001
`U.S. Patent No. 6,895,519
`
`0001
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 1 of 10
`
`US 6,895,519 B2
`
`FIG.1
`
`541
`rJ
`5~31
`
`7
`INTERNAL
`DATA CACHE
`RAM
`
`511
`v-J
`INTERNAL
`514
`INSTRUCTION if~
`CACHE RAM
`512
`fJ
`
`CORE CPU
`
`522
`.-l
`520
`~ TEST
`CPU BRIDGE I
`INTERFACE
`
`r
`
`r -?
`
`521
`
`510
`r---1
`
`I R-
`
`542
`
`s23 L
`
`543
`
`MEMORY
`CONTROL
`CIRCUIT
`
`r
`
`I
`INTERNAL
`INTERRUPTION
`CONTROL
`CIRCUIT
`(
`I 525
`
`544
`
`545
`
`~30 524
`
`PERIPHERAL l ARBITRATION
`
`BUS
`
`DEVICE
`
`BRIDGE
`
`r
`~ l
`
`531
`
`TIMER
`
`("'-.J
`532
`
`I
`
`SERIAL
`INTERFACE
`533 ~ 534
`
`/'--.
`
`0--
`
`547
`
`SYSTEM
`CONTROL
`CIRCUIT
`
`I
`
`546
`
`0002
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 2 of 10
`
`US 6,895,519 B2
`
`FIG.2
`
`JTAG TERMINAL
`
`510
`
`550
`?
`
`EXTERNAL TEST BUS
`
`EXTERNAL MEMORY BUS
`
`551
`
`552
`rJ
`
`ROM
`
`RAM
`
`553
`r--1
`USER
`ORIGINAL
`CIRCUIT
`GROUP
`
`543
`
`544
`
`525
`
`545
`
`~iNf(RNACI
`
`'INTERRUPTION'
`: CONTROL
`1
`I CIRCUIT
`I
`________ J
`
`EXTERNAL
`INTERRUPTIO
`CONTROL
`CIRCUIT
`
`559
`
`554
`
`PERIPHERAL
`BRIDGE
`
`555
`
`546
`534
`r_( _____ _
`: SYSTEM
`:
`t CONTROL
`________ ,)
`: CIRCUIT
`:
`547
`
`558
`
`CLOCK
`GENERATION
`CIRCUIT
`
`POWER
`DOWN
`CONTROL
`CIRCUIT
`
`USER
`ORIGINAL
`CLOCK
`ENERATION
`CIRCUIT
`
`556
`
`557
`
`t COMMUNICATION PORT
`
`0003
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 3 of 10
`
`US 6,895,519 B2
`
`FIG.3
`
`534
`
`561
`
`566
`
`10 REGISTER
`
`567
`
`STATUS
`REGISTER
`
`CONTROL
`SIGNAL
`CKWT
`
`CONTROL
`SIGNAL
`CGC
`
`CONTROL
`SIGNAL
`PMP
`
`CLOCK
`SIGNAL
`BCLK(IN)
`
`562
`
`CLOCK SUPPLY
`WAIT REGISTER
`
`563
`~
`FREQUENCY-DIVISION
`RATIO SETTING REGISTER
`
`CLOCK HALT
`REGISTER
`
`564
`~
`
`565
`
`CLOCK HALT
`CONTROL REGISTER
`
`HCLK CLOCK SIGNAL
`
`0004
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 4 of 10
`
`US 6,895,519 B2
`
`558
`
`572
`
`CONTROL PORTION
`
`OSCEN
`
`FIG.4
`
`CONTROL
`SIGNAL
`CGBSTP
`
`CONTROL
`SIGNAL
`CKWT
`
`MCLKO
`
`MCLK 1
`
`MCLK2
`
`571
`
`CONTROL
`SIGNAL
`CLKEN
`574
`
`CLOCK
`CONTROL
`PORTION
`
`FREQUENCY
`DIVISION/
`SELECTION
`PORTION
`
`573
`.,.._;
`
`FCLK
`
`BCLK(OVT)
`
`TMCLK
`
`PLLEN
`
`PLL
`
`CSEL TMSEL
`
`0005
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 5 of 10
`
`US 6,895,519 B2
`
`FIG.5
`
`RESET
`
`(1)
`
`STN 1
`HIGHEST-SPEED
`OPERATION MODE
`(62.5MHz)
`
`(3)
`
`(5)
`
`(4)
`
`STN 2
`HIGH-SPEED
`(2) OPERATION MODE
`SOMHz)
`(1 0)
`
`(9)
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`11
`(n):STATE
`- J
`TRANSITION NUMBER
`,-------------- ----~-------------------,
`(0}
`:
`:
`~--~s=TN~o~~
`INITIAL OPERATION
`1
`MODE
`:
`(25MHz)
`1
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`r
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`
`STN 3
`LOW-SPEED
`OPERATION MODE
`_{_31.25MHz)
`(7)
`
`(6)
`
`STN 4
`LOWEST -SPEED
`OPERATION MODE
`(32.768KHz)
`
`(8)
`
`------ ~; ------------r-------- ~~::~~~ ~~:~-
`
`1- -
`
`- _;::}__ -
`
`-
`
`-
`
`- - - - - - - - - - -
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`- - - - - - - -
`
`-
`
`- - - -
`
`-1
`
`r
`I
`I
`~--~--~ ~-------. ~-----~ I
`STN 6
`STN 7
`:
`STN 5
`HALT MODE
`SLEEP MODE
`:
`STOP MODE
`I
`I
`I
`
`L----------------------------------------~
`
`0006
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 6 of 10
`
`US 6,895,519 B2
`
`FIG.6
`
`31
`~
`I APPLICATION PROGRAM
`
`I
`
`32
`I
`CLOCK CONTROL LIBRARY .
`r....t::::::----------------------------------------1
`33
`
`I
`
`MAIN LIBRARY
`
`I
`I
`I
`I
`I
`I
`I
`I
`
`I
`
`LIBRARY 1
`
`LIBRARY 0
`
`I
`
`LIBRARY 8
`
`34
`
`~
`
`~--------------- ---------------------------
`35
`I CLOCK CONTROLLING HARD
`
`0007
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 7 of 10
`
`US 6,895,519 B2
`
`FIG.7
`
`CLOCK STATE
`TRANSITION
`
`INPUT
`PARAMETER
`
`JUMP
`TABLE
`NO.
`
`LIBRARY
`FUNCTION
`NAME
`
`SYSTEM
`w/o
`DRAM
`
`OxOO
`--------
`
`LOW-SPEED>
`OxOO
`clkgearO
`HIGH-SPEED OR
`HIGHEST-SPEED 1---------
`----------
`1--------
`HIGH-SPEED OR
`Ox01
`HIGHEST -SPEED
`clkgear1
`Ox01
`>LOW-SPEED
`1---------- -------- -------- -------
`NO CHANGE
`Ox02
`Ox02
`clkgear2
`IN MEMORY
`PARAMETER
`
`LOW-SPEED>
`OxOO
`Ox10
`clkgear3
`HIGH-SPEED OR
`HIGHEST-SPEED
`1---------- -------- -------- 1--------
`HIGH-SPEED OR
`SYSTEMw.
`Ox01
`clkgear4
`Ox11
`HIGHEST -SPEED
`DRAM w/o
`>LOW-SPEED
`LOWEST 1----------1--------- -------- 1--------
`SPEED
`NO CHANGE
`IN MEMORY
`Ox02
`clkgear5
`Ox12
`PARAMETER
`LOWEST -SPEED>
`LOW-SPEED.
`clkgear6
`Ox23
`Ox13
`HIGH-SPEED OR
`HIGHEST -SPEED 1--------- -------- 1--------
`SYSTEM w. ~-~--- - - - ---
`LOW-SPEED,
`DRAMw.
`HIGH-SPEED OR
`clkgear7
`Ox14
`LOWEST
`Ox24
`HIGHEST-SPEED
`SPEED
`>LOWEST -SPEED
`1'---------- -------- --------1--------
`CLOCK CHANGE
`Ox15
`clkgear8
`Ox25
`IN
`LOWEST -SPEED
`
`0008
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 8 of 10
`
`US 6,895,519 B2
`
`FIG.8(a)
`
`I
`I
`I
`
`®: I
`
`I
`
`@:
`I
`I
`I
`
`I
`I
`I
`
`@:
`
`I
`
`I
`I
`I
`
`@:
`
`I
`I
`I
`
`I
`I
`I
`
`I
`I
`I
`
`:®
`
`I
`I
`
`I
`I
`
`I
`I
`
`I
`I
`
`I
`
`I
`
`I
`I
`
`I
`
`I
`
`I 1
`I Oxff
`1
`6
`1
`1
`1
`I 0
`0
`---------- ---~----r---,----r---,----r---~----
`I
`I
`1
`I 1
`3
`3
`3
`8
`7
`I Oxff
`Q
`---------- ---,----r---,----r---,----r---,----
`I
`I
`1
`2
`1
`I 0
`I Oxff I Oxff I
`1
`6
`1
`I Oxff
`---------- ---4----~---~----~---~----~---~----
`3
`0
`1
`3
`8
`7
`I Oxff I Oxff I
`I Oxff
`I
`I
`I
`---------- ---~----L---~----L---~----L---~----
`4
`1
`1
`1
`1
`1
`6
`I Oxff I Oxff
`I
`I
`I
`I
`I
`---------- ---~----L---~----L---~----L---~----
`I
`I
`1
`I
`I
`I
`I
`5
`0
`3
`3
`3
`8 . I
`7
`1
`I Oxff
`---------- ---~----r---,----r---,----r---~----
`I
`I
`I
`I
`I
`6
`Ox14 1 0
`0
`0
`0
`2
`2
`1 Oxff
`1
`1
`r---------- ---4----~---~----~---~----~---~----
`Ox 1 3 1 1
`1 Ox Of 1 Oxff
`1
`1
`1
`1 6
`7
`1
`1
`1
`---------- ---~----L---~----L---~----L---~----
`8
`Ox14 : 0
`: 0
`0
`: 0
`: 2
`:
`2
`: Oxff
`:
`r---------- ---T----r---~----r---~----r---~----
`Oxl3 1 0
`1 Oxff
`9
`3
`3
`1
`6
`1
`---------- ---4----r---,----r---~----r---~----
`10
`0
`: 0
`: 3
`:
`3
`: Oxff I Oxff I
`1
`: Oxff
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`bO
`
`FIG.8(b)
`b7
`CD MEMORY PARAMETER CHANGE PATTERN
`---------------------------------
`® ~~~9~~C_K_~~D_E _____________________ _
`@ E~~E_R~~~ ~~~ ~§~~~~~':_~~§~~R- ________ _
`@ r E~~E_R~~~ ~~ ~~~<2~Y-~-~~~~E_R _________ _
`@ r ~~~E_R~~~ ~~ ~~~0~!~R ________________ _
`@ r §Q~~§C2~-~~----------------------
`(/) PCGBCNTO SET VALUE
`r---------------------------------
`@ PCGBCNT1 SET VALUE
`
`0009
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 9 of 10
`
`US 6,895,519 B2
`
`40
`
`r----~---------------------------------1
`I
`I
`41
`42 I
`I
`I
`I
`I
`I
`I
`1
`
`FIG.9
`
`OSC1
`
`OSC2
`
`I
`I
`I
`I
`I
`
`43
`;---/
`CLOCK
`FILTER
`
`OSCILLA TINGI---++-1
`PORTION
`
`44
`
`CLOCK
`INTERPOLATION
`PORTION
`
`45
`
`48
`
`46
`
`47
`
`CLKOUT
`
`1/0 '
`SETTING
`SWITCHING~-!-----{ REGISTER
`PORTION
`
`fcpu
`L----------------------------- ----------
`
`I
`
`PERIPHERA
`DEVICE
`
`49
`
`0010
`
`

`

`U.S. Patent
`
`May 17,2005
`
`Sheet 10 of 10
`
`US 6,895,519 B2
`
`FIG.1 0
`
`HIGH-SPEED
`OPERATION MODE
`
`WAIT
`MODE
`
`HALT
`MODE
`
`LOW-SPEED
`OPERATION MODE
`
`0011
`
`

`

`1
`SYSTEM LSI
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a system LSI having a
`core CPU and, more particularly, to a system LSI capable of
`executing the dynamic clock control from the side of an
`application program.
`2. Description of the Related Art
`In case of battery-powered devices, for instance a mobile
`telephone, which belong to the application field of a micro(cid:173)
`controller constituted by means of a system LSI, it seems
`that many of them are still requested to improve themselves
`such that their consumption of electric power (referred to
`simply as "power" hereinafter) is reduced as low as possible
`for the sake of their users' convenience and benefit, and
`there have been developed various techniques for respond(cid:173)
`ing to such request. Owing to these techniques, it has
`become possible to reduce the power consumption of the
`entire system, though gradually, by properly changing the
`clock speed corresponding to the need, for instance by
`supplying the high-speed clock when the high speed pro(cid:173)
`cessing is necessary and supplying the low-speed clock
`when the wait state is needed. In the recent years, in almost
`all application fields, an application specific integrated cir(cid:173)
`cuit (ASIC) is provided for the microcontroller constituted
`by means of the system LSI. In the case of the system into
`which the ASIC is built, in order to extend the battery life,
`the power reduction as well as the matters related thereto are
`requested to be described in the specification of the system,
`and it becomes not rare that such low power consumption
`technique is incorporated into the core CPU of the system.
`To begin with, a core CPU ST7 (referred to as "ST7 core"
`hereinafter), a product of a U.S. firm "ST Microelectronics"
`will be explained as an example of a conventional core CPU
`with reference to FIGS. 9 and 10 of the accompanying
`drawings. FIG. 9 is a block diagram for explaining a clock
`control circuit 40 of the ST7 core while FIG. 10 is an
`illustration for explaining the clock operation mode of the
`ST7 core.
`As shown in FIG. 9, an oscillation portion 41 includes two
`oscillation terminals OSC1 and OSC2 and is connected with
`an oscillator such as a quartz oscillator through these oscil(cid:173)
`lation terminals, thereby generating clock signals. A clock
`correction portion 42 is made up of a clock filter 43 and a
`clock rearrangement portion 44. The clock filters 43
`removes the clock in which a spike noise or the like is
`mixed, and rearranges the clock in a predetermined wave
`forms. If the clocks are sparsely lined as a result of the above
`rearrangement of wave form thereof, the rearrangement
`portion 44 operates to narrow the frequency bandwidth of
`the clock.
`A main clock control circuit 45 is made up of a setting
`register 46 and a clock frequency dividing portion 47. The
`setting register 46 sets the frequency division ratio of the
`clock to be 1/4, 1/8, 1!16, and 1!32. The frequency divided
`clocks fcpu are supplied to the ST7 core and peripheral
`devices, and are outputted from the 1!0 terminal CLKOUT
`to the external portion through an 1!0 switching portion 48.
`The ST7 core is operable in four kinds of clock operation
`modes as shown in FIG. 10, under the control of the above
`clock control circuit 40. To put it more concretely, the ST7
`core operates at the frequency of 1/2 of the oscillation
`frequency in the high-speed operation mode. In the low-
`
`30
`
`35
`
`40
`
`US 6,895,519 B2
`
`10
`
`2
`speed operation mode, it operates at the frequency of 1/4,
`1/8, 1/16, and 1!32 of the oscillation frequency, respectively.
`In the wait mode, the clock of the CPU is halted while
`peripheral devices are in operation. In the halt mode, the
`5 oscillation per se halts so that the power consumption of the
`ST7 core is then minimized. Like this, if each operation
`mode is selectively used in correspondence with the pro(cid:173)
`cessing by the CPU, a considerable amount of the power
`consumption can be saved in total.
`On one hand, in case of constituting a microcontroller by
`means of the system LSI, there are some cases where the low
`power consumption technique is incorporated in the core
`CPU. An ARM920T (referred to as ARM core hereinafter),
`a product of a British firm "ARM", may be a good example
`15 of such core CPU. In case of the ARM core, it is premised
`that a power management portion is formed on the side of
`the system LSI.
`There are two reasons why the ARM core adopts the
`constitution like the above. The first reason is that if the
`20 clock control mechanism is built in the core CPU side, a
`certain restriction is given to the design of the system LSI,
`as a result of which the core CPU would come to lose
`versatility thereof. On the side of the system LSI using the
`core CPU, there might take place a case where the clock
`25 drops its speed down and halts, eventually. In such case, it
`would become necessary to detect and examine such state
`and to adjust the timing of the internal memory, the internal
`timer, and so forth.
`The second reason is as follows. The ARM core is
`provided with a joint test action group (JTAG) interface test
`terminal, and transmits the internal state of the core CPU to
`the external portion through an in-circuit emulator (ICE),
`and operates the debugger, thereby giving convenience to
`the development of the application program. Consequently,
`the clock change on the core CPU side results in restriction
`of such use of the test terminal. Therefore, in order to
`effectively carry out the power management free from such
`restriction as mentioned above, it is preferable for them to
`provide the power management portion not on the side of the
`core CPU but on the side of the system LSI, thereby
`achieving the total power management.
`In recent years, the system LSI has been sophisticated
`more and more and it becomes so difficult for the core CPU
`45 to directly and quickly respond to various demands coming
`from ASIC only by the core CPU itself. Then, in order to
`comply with the above problem, it would be considered to
`provide a versatile microcontroller mounting the same core
`CPU thereon. In other words, it is the thought of collecting
`50 common elements which are usually used by the system LSI,
`for instance, peripheral devices of the CPU, memory archi(cid:173)
`tectures and so forth, and have the basic function of execut(cid:173)
`ing an operating system (OS) at real time, and of presenting
`a versatile microcontroller provided with the elements and
`55 function as described above.
`In order to achieve a total power management by mean of
`a versatile microcontroller like this, it is necessary for the
`versatile power management to be carried out taking account
`of not only the core CPU but also the inherent function of the
`60 application.
`In the power management by the prior art microcontroller,
`however, the clock is just simply changed similar to the case
`of the ST7 core as mentioned above. In case of the ST7 core,
`as shown in FIG. 10, there are just simply changed the four
`65 operation modes which are the high-speed operation mode,
`the low-speed operation mode, the wait mode and the halt
`mode. However, when the power management portion is
`
`0012
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`

`US 6,895,519 B2
`
`3
`provided not on the side of the core CPU but on the side of
`the system LSI, it is demanded that the clock of the core
`CPU and that of the system LSI have to be separately
`controlled. Consequently, it is not possible to carry out a fine
`control by means of the simple model like this.
`Furthermore, it has been tried to dynamically control the
`clock from the application program side. For instance, in
`case of the ST7 core, the circuit related to the clock control
`is controlled by means of an assembler language which can
`be directly controlled. However, the clock control by using
`the assembler language is apt to receive many restrictions
`from the point of view of the application program develop(cid:173)
`ment. Accordingly, it is preferable, if possible, to provide a
`flexible interface constituted by using the high-level pro(cid:173)
`gram language like the C language that is usually adopted in
`the current software development. Unfortunately, however,
`there has been no support allowing a real power manage(cid:173)
`ment by using the programming language like this.
`
`SUMMARY OF THE INVENTION
`
`The present invention has been made in consideration of
`various problems the prior art system LSI has encountered
`so far, and an object of the invention is to provide a novel
`and improved system LSI wherein the power consumption
`of it can be suitably reduced by dynamically and speedily
`controlling the clock having various frequencies as used in
`a wide mode range from the high-speed operation mode to
`the low-speed operation mode and, in addition, a real power
`management is executed from the side of an application
`program by using such a programming language as usually
`and widely adopted in the software development, thereby
`enabling the user to select the low power consumption
`system most suitable for his own system.
`In order to solve the problems as mentioned above,
`according to the first aspect of the invention, there is
`provided a system LSI having a plurality of ordinary opera(cid:173)
`tion modes and a plurality of special modes in response to
`the clock state supplied to a central processing unit. The
`system LSI includes: the first memory means (551) storing
`a clock control library for controlling the clock state tran(cid:173)
`sition between the ordinary operation modes; a system
`control circuit (534) having a register and carrying out the
`clock state transition between the ordinary operation mode
`and the special mode in response to the change of the value 45
`of the register, and also carrying out the clock state transition
`among the ordinary operation modes in response to the clock
`control library; a clock generation circuit (558) receiving a
`plurality of standard clocks and generating the clock sup(cid:173)
`plied to the central processing unit according to the control 50
`of the system control circuit; and the second memory means
`(551) storing an application program (31); wherein call of
`the clock control library and change of the register value are
`controlled by the application program.
`The first memory means storing the clock control library 55
`and the second memory means storing the application pro(cid:173)
`gram may be constituted as two independent memory means
`which are separated from each other. The first memory
`means and the second memory means may be formed to
`coexist in a single memory means, sharing the memory area 60
`of the above single memory means.
`The prior art system has used a single standard clock
`system and realized only the high-speed operation mode and
`the low-speed operation mode by executing the frequency
`division of the above standard clock. On this point, different 65
`from the above prior art system LSI, the present invention
`adopts a plurality of standard clock systems. Accordingly,
`
`4
`the clock generation circuit ( 558) is made up of a PLL ( 573)
`which receives a plurality of standard clocks (MCLKO,
`MCLK1, MCLK2) and generates, if need be, the clock
`obtained by multiplying the standard clocks, and a fre-
`5 quency division/selection portion (574) which divides the
`frequency of the standard clock or the multiplied standard
`clock, or selects the same. With this, it becomes possible to
`construct the system LSI having a variety of ordinary
`operation modes (highest-speed operation mode, high-speed
`10 operation mode, low-speed operation mode, lowest-speed
`operation mode, and so on).
`Furthermore, when expressing the relation between the
`current clock state and the clock state after transition by
`using a function (clkgear) in the form of the clock control
`15 library, it becomes possible to dynamically and speedily
`control a plurality of clocks in the ordinary operation mode,
`as if it were a gear-change operation. In this way, the clock
`state can be controlled more finely.
`Still further, according to the invention, the system control
`20 circuit includes a register, and the control making the
`ordinary operation mode transit to the special mode is
`carried out by changing the value of this register. At this
`time, as the register setting is kept unchanged after comple(cid:173)
`tion of transition to the special mode, the reverse transition
`25 from the special mode to the ordinary operation mode can be
`carried out by just releasing the special mode with the help
`of the external interruption, thus, the transition control being
`made much easier.
`It is preferable that the clock control library is made up of
`30 a plurality of libraries and a main library, the former
`controlling the system control circuit and the clock genera(cid:173)
`tion circuit as well to transit the clock state supplied to the
`central processing unit and the latter being called by the
`application program and selecting any one of the libraries in
`35 correspondence with the clock state supplied to the central
`processing unit.
`As described above, the clock control library is made up
`of the main library and a plurality of libraries. With execu-
`40 tion of the function ( clkgear) corresponding to the library as
`selected by the main library, it becomes possible to dynami(cid:173)
`cally control the circuits associated with the clock control,
`that is, the clock generation circuit and the system control
`circuit.
`It is preferable for the main library to be described in the
`same programming language as the application program.
`The main library and the application program are
`described in the same programming language and the appli(cid:173)
`cation calls the main library by using the above same
`language. With this, it becomes possible to realize a flexible
`interface enabling the user to handle it with ease and also
`enabling the user to select the power management system
`which is the most suitable to his system. At present, with
`regard to the above-mentioned language, the invention
`assumes the C language, which is a high-levellanguage and,
`now a day, is widely adopted in the development of the
`software. Even though a certain higher-level language
`would come out in future, it is needless to say that the
`descriptive language of the library could be suitably altered
`without causing any change in the essential constitution of
`the invention.
`Furthermore, it is preferable for each library to be
`described in a programming language which is able to
`directly control the clock generation circuit and the system
`control circuit as well.
`With use of such language, the hardware in association
`with the clock control, that is, the clock generation circuit
`
`0013
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`

`US 6,895,519 B2
`
`5
`
`6
`FIG. 6 is a block diagram for explaining the constitution
`of a clock control library,
`FIG. 7 is a table for explaining call of the clock control
`library,
`FIG. 8 is a table for explaining parameters possessed by
`the library, wherein (a) indicates input parameters to the
`library and (b) indicates the contents of the input parameters,
`FIG. 9 is a block diagram for explaining a prior art clock
`control circuit, and
`1° FIG. 10 is an illustration for explaining conventional
`clock operation modes.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`5
`and the system control circuit can be directly controlled by
`the library. As an example of such language, the invention
`supposes the assembler language for the time being.
`The special mode includes the first special mode (Halt
`Mode) which halts the clock supply to the principal con-
`stituents of the central processing unit, the second special
`mode (Stop Mode) which stops the clock of the entire central
`processing unit, and the third special mode (Sleep Mode)
`which puts the power source of the entire central processing
`unit into the sleeping state.
`With provision of the above-mentioned three modes, it
`becomes possible to establish the constitution which can
`freely manages the reduction of the power consumption
`It is preferable for the system control circuit to be pro- 15
`vided with the frequency division ratio setting register ( 563)
`for setting the frequency division ratio of the clock in the
`clock generation circuit, the clock halt registers (564, 565)
`which receive the clock signal from the clock generation
`circuit to carry out the setting for stopping or supplying the
`individual clock signal, and the status register (567) for
`judging the status of the central processing unit immediately
`after being released from the third special mode. The above
`three registers, that is, the frequency setting register, the
`clock halt register, and the status register may be constituted 25
`by separately using a single register or by complexly using
`two or more registers. The design of the bit length and the
`meaning of each bit may be suitably changed to meet the
`specification of the system.
`With provision of the clock halt register as the register of 30
`the system control circuit, it becomes possible to control the
`transition of the clock state to the first special mode (Halt
`Mode) which halts the clock supply to the principal con(cid:173)
`stituents of the central processing unit, and also the transi(cid:173)
`tion to the second special mode (Stop Mode) which stops the 35
`clock of the entire central processing unit. Furthermore, with
`the provision of the status register, it becomes possible to
`control the transition of the clock state to the third special
`mode (Sleep Mode) which puts the power source of the
`entire central processing unit into the sleeping state.
`It is preferable for one of the standard clocks to use the
`frequency of 32.768 kHz.
`The quartz oscillator for use in a wristwatch may be used
`for obtaining the frequency of 32.768 kHz. With use of the
`clock of which the frequency is very low compared to the 45
`ordinary operation mode which is operated at the frequency
`of several tens of MHz through several hundreds, it becomes
`possible to realize the substantial wait mode.
`
`20
`
`(CPU 510)
`Referring to FIG. 1, a CPU 510 includes a processor 511
`in its inside. A CPU bridge 520 is between the processor 511
`and a dedicated high-speed bus 521 and connected with both
`of them, respectively. On one hand, a peripheral bridge 530
`is between the dedicated high-speed bus 521 and a dedicated
`peripheral bus 531 and connected with both of them, respec(cid:173)
`tively. The processor 511 includes a core CPU 512 as a main
`constituent thereof and further includes an internal data
`cache RAM 513 and an internal instruction cache RAM 514
`as well.
`A system control circuit 534 is connected with the periph(cid:173)
`eral bridge 530 and is able to receive an external clock from
`an external circuit through an external clock terminal 546.
`This system control circuit 534 has the function of supplying
`the clock to the processor 511 and the other constituents of
`the CPU 510 and also has the function of controlling them.
`All of a test interface 522 connected to the dedicated
`high-speed bus 521, a memory control circuit 523, a bus
`arbitration device 524 and an interruption control circuit 525
`belongs to the other constituents of the CPU 510. The test
`interface 522 is connected with an external test bus 542, the
`memory control circuit 523 is connected with an external
`memory bus 543, and the interruption control circuit 525 is
`40 connected with an interruption signal terminal 545. The
`dedicated high-speed bus 521 is provided with an external
`terminal 544, and the system LSI can be constituted by
`connecting a user device with this external terminal 544.
`In addition to the system control circuit 534, a timer 532
`and a serial interface 533 having a communication port 547
`are also connected with a dedicated peripheral bus 531.
`A JTAG terminal 541 is used as a test interface of the
`processor 511 itself.
`(System LSI 550)
`Referring to FIG. 2, a system LSI 550 includes the CPU
`510 shown in FIG. 1 as a principal constituent thereof and
`a dedicated high-speed bus 521 extended from the external
`terminal 544. The extended dedicated high-speed bus 521 is
`55 connected with a read only memory (ROM) 551 storing a
`clock control library and an application program which will
`be described later, a random access memory (RAM) 552,
`and a user original circuit group 553.
`Furthermore, a peripheral bridge 554 connected with the
`60 dedicated high-speed bus 521 is connected with a power
`down control circuit 556 and a user original clock generation
`circuit 557, both of which are on a dedicated peripheral bus
`555. The power down control circuit 556 realizes the power
`down by controlling the clock distribution over the entire
`65 system LSI.
`The external clock terminal 546 is connected with a clock
`generation circuit placed on the system LSI 550 and supplies
`
`50
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Certain embodiments of the system LSI according to the
`invention will now be described in detail by way of
`examples and with reference to the accompanying drawings,
`wherein parts having substantially like function and consti(cid:173)
`tution in each of several figures are identified by the like
`reference numeral or character, and wherein:
`FIG. 1 is a block diagram for explaining the constitution
`of a CPU,
`FIG. 2 is a block diagram for explaining the constitution
`of a system LSI using the CPU as shown in FIG. 1,
`FIG. 3 is a block diagram for explaining a system control
`circuit,
`FIG. 4 is a block diagram for explaining a clock genera(cid:173)
`tion circuit.
`FIG. 5 is a block diagram showing an example of clock
`operation mode and the state transition thereof,
`
`0014
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`

`US 6,895,519 B2
`
`20
`
`8
`7
`A clock control portion 571 controls various sorts of
`the external clock to a system control circuit 534. In
`clocks. A control signal CKWT inputted to the clock control
`addition, an external interruption control circuit 559 is
`portion 571 is an input signal from the clock supply wait
`provided to be connected with the interruption signal ter(cid:173)
`register 562 of the system control circuit 534 and is used for
`minal 545. The embodiment of the invention as mentioned
`above is characterized by a system control circuit 534 and a
`5 ensuring the stabilized period of time of the PLL 573.
`clock generation circuit 558. These two circuits 534 and 558
`A control portion 572 controls the entirety of the clock
`will be explained in the following, with reference to FIGS.
`generation circuit 558. The control signal CGBSTP inputted
`3 and 4, respectively.
`to the control portion 572 is a signal which halts the clock
`of the clock generation circuit 558 itself. In the sleep mode
`(System Control Circuit 534)
`10 which will be described later, halt of oscillation is instructed
`Referring to FIG. 3, the system control circuit 534 has the
`by an output signal OSCEN. Moreover, the control portion
`function of supplying the clock to the processor 511 and
`572 outputs a signal CLKEN controlling the supply/halt of
`other constituents of the CPU 510 and controlling those. A
`the clock to a frequency-division/selection portion 574