UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
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`Petitioner
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`v.
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`AQUILA INNOVATIONS INC.
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`Patent Owner
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`Case IPR2019-01526
`U.S. Patent No. 6,895,519
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`PATENT OWNER'S RESPONSE
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`TABLE OF CONTENTS
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`Page
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`B.
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`C.
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`THE ’519 PATENT CLAIMS A NOVEL SYSTEM LSI ............................. 1
`I.
`II. ASSERTED REFERENCES .......................................................................... 5
`A. Ober ...................................................................................................... 5
`1.
`Ober’s Microcontroller .............................................................. 7
`1.
`Ober’s Decentralized Power Control Architecture .................. 13
`B. Nakazato ............................................................................................. 17
`III. CLAIM CONSTRUCTION ......................................................................... 20
`A.
`The Preamble of Claim 1 Of the ’519 Patent Is Limiting .................. 21
`B.
`The “Plurality Of Ordinary Operation Modes” Operate At
`Different Clock Frequencies Supplied To The CPU ......................... 22
`IV. GROUND 1: THE CHALLENGED CLAIMS ARE NOT OBVIOUS
`OVER OBER AND NAKAZATO ............................................................... 26
`A. Ober Does Not Disclose “A Plurality Of Ordinary Operation
`Modes.” .............................................................................................. 27
`The Combination of Ober and Nakazato Does Not Disclose “A
`First Memory Storing A Clock Control Library For Controlling
`Clock Frequency Transitions Between Said Ordinary Operation
`Modes.” .............................................................................................. 36
`There Is No Reasonable Expectation Of Success Writing To
`The Unused Bits In Ober’s SFR 62 To Supply Low Speed
`Clocks To The CPU During RUN Mode ........................................... 43
`1.
`Reading Or Writing To Unused Register Bits Is Either
`Ignored Or Causes Unpredictable Behavior ............................ 44
`Ober’s Power Management State Machine Might Behave
`Unpredictably Outside The Scope Of Its Defined States ........ 46
`There Is No Motivation To Combine Ober And Nakazato ................ 48
`1. Modifying Ober’s Microcontroller Would Change Its
`Principle Of Operation ............................................................. 49
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`2.
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`D.
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`-i-
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`TABLE OF CONTENTS
`(continued)
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`Page
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`3.
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`E.
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`VII.
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`2. Modifying Ober’s RUN Mode To Use A Divided Clock
`Would Render Ober’s Microcontroller Inoperable For Its
`Intended Purpose ...................................................................... 51
`Ober Teaches Away From A Combination With
`Nakazato ................................................................................... 54
`Ober’s SFR 62 Already Configures The System Clock .......... 61
`4.
`The Institution Decision Relied Upon A New Theory Not
`Asserted by Petitioner ........................................................................ 61
`V. GROUND 2: CLAIMS 2-6 ARE NOT OBVIOUS OVER OBER IN
`VIEW OF NAKAZATO, COOPER, AND WINDOWS ACPI ................... 63
`A.
`The Combination Of Ober, Nakazato, Cooper, and Windows
`ACPI Does Not Render Claims 2-6 Obvious ..................................... 63
`Exhibit 1005 Is Not A Printed Publication ........................................ 64
`B.
`VI. GROUND 3: CLAIMS 8 AND 9 ARE NOT OBVIOUS OVER
`OBER IN VIEW OF NAKAZATO AND DOBLAR .................................. 67
`INTER PARTES REVIEW IS UNCONSTITUTIONAL ............................ 69
`A.
`Inter Partes Review Violates The Appointments Clause ................... 69
`B.
`Inter Partes Review Violates The Takings And Due Process
`Clauses ................................................................................................ 70
`VIII. CONCLUSION ............................................................................................. 70
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`-ii-
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`
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Federal Cases
`Arthrex, Inc. v. Smith & Nephew, Inc.,
`941 F.3d 1320 (Fed. Cir. 2019) .................................................................... 69, 70
`
`Bicon, Inc. v. Straumann Co.,
`441 F.3d 945 (Fed. Cir. 2006) ...................................................................... 21, 22
`
`Celgene Corp. v. Peter,
`931 F. 3d 1342 (Fed. Cir. 2019) ......................................................................... 70
`
`In re Cronyn,
`890 F.2d 1158 (Fed. Cir. 1989) .......................................................................... 66
`
`Edmond v. United States,
`520 U.S. 651 (1997) ............................................................................................ 69
`
`Free Enter. Fund v. Pub. Co. Accounting Oversight Bd.,
`561 U.S. 477 (2010) ............................................................................................ 69
`
`Freytag v. Commissioner,
`501 U.S. 868 (1991) ............................................................................................ 69
`
`In re Gordon,
`733 F.2d 900 (Fed. Cir. 1984) ............................................................................ 52
`
`Hulu, LLC v. Sound View Innovations, Inc.,
`IPR2018-01039, Paper No. 29 (PTAB Dec. 20, 2019) ...................................... 64
`
`Infineon Techs. AG et al. v. Atmel Corp.,
`No. 11-307-RGA, Dkt No. 174 (D. Del. Dec. 4, 2012) ..............................passim
`
`InTouch Techs., Inc. v. VGo Communs., Inc.,
`751 F.3d 1327 (Fed. Cir. 2014) .......................................................................... 48
`
`Kinetic Concepts, Inc. v. Smith & Nephew, Inc.,
`688 F. 3d 1342 (Fed. Cir. 2012) ......................................................................... 68
`
`Koninklijke Philips NV v. Google LLC,
`948 F. 3d 1330 (Fed. Cir. 2020) ......................................................................... 62
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`
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`

`

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`Kyocera Wireless Corp. v. Int’l Trade Comm’n,
`545 F.3d 1340 (Fed. Cir. 2008) .......................................................................... 64
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`Lucia v. SEC,
`138 S. Ct. 2044 (2018) ........................................................................................ 69
`
`Masias v. Sec’y of HHS,
`634 F.3d 1283 (Fed. Cir. 2011) .......................................................................... 69
`
`Polaris Indus. v. Arctic Cat, Inc.,
`882 F.3d 1056 (Fed. Cir. 2018) .......................................................................... 55
`
`In re Ratti,
`270 F.2d 810 (CCPA 1959) .......................................................................... 49, 50
`
`SRI Int’l, Inc. v. Internet Sec. Sys., Inc.,
`511 F.3d 1186 (Fed. Cir. 2008) .......................................................................... 65
`
`In re Stepan Co.,
`868 F.3d 1342 (Fed. Cir. 2017) .......................................................................... 44
`
`Thryv, Inc. v. Click-To-Call Techs., LP,
`140 S. Ct. 1367 (2020) ........................................................................................ 62
`
`TQ Delta, LLC v. Cisco Sys.,
`942 F.3d 1352 (Fed. Cir. 2019) .................................................................... 49, 64
`
`W.L. Gore & Assoc., Inc. v. Garlock, Inc.,
`721 F.2d 1540 (Fed. Cir. 1983) .................................................................... 37, 40
`
`Wellman, Inc. v. Eastman Chem. Co.,
`642 F.3d 1355 (Fed. Cir. 2011) .......................................................................... 20
`
`In re Wesslau,
`353 F.2d 238 (C.C.P.A. 1965) ............................................................................ 68
`
`Federal Statutes
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`5 U.S.C. § 706 .......................................................................................................... 62
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`35 U.S.C. §102 ......................................................................................................... 64
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`35 U.S.C. § 319 ........................................................................................................ 62
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`-2-
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`PATENT OWNER’S EXHIBIT LIST
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`2002
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`2003
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`2004
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`2005
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`2006
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`2007
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`2008
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`2009
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`2010
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`2011
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`2012
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`Exhibit No. Description
`2001
`Joint Claim Construction Statement dated May 17, 2019
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`Revised Joint Claim Construction Statement dated November 1,
`2019
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`Markman Order re Infineon Technologies AG and Infineon
`Technology North America Corp. v. Atmel Corporation
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`Email Correspondence with Board re Sur-Replies
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`Declaration of Dr. Steven Przybylski
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`Curriculum Vitae of Dr. Steven Przybylski
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`MNSC140CORE Reference Manual
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`ARM920T Technical Reference Manual
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`DDI0275 ETB11 Technical Reference Manual
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`Excerpts from CRC Modern Dictionary Electrical Engineering
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`VDHL Coding Styles and Methodologies, 2nd Ed.
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`Transcript of D Albonesi May 21 deposition
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`Microsoft Computer Dictionary, 5th Ed.
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`Graf Modern Dictionary of Electronics
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`2013
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`2014
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`Patent Owner Aquila Innovations Inc. (“Aquila”) submits this Patent Owner
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`Response to the Petition for inter partes review filed by Petitioner Advanced
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`Micro Devices, Inc. (“Petitioner”) against U.S. Patent 6,895,519 (“the ’519
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`patent”). Paper No. 1. The Petition and corresponding evidence do not show that
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`claims 1-11 of the ’519 patent are obvious. Petitioner’s challenges to the claims
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`rely upon a combination of U.S. Patent 6,65,802 (“Ober”) and U.S. Patent
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`6,681,336 (“Nakazato”). The combination of Ober and Nakazato fails to disclose
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`several limitations of claim 1. Additionally, a person of ordinary skill in the art
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`would not have been motivated to combine Ober and Nakazato, and would not
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`have had a reasonable expectation of success making the proposed combination.
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`Ground 2 fails to show the unpatentability of claims 2-6 because it relies upon
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`conclusory, unsupported expert testimony, and does not establish that Windows
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`ACPI is a printed publication. Ground 3 fails because Petitioner did not adequately
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`show motivation to combine. Petitioner’s combinations and motivations are
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`nothing more than impermissible hindsight, and should be rejected.
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`I.
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`THE ’519 PATENT CLAIMS A NOVEL SYSTEM LSI.
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`The ’519 patent is directed generally at power management techniques in
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`large, complex integrated circuits that include a processor, also known as an
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`“LSI.”1 The ’519 patent teaches power management in an integrated circuit
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`comprising a variety of different subunits, at least one of which is processor
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`including a CPU core. The ’519 patent also discloses a set of mechanisms by
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`which the level/clock frequency of the CPU can be controlled through an
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`application program that interacts with the hardware registers through a clock
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`control library.2 Ex. 1001 at Figure 6, Abstract, 3:35-55, 14:20-22, 14:35-39. Ex.
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`2005 ¶ 39.
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`1 The term “LSI” is an acronym for “large scale integration” and refers generally to
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`“the level integration at which entire integrated circuits can be placed on a chip.”
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`See Ex. 2011 at 385; Ex. 2014 at 412 (technical dictionary definitions of “large
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`scale integration.”).
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`2 See Ex. 2014 at 636.
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`-2-
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`Ex. 1001 at Figures 1 and 2.
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`The system LSI disclosed in the ’519 patent also may include a system
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`control circuit 534, a clock generation circuit 558, a power down control circuit
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`556, and the internal and external buses 521. Ex. 1001 at 6:17-46. The ’519 patent
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`teaches that reducing the frequency of the CPU, or suspending execution of
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`instructions altogether, may reduce the power consumed by the System LSI, a key
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`object of the invention. Ex. 1001 at Abstract, 1:20-26, 1:63-2:9. The CPU 512 in
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`the processor 510 has a number of different modes of operation.
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`“Special” modes are ones in which the CPU is stopped and does not execute
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`instructions. Specifically, there is a halt mode in which clock is stopped “to the
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`principal constituents of the CPU 510”, and a stop mode, in which all clocks
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`throughout the CPU 510 are stopped. Ex. 2005 ¶ 35. The CPU is placed into one of
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`-3-
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`these two modes by software controlling a clock halt register 564. Ex. 1001 at
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`7:28-37, 9:19-26.
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`“Ordinary” operation modes are ones in which the CPU continues executing.
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`In one embodiment, there are 5 “ordinary” operation modes identified as “ST0”
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`through “ST4,” each characterized by the principal clock operating at different
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`frequencies. Ex. 1001 at Figure 5, 9:7-17, 9:46-10:17.
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`The ’519 patent specification refers to a function in the clock control library
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`that changes from one ordinary mode, operating at one frequency, to another
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`ordinary mode, operating at a different frequency. The function is identified as
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`“clkgear.”
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`[W]hen expressing the relation between the current clock
`state and the clock state after transition by using a
`function (clkgear) in the form of the clock control library,
`it becomes possible to dynamically and speedily control a
`plurality of clocks in the ordinary operation mode, as if it
`were a gear-change operation.
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`Ex. 1001 at 4:12-17. See also Ex. 1001 at 4:38-44, 8:60-9:6, 9:64-10:4, 11:33-38.
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`Ex. 2005 ¶ 37.
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`
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`The ordinary operation modes may also be selected by writing values into a
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`register. Ex. 1001 at 8:57-65. The operational frequency of the core CPU in each of
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`the ordinary operation modes corresponds to the frequency of various clock
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`-4-
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`signals, identified as MCLK0, MCLK1, MCLK2, that are provided to the clock
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`generation circuit 558 that generates the FCLK clock signal to the CPU. Ex. 1001
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`at Figure 4, 3:65-4:11.
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`Ex. 1001 at Figure 4. Ex. 2005 ¶ 38.
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`II. ASSERTED REFERENCES
`A. Ober
`Ober is titled “Power Management And Control For A Microcontroller” and
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`relates generally to power management in a microcontroller. Ober’s stated concern
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`is providing power management to each of the peripheral subsystems in a
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`microcontroller, not a central processing unit core Ex. 1004 at 1:25-40. Ober
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`explains that prior attempts to reduce microcontroller power consumption involved
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`slowing the frequency of the system clock or stopping the system clock altogether.
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`Id. at 2:16-20.
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`-5-
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`Ober points out that controlling power consumption of a microcontroller at
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`the central processing unit fails to optimize the power consumption of its
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`subsystems and results in overly complicated and expensive design and
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`development. Id. at 2:21-40. In a microcontroller with a plurality of peripherals on
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`the same integrated circuit as the processor, controlling the power centrally means
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`that all of the peripherals are subject to the same power control policy, even if that
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`policy might not work well for a specific peripheral at a specific time. Id. at 1:22-
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`2:39. Ex. 2005 ¶ 47. In short, all elements are treated the same regardless of need
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`or function. This is inefficient and problematic.
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`Because, Ober believed, “power management of a particular peripheral for a
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`computer system may be best optimized at the peripheral device itself,” Ober
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`sought to “provide a power management system for a microcontroller which
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`enables the microcontroller subsystems to be independently controlled.” Ex. 1004
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`at 2:45-48. See also Ex. 2003, Infineon Techs. AG et al. v. Atmel Corp., No. 11-
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`307-RGA, Dkt No. 174 at * 3-4 (D. Del. Dec. 4, 2012) (district order construing
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`Ober and finding Ober’s goal is “decentralized and independent power
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`management for peripheral units,” not the CPU core). Ober accomplishes its goal
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`by independently controlling either the frequency of the clock or the power
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`supplied to the peripheral systems.
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`-6-
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`1. Ober’s Microcontroller
`To achieve its stated goal of independent power management for peripheral
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`units, Ober discloses a microcontroller architecture that allows the power level of
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`each of the peripheral subsystems to be controlled independently of the CPU.
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`Ex. 1004, Fig. 1. Ober discloses Flexible Peripheral Interface (“FPI”) devices 42-
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`52 that connect each of the peripherals 30-40 to management system 26 and CPU
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`22 through the FPI bus 24. Each of the FPI devices includes a special function
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`register (“SFR”) 116 that “control[s] the response of each subsystem 30-40 during
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`the different power modes of operation.” Id. at 9:21-25.
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`-7-
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`The distribution of the SFR 116 to each FPI “allow[s] the operating system to
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`control each of the subsystems independently.” Id. at 9:49-51. The CPU core 22
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`lacks (1) an FPI interface, (2) a special function register, and (3) a software-
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`configurable register.
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`-8-
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`\
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`Id., Fig. 1. Ober uses the term “subsystem” to refer to each of the peripheral
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`subsystems. Ober refers to the major subsystems 30-40, the power management
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`subsystem 28, and the clock subsystem 64. The CPU core 22, however, is not
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`referred to as a “subsystem.” Ex. 2005 ¶ 62.
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`The management subsystem 26 contains a power manager 28 that controls
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`the power modes of the CPU core and the peripheral subsystems. Ex. 1004 at 5:37-
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`40. “The heart of the power management control system is a power management
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`-9-
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`state machine.” Id. at 17:3-4.3 The state machine includes 8 pre-defined states: “a
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`RUN state 132; an IDLE state 134; a START/SHUTDOWN state 136; a SHUT
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`DOWN state 138; a SLEEP (DEEPSLEEP) state 140; a POWER UP state 142; a
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`WAIT PLL state 144; a FAULT transition state 146; and a RESET state 148.” Id.
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`at 17:6-14; Fig. 6:
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`3 A “state machine” refers to “[a] sequential-logic system whose outputs depend on
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`previous and present inputs (for example, a counter), as opposed to processes that
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`are functions of present inputs alone.” Ex. 2014 at 732. State machines use pre-
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`defined, discreet states defined by these inputs. Ex. 2010 at 656; Ex. 2011 at 304-
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`305.
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`-10-
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`The power manager 28 also contains a programmable special function register 62,
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`which configures the clock subsystem 64. The programmable special function
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`register 62 contains fields that configure the power management state machine’s
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`different modes. Id., Fig. 5.
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`-11-
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`The clock subsystem 64 generates the System Clock and the local
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`Management Clock. Id., Fig. 3. The System Clock is principally derived from a
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`single crystal oscillator by way of a PLL that multiplies the crystal’s frequency,
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`and a clock circuit 108 that divides the frequency to generate the frequency that is
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`required by the CPU Core 22. Id. at 8:53-64, Table 2. Ex. 2005 ¶ 54.
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`The clock subsystem 64 also generates a Management Clock, output from
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`the Management Clock block 110. The Management Clock is internal to the
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`management subsystem 26. It can be derived from a number of different sources,
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`including the System Clock or the low frequency Real Time Clock. Table 7 in
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`Ober shows that the even though the Management Clock can be derived from other
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`sources, during the RUN state, both of these clocks are taken from the Divided
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`PLL Output. Ex. 1004 at 8:53-9:18. Ex. 2005 ¶ 52.
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`-12-
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`1. Ober’s Decentralized Power Control Architecture.
`Ober discloses “up to four power modes” – RUN, IDLE, SLEEP, and DEEP
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`SLEEP. Ex. 1004 at 4:18-19. The core CPU is fully operational in RUN mode, but
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`is stopped in the IDLE and SLEEP modes, including each of the SLEEP submodes.
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`The core CPU may additionally be powered off in the SLEEP and DEEP SLEEP
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`modes.
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`In RUN mode, the CPU, power supply, clocks, and all subsystems are fully
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`functional. Ex. 1004 at 13:49-52. It is the only mode during which the CPU core is
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`executing instructions. Ex. 2005 ¶ 50. In RUN mode, system clock operates on a
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`single, fixed frequency that cannot be selected or altered. Ex. 1001. at 17:15-27;
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`Ex. 2005 ¶ 60. Ober refers to “the clock speed of the CPU” in the singular,
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`indicating that the CPU core has a single operating frequency. Ex. 2005 ¶ 51. Ober
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`does not contemplate the CPU core 22 operating at more than one frequency. Id.
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`(citing Ex. 1004 at 8:59, Table 7). Ober does not mention or suggest lowering the
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`CPU core’s operating frequency to reduce the operating power of the core, even in
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`discussing the control of the operating state of the CPU core 22 by the
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`management subsystem 26 and the power management state machine (PMSM). Id.
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`(citing Ex. 1004 at 8:35-49, 15:14-16, 17:1-26). The RUN mode simply is not
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`identified as one of the modes in which power management occurs and there is no
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`basis on which to conclude that power management was intended or contemplated
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`-13-
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`during RUN mode. During RUN mode, the only possible source for the System
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`Clock is the Divided PLL Output that is output from block 108. Ex. 2005 ¶ 51
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`(citing Ex. 1004 at Tables 7 and 8). The control registers offer no avenue for
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`controlling the PLL multiplier, nor any facility for controlling the Clock circuit 108
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`divisor during RUN mode. Ex. 1004 at Figure 5, Table 5. In fact, low speed clocks
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`are disabled in the RUN state. Ex. 1004 at 12:10-67, 17:1-27. Moreover, because
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`the frequency of the System Clock is not controllable by the SFR 62 during RUN
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`mode (see below), the only power level during ordinary operation mode is full
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`power based on “the clock speed of the CPU core 22.” Ex. 1004 at Tables 7, 8 and
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`9, 8:56-61. Ex. 2005 ¶ 54. It is only during RUN mode that the CPU Core 22
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`executes programs. Id. ¶ 50. Consequently, it is only during RUN mode that any of
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`the special SFR registers can be written. Id..
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`In IDLE mode, on the other hand, the CPU does not execute instructions, but
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`the subsystems may function normally. Ex. 1004 at 13:52-59 (“The CPU core
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`clock is disabled … During [IDLE] mode, all subsystems remain powered up and
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`fully clo[ck]ed.”). The CPU core sets the request sleep bits of the power manager
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`state machine register 62 to IDLE. Id. 15:21-24. The IDLE signal is initiated by the
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`power management state machine in power manager 28 and transmitted to the
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`-14-
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`

`
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`CPU core 22 to turn off its internal clocks to suspend execution of instructions.
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`Ex. 1004, Fig. 1. When the IDLE signal is asserted, the CPU flushes its pipeline
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`and shuts down its internal clocks until the IDLE signal is removed. Once the
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`IDLE signal is asserted, the CPU core 22 asserts the IDLE acknowledge signal
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`when the pipeline is flushed, then halts or disables the internal CPU clock.
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`-15-
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`The CPU is IDLE in each of the IDLE, SLEEP, and DEEP SLEEP modes. Ex.
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`2005 ¶ 50.
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`SLEEP mode is divided into three submodes – “sleep with clocks, no clocks,
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`and deep sleep where power may be disabled.” Ex. 1004 at 15:40-43. Ex. 2005
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`¶ 48. In all of the SLEEP modes, the CPU is in an IDLE state. In “SLEEP MODE
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`(Clocks Distributed),” “the phase lock loop (PLL) or oscillator (OSC) clock is
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`distributed to the subsystems which have been preconfigured to operate in the
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`SLEEP mode.” Ex. 1004 at 14:61-64. The individual peripheral subsystems may
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`-16-
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`

`

`
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`be on or off, as configured in their respective SFR 116. See id. at Table 4 (Sleep
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`Mode Enable, Sleep Divide Clock bits in peripheral special function register 116).
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`The system clock provided to active peripheral devices in SLEEP mode may be
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`divided by 2, 4, or 128, as configured in the SlpClk bits of the power management
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`SFR 62. As a result, the power level to the peripherals may vary. Id. at Tables 5, 7.
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`The CPU, however, remains in an IDLE state during SLEEP mode, with its core
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`having flushed its pipeline and not receiving a clock supply. Id. at 8:39-45. Ex.
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`2005 ¶ 48.
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`In SLEEP MODE (Clocks Not Distributed), the CPU is in an IDLE state and
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`may also be unpowered. SLEEP mode is triggered when “the CPU core 22 sets the
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`power management state machine software configuration register SFR 62 Request
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`Sleep REQSLP bit to SLEEP and the clock source bits and no distribution of clock
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`as indicated in Table 5.” Ex. 1004 16:29-33. The power management subsystem
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`halts the clocks to all of the peripheral subsystems. Ex. 2005 ¶ 49.
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`B. Nakazato
`Recognizing that Ober fails to teach or suggest all of the claim elements of
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`the ’519 patent, the Petition also relies on Nakazato for its purported teaching of
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`“‘a clock control library’ and an ‘application’ for controlling CPU frequency.”
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`Petition at 8. Nakazato relates generally to power savings in computer systems,
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`such as a personal computer, not a microcontroller or LSI. Ex. 1008 at 1:20-24;
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`-17-
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`4:1-5:52 (describing “battery-operable notebook type personal computer (PC)” in
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`accordance with disclosed embodiments).
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`The specification of Nakazato describes a software environment running on
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`a notebook PC. Ex. 1008 at Figure 1, 4:1-16. Ex. 2005 ¶ 64.
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`Ex. 1008 at Figure 1.
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`Nakazato describes a CPU speed control circuit 153 that facilitates control of
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`the CPU speed and power consumption. Nakazato discloses two features for
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`controlling CPU speed and power consumption: the CPU throttling function and a
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`frequency/voltage controlling function called speed-step or Geyserville. Ex. 1008
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`at 4:17-24, 5:53-6:7, 6:8-7:27. Ex. 2005 ¶ 62.
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`The CPU speed can be determined by a user’s selection or by some other
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`factor, such as temperature of the CPU. Ex. 1008 at 4:25-26, 5:40-43, 7:16-19.
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`-18-
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`Id. at Figure 2. Ex. 2005 ¶ 63.
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`Nakazato describes the user’s selection of the CPU’s speed through the
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`interactions between a power-saving utility and a power-saving driver. Ex. 2005 ¶
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`64. The user interacts with a power-saving utility that saves the selection to a
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`predetermined location on the hard disk drive (HDD 161), such as a registry. Id.
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`Separately, the power-saving driver can at its convenience consider the values (if
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`any) written to the registry on the hard disk and determine whether a change in the
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`current power level should be executed. Id. (citing Ex. 1008 at Figure 1, 7:16-27.).
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`The writing to, or subsequent reading from, a registry area in the hard desk
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`is not equivalent to writing a register to change or control the CPU hardware. Ex.
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`-19-
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`2005 ¶ 65; see also Ex. 2013 at 445 (dictionary definitions of “register” and
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`“registry”). Nakazato’s use of a registry area in a hard disk drive is not analogous
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`to using a register to ultimately set the power level of a CPU. Ex. 2005 ¶ 65.
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`Instead, Nakazato teaches that the CPU speed is controlled by writing a CPU
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`Speed Control Circuit register 152 that is in the PCI-ISA Bridge 15. The PCI-ISA
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`Bridge 15 is located in an entirely different integrated circuit than the CPU 11. Ex.
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`1008 at 6:19-21. A person of ordinary skill in the art at the time of the filing of the
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`’519 patent would have recognized the PC architecture of Figure 1 of Nakazato
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`and understood that CPU 1, Host-PCI Bridge 12 and PCI-ISA Bridge 15, as well as
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`a host of other blocks, are each their own individual integrated circuits. Id. at
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`Figure 1, 3:5-7, 4:11-16. Ex. 2005 ¶ 65.
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`III. CLAIM CONSTRUCTION.
`Petitioner identifies three terms for construction: “system LSI,” “a clock
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`control library for storing clock frequency transitions between said ordinary
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`operation modes,” and “principal constituents of said central processing unit.” The
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`Petition does not turn on the construction of these terms and it is not necessary to
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`construe any of them. See Wellman, Inc. v. Eastman Chem. Co., 642 F.3d 1355,
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`1361 (Fed. Cir. 2011) (explaining “claim terms need only be construed ‘to the
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`extent necessary to resolve the controversy’”) (quoting Vivid Techs., Inc. v. Am.
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`Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)). It is necessary, however,
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`to determine whether the preamble of claim 1 is limiting, and to determine that the
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`plurality of ordinary operation modes recited in claim 1 operate at various
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`frequencies.
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`A. The Preamble of Claim 1 Of the ’519 Patent Is Limiting.
`The preamble recites “[a] system LSI having a plurality of ordinary
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`operation modes and a plurality of special modes in response to clock frequencies
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`supplied to a central processing unit.” Ex. 1001 at 14:15-19. Petitioner has not
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`stated whether the preamble is limiting, see Petition at 25 (“To the extent the
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`preamble is determined as limiting …”), but it did find the term sufficiently
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`important that it proposed a construction for the term “system LSI” found in the
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`preamble. There is no reason to propose a construction for “system LSI” if “system
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`LSI” is not part of the claim. Petitioner cannot propose a construction for a term
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`that only appears in the preamble, advocate for that construction, only to hedge its
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`bets by stating that the construction applies only “to the extent” the preamble is
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`limiting. In district court, where the same parties have been litigating for almost
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`two years, Petitioner agrees that the preamble is limiting, and it has not presented
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`any reason why it should be allowed to depart from that position before this
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`tribunal. See Ex. 2001 at 1; Ex. 2002 at 2.
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`The preamble is limiting, of course, because it recites an essential element of
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`the invention, the “system LSI.” See Bicon, Inc. v. Straumann Co., 441 F.3d 945,
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`952 (Fed. Cir. 2006) (“[T]he preamble is regarded as limiting if it recites essential
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`structure that is important to the invention or necessary to give meaning to the
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`claim… if the claim drafter ‘chooses to use both the preamble and the body to
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`define the subject matter of the claimed invention, the invention so defined, and
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`not some other, is the one the patent protects.’”) (internal citations omitted). The
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`invention claimed in claim 1 is not complete without the term “system LSI,” nor is
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`the remainder of the preamble. Even Petitioner’s proposed construction requires a
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`chip.
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`In addition to reciting necessary structure, the preamble also provides the
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`antecedent basis for the “ordinary operation modes,” “special modes,” and “central
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`processing unit,” each of which is recited in the body of claim 1. “When the
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`limitations in the body of the claim rely upon and derive antecedent basis from the
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`preamble, then the preamble may act as a necessary component of the claimed
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`invention.” Bicon, 441 F.3d at 952 (internal citations and quotations omitted).
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`Here, because the preamble provides antecedent basis for several limitations in the
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`body of the claim, it is a necessary component of the claimed invention. The
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`preamble of claim 1 of the ’519 patent should be construed as limiting.
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`B.
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`The “Plurality Of Ordinary Operation Modes” Operate At
`Different Clock Frequencies Supplied To The CPU.
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`The preamble of claim 1 recites “a System LSI having a plurality of ordinary
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`operation modes and a plurality of special modes in response to clock frequencies
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`-22-
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`supplied to a central processing unit.” Ex. 1001 at 14:15-17. Patent Owner and
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`Petitioner both agree that the ordinary operation modes operate at various
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`frequencies:
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`With respect to the functioning of the “ordinary operation
`modes,” claim 1 requires: (1) that clock frequency
`transitions occur between ordinary operation modes 1;
`and (2) that such clocks are supplied to a central
`processing unit. EX1001, 14:20-22. To state it another
`way, the claimed ordinary operation modes operate at
`different frequencies.
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`Ex. 1003 ¶ 102 (emphasis added). As Petitioner correctly notes, claim 1 requires
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`clock frequency transitions between the ordinary operation modes. Petitioner also
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`correctly notes that the ordinary operation modes “operate” at different
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`frequencies. In other words, the CPU core executes instructions at a rate
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`determined by the frequency of the supplied clock signal of each ordinary
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`operation mode. Conversely, any mode in which the CPU is not executing
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`instructions is not an “ordinary operation mode.” Ex. 2005 ¶ 45.
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`The ’519 patent teaches that the ordinary operation modes are achieved by
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`varying the frequency of the clock signal used by the CPU during operations,
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`FCLK.
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`In case of the CPU 510, the clock FCLK for use in the
`core CPU and others could be set in detail in the register
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`group inside the system control circuit 534 as shown in
`FIG. 3. The function capable of dynamically and speedily
`controlling the clock group like this will be called “Clock
`Gear” hereinafter in the present specification.
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`Ex. 1001 at 8:56-65. The ’519 patent