`571-272-7822
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`Paper 36
`Entered: January 4, 2021
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`
`v.
`
`AQUILA INNOVATIONS, INC.,
`Patent Owner.
`____________
`
`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
`____________
`
`Record of Oral Hearing
`Held: December 11, 2020
`____________
`
`Before SALLY C. MEDLEY, DENISE M. POTHIER, and
`AMBER L. HAGY, Administrative Patent Judges.
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`
`
`
`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`APPEARANCES:
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`ON BEHALF OF PETITIONER:
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`
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`MICHAEL D. SPECHT, ESQUIRE
`DAN BLOCK, ESQUIRE
`CHRISTOPHER R. O’BRIEN, ESQUIRE
`LAUREN C. SCHLEH, ESQUIRE
`Sterne, Kessler, Goldstein & Fox P.L.L.C.
`1100 New York Avenue NW Suite 600
`Washington, D.C. 20005
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`
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`ON BEHALF OF PATENT OWNER:
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`
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`JING H. CHERNG
`Freitas & Weinberg, LLP
`350 Marine Parkway Suite 200
`Redwood City, CA 94065
`(650) 593-6300
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`
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`
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`The above-entitled matter came on for hearing on Friday, December
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`11, 2020, commencing at 10:00 a.m. EDT, via Video/Teleconference.
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`2
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`
`P R O C E E D I N G S
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`- - - - -
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`
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`JUDGE HAGY: This is our combined hearing for IPR2019-1525
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`and IPR2019-1526 between Petitioner Advanced Micro Devices, Inc. and
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`Patent Owner Aquila Innovations, Inc. The challenged patents are
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`6,239,614B1 and 6,895,519B2, respectively. I’m Judge Hagy. With me
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`today on the panel are Judges Medley and Pothier.
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`So let’s go ahead and start with counsel introductions. Petitioner,
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`please identify yourself, who will present arguments.
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`MR. SPECHT: Good morning, Your Honor. This is Michael Specht
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`on behalf of Petitioner. I will be arguing for the 1525 IPR for the 614
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`patent. And my colleague Dan Block will be arguing for the 1526 IPR.
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`JUDGE HAGY: Thank you. And for Patent Owner.
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`MR. CHERNG: Good morning. My name is Jing Cherng on behalf
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`of Patent Owner Aquila Innovations, Inc. and I will be arguing both patents.
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`JUDGE HAGY: Okay, great. Welcome everyone, it’s great to have
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`you here. And we appreciate that you’re doing this by video. So if at any
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`time during the proceeding you encounter any kind of technical difficulties, I
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`think you’ve been in communication with our IT team so please reach out to
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`them for any information on reconnecting and please just let us know. We
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`want to make sure that everyone can be heard, present their arguments.
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`So we set forth the procedure for the hearing in the Order. We’re
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`going to hear both of the cases at the same time, but our plan is to hear the
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`complete arguments on 1525 and then we can turn to the complete
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`arguments on 1526. I think that especially makes sense given that Petitioner
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`is going to have different counsel argue for each of the cases. So are there
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`any questions or concerns about that before we keep going? That’s good?
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`Okay.
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`As we said in the Order, each of the parties has 60 minutes to present
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`its arguments, which they may divide up as they see fit between the two
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`cases. So you know there’s no need that you have to spend an exact amount
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`at the same time, 30 and 30 on each case, you can divide it as you would
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`like.
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`We do have the whole record in front of us, including the slides that
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`were submitted on Tuesday. And we also have received Petitioner’s
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`objections to some of Patent Owner’s slides. At this point we’re not going
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`to make a ruling on those objections. Patent Owner may present those slides
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`and Petitioner may point out as part of its argument issues it has with the
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`slides and we will take those under advisement.
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`So we have a clear record, because we have your slides, we will
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`follow along on our screen, it’s especially important to let us know which
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`slide number that you’re on, any exhibits or anything that you’re
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`referencing, and maybe give us a second to make sure that we can find it if
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`you’re jumping around. Also please mute the line when you’re not
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`speaking, and if it has been a little while since you have spoken, please
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`identify yourself for the court reporter.
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`After our time is up we’re going to pause and just check in with the
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`court reporter, see if there are any spellings or any concerns to address. But
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`our court reporter does have a lot of the materials so the spellings should be
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`clear from the record.
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`So as you’ll know, the Petitioner does bear the burden of persuasion
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`here and will proceed first, followed by Patent Owner. Petitioner may
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`reserve time for rebuttal. Patent Owner may reserve time for sur-rebuttal.
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`Again, as I previously mentioned, we’re going to go case by case. So at this
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`point please let us know how you would like to divide up your time.
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`Petitioner?
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`MR. SPECHT: Thank you. Yes, Your Honor. We intend to use 30
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`minutes for the 1525 matter and I would like to reserve 10 minutes for
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`rebuttal in that matter.
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`JUDGE HAGY: Okay. And so do you want to do this, are you going
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`to do the same in both cases, 30 with 10 rebuttal?
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`MR. BLOCK: Yes, Your Honor. This is Daniel Block on behalf of
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`AMD. We’re 30 on the second one.
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`JUDGE HAGY: Okay. And Patent Owner?
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`MR. CHERNG: Same for me as well, Your Honor, thank you.
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`JUDGE HAGY: Okay. So obviously, you know, we’re all at home or
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`in our office, we don’t have the traffic light system to let us know, so I
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`assume that you guys will keep time. But would you like us also to, I’ve got
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`a little stopwatch here, I can let you know how much time that I have
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`according to me, how much time you have left. Do you want any sort of a
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`warning when you’re nearing the end of say 20 minutes and running into
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`your rebuttal time?
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`MR. SPECHT: Your Honor, yes, this is Mike Specht. That would be
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`helpful, thank you.
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`JUDGE HAGY: Okay.
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`MR. CHERNG: Your Honor, this is Jing Cherng. That would be
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`very helpful for me too. Thank you.
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
`
`
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`JUDGE HAGY: Okay, great. All right. So, again, we want to keep
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`the arguments focused on the merits of the case so I assume you guys are
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`experienced at this. We don’t interrupt the other side to make objections,
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`you know, this is not district court. You can raise and discuss any objections
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`you have to the other side’s evidence arguments during your own time for
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`response, rebuttal, sur-rebuttal, et cetera.
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`So with all of that I just want to make sure the court reporter is on and
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`ready and everyone can be clearly heard and seen. All good?
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`COURT REPORTER: Yes, Your Honor.
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`JUDGE HAGY: All right. So with that we’re going to go ahead and
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`begin with Petitioner’s arguments on 1525.
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`MR. SPECHT: Thank you, Your Honor, and good morning to all of
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`the judges again. Just for the record my name’s Michael Specht, here on
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`behalf of Petitioner AMD. With me on this particular case is also Chris
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`O’Brien, one of the counsels as well. He is also at the firm of Sterne,
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`Kessler.
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`I would like to begin by directing your attention to our Slide 2. This
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`is a quick summary of the case. As you know, there are three grounds.
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`Grounds 1 and 2 address Claims 1 and 3, and Ground 3 addresses Claims 4
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`and 5. There are two independent claims, Claim 1 and Claim 4. I will direct
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`most of my time today to Ground 1. The arguments that we make for
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`Ground 1 are very similar to those for Ground 2. I’ll certainly be happy to
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`answer any questions you may have but given the time limits I’ll focus on
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`Ground 1, and will briefly touch on Ground 3 with respect to Claims 4 and
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`5.
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`At the onset I would observe that with respect to Ground 3, Patent
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`Owner’s arguments are mere attorney arguments. They provide no expert
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`declaration in support of their positions with respect to Ground 3.
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`Now turning to our Slide 3. A quick overview. First of all it’s our
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`view that the Petition could have demonstrated that all claims, Claims 1
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`through 5 were challenged, are unpatentable. It is also undisputed in the
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`record that the prior art discloses each and every claim element. The only
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`dispute to this point, we are looking here first with respect to Ground 1 and
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`2, whether a person of ordinary skill in the art would be motivated to
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`combine the references that were used. And similarly with respect to
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`Ground 3, a motivation to combine argument. I will obviously focus my
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`attention on the motivation to combine argument.
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`If we now turn to Demonstrative Slide 4, Petitioner’s Slide 4 where
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`we have laid out the claim here with Independent Claim 1. And what you
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`see highlighted in yellow is in fact the only claim term that is in dispute with
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`respect to the motivation to combine. The argument being that we have not
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`demonstrated a motivation to combine the references in Ground 1 or Ground
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`2 to disclose this element of a power switch.
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`To give ourselves some context in the patent, I’d like to now turn to
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`Demonstrative Slide 5. Demonstrative Slide 5 is just to give us bearings for
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`the claim. What you see highlighted in red are the unit cells with a low
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`threshold MOSFETS. What you see in the blue, the high threshold
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`MOSFETS, these are the initial elements of the claim. And what’s critical
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`for discussion today is what’s highlighted in green are the power switches
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`disclosed around the gate array. And I’ll focus my comments on that as
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`mentioned.
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`Now turning to Slide 8, Petitioner Demonstrative Slide 8. We focus
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`in on our combination with respect to that element, the power switch
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`element. In Ground 1 we rely on two references, Urano reference and
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`Mutoh021. It’s our view that Urano discloses all elements to meet the claim.
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`It discloses the power switch but it doesn’t explicitly talk about disposed
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`around that element of the power switch claim, or claim element. And that’s
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`what we bring Mutoh021 in for, to disclose the power switch disclosed or
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`disposed around the gate array.
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`Turning to Demonstrative Slide 9, Demonstrative Slide 9 is
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`highlighting very briefly the Urano reference showing the power switch,
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`highlighted in green. In Urano there’s no dispute that it teaches the gate
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`array. And you see here highlighted that it has the power switch cells on the
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`vertical, on the right and left on the vertical. And as I mentioned earlier
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`there, it does not explicitly disclose that the power switches are comprised
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`around the gate array, which is what we use Mutoh021 for which is
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`presented on our next slide, Demonstrative Slide 10.
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`Demonstrative Slide 10 we’re showing two figures from Mutoh021.
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`These figures highlight they have power switches either on the vertical or
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`the horizontal ends of the gate array. But what’s critical about this slide and
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`critical about the disclosure of Mutoh021 is what’s highlighted at the bottom
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`of this slide in yellow. Where it clearly indicates that the power switches are
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`disclosed or disposed at all ends vertically and horizontally, thus meeting the
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`disposed around limitation.
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`So there really is no dispute that Urano teaches the elements of the
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`claim that lead to Mutoh021 teaches disclosed round. The dispute is that a
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`person of ordinary skill in the art would not be motivated to combine these
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`two references. And we think there’s no basis in that. Patent Owner’s
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`arguments, they’re basically alleging that our expert’s testimony is
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`conclusory, our positions are based on hindsight, et cetera. We don’t believe
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`that to be the case.
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`And if we now turn to Petitioner’s Demonstrative Slide 11, we talk
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`about this issue. So here what we’re highlighting is the support that we
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`provided to show the motivation to combine. And we’ve highlighted a
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`couple points on this slide. First of all, Dr. Holberg, an industry expert with
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`40 years of experience in this art, identified the motivations to combine,
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`design efficiencies of reduced noise and voltage drops due to parasitic
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`resistance but would be achieved if you add the power switches on all four
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`sides of the cell or all four sides and then within the cell array.
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`And that’s corroborated here, it’s not just his opinion, but it’s what
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`was known at the time by a person of ordinary skill in the art. And we make
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`reference here to Exhibit 1025. Exhibit 1025 is the CMOS textbook, which
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`as you can see from the text here, is highlighting this issue. Many of the
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`problems encountered with designing a chip can be related to the distribution
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`of power and ground. So it’s highlighting the issue, but more critically is the
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`next corroborating reference, Exhibit 1017. This is a 1984 IEEE article.
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`And you see the quote that we have highlighted here, the power supply
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`terminals are located on all four sides of the chip. And the chip in that
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`reference is also a gate array, to reduce the voltage drops in power busses
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`caused by the maximum power supply current.
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`So not only do we have an expert with 40 years of experience talking
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`about why one would be motivated to place power switches around the gate
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`array, but we also have a reference from 1984 highlighting and supporting
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`that position.
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`Now additionally beyond this --
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`JUDGE HAGY: Counsel, I have a quick question on this. Does it
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`need to be the case that having it on all four sides is the best arrangement?
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`MR. SPECHT: It does not. Case law is clear we just have to show an
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`advantage, we don’t have to distinguish between multiple different design
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`choices essentially. This clearly has an advantage of having it dispersed
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`around all four, or around the gate array. And we addressed that question
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`even more specifically, Your Honor, in our Petitioner Reply, which again
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`was supported by Dr. Holberg’s Declaration. And I would reference his
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`Declaration at Paragraphs 22 of Dr. Holberg’s Declaration where he talked
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`about the specific advantages of having the power switches disposed
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`completely around. And he focused on how that improves power
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`performance to cells that are in the gate array, that are in the middle of the
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`gate array. It reduces glitches, power glitches, and has improved
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`performance by using this particular arrangement. But even to the extent
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`that we don’t need to show it, we did show it. All right. But there’s this
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`specific advantage associated with power cells surrounding the chip.
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`That’s further not just his opinion again, we corroborated that with an
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`additional IEEE article that was entitled “20,000 Gate, CMOS Gate Array”
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`where they discuss the specific advantages of the power switch reducing
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`power supply glitches, pursuant to what Dr. Holberg was saying. And that
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`reference is from 1983. This is a problem that industry knew about that
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`persons of ordinary skill were well aware of and it was well aware to
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`implement power switches around the exterior encircling the gate array.
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`Now I may move on to Petitioner’s Slide 12. This again just further
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`elaborates the point. It expands on some of the other benefits associated
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`with having the power switches around the periphery of the chip. And you
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`see highlighted in green there circuit design efficiencies, reducing wearing
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`complexity, reducing resistance, decreasing response times, et cetera. All in
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`an effort to achieve the low voltage high speed operations of Urano and gate
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`array chips in general.
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`JUDGE HAGY: Counsel, why is it that you suppose that if having it
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`all the way around is especially advantageous, why is it that neither Urano
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`nor Mutoh021 actually depicts that? I mean I know that Mutoh021, as you
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`know, does describe it in one sentence, but it doesn’t actually show it in a
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`figure. What can we take away from that?
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`MR. SPECHT: What I take away from that is these were design
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`choices that were widely known already, and in Mutoh021 was enumerating
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`that the various choices, and one being surrounding the chip entirely with
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`power switches. And as Dr. Holberg testified and these other references
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`highlighted, there are specific advantages of that solution, particularly with
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`cells that are in the middle of the gate array, improving their performance.
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`Frankly I think all of this was very well known years, if not decades, before
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`this alleged invention of the 614. And that’s supported by the record. It
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`doesn’t really matter what I think, but that’s what the record shows.
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`And moving on to Demonstratives Slide 13, Demonstrative Slide 13
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`simply highlighting that this would be an easy solution. There would be no
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`issues with combining these references in terms of the design consideration
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`Dr. Holberg talks about. Now this was widely known to use power switches
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`surrounding the gate array up to the computer-aided design tools that would
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`easily make this change. So there’s no issue about how you would combine
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`these references as well.
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`Now if we turn to Petitioner’s Demonstrative Slide 15. I’ll just very
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`quickly sum up Patent Owner’s arguments. Here one of their arguments was
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`because Urano does not disclose the problem, a POSA in the art would have
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`no reason to look to Mutoh021. But we know that’s not the law. The
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`decisions are long based as a legal matter and also the factual matter. This is
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`one where it’s won on the law. You don’t have to have that rationale
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`specifically in the reference, and that’s well documented. We just provided
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`a cite here to the MPEP, and as we’ve shown, a person of ordinary skill in
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`the art would have recognized or had the motivation to define these
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`references by recognizing the issues with distribution of power.
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`If I now turn to Demonstrative Slide 16. And this, Your Honor, I
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`believe goes to you’re talking about, you know, the Patent Owner’s
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`response, Mutoh does not disclose any advantage associated at all ends
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`vertically and horizontally. And there’s two elements to that. One, and this
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`one is incorrect, there’s two aspects. One, in the absolute are there any
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`advantages discussed? And then relative to all the other potential
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`arrangements for power switches, are there advantages discussed? And as I
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`discussed earlier, there are. I mean Mutoh021 specifically talked about
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`advantages in terms of improving performance both for low voltage high
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`speed chips.
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`And then if we turn to our Demonstrative Slide 18. This is really a
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`summary of the points that we made, where Dr. Holberg’s supported by a
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`plethora of supporting corroborating references identified, reducing wiring
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`complexities, the parasitics, better response time, increased pattern layouts.
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
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`And it’s further expanded in Dr. Holberg’s revised Declaration again, that’s
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`Exhibit 1048. Whereas I mentioned earlier, Paragraph 27, he goes into
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`details of how having the power cells at the top and the bottom around the
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`chip reduces resistance, improves performance where cells that were in the
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`central part of the gate array.
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`Lastly with respect to this issue, and importantly, on Demonstrative
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`Slide 19, Dr. Przybylski, and we can spell that later for the court reporter.
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`Dr. Przybylski admitted that there are advantages to having the power switch
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`surround the gate array. And so the question at that, what are the benefits of
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`placing the power switch cells around either side of the unit cell array. And
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`his answer “Yes, the more efficient design overall. There are benefits that
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`are not specifically articulated within the 614 patent but are completely
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`understood by a person of ordinary skill in the art.” And, one, he’s
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`confirming it, and two, this just highlights the notion that this was really a
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`well-known kind of invention by a person of ordinary skill in the art, so
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`much so they didn’t have to mention it in the 614 patent. And Dr.
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`Przybylski concurred that, yeah, a person of ordinary skill in the art at the
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`time would have known this.
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`So all of that, in sum, we think there is a strong motivation to combine
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`these two references, the Urano and Mutoh021. And very similar arguments
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`apply in Ground 2 which I’ll refer you to the papers on those. I see I’m
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`fairly close to my time here. And the arguments are very similar. So I refer
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`to in the Brief, as are their arguments in opposition to that.
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`Now if I could take just a moment to move on to Petitioner’s
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`Demonstrative Slide 31. I’ll give you a second since we’re skipping all this
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`here. And what I’d like to do is simply move on to our Ground 3, briefly
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
`
`touch on that argument with respect to in this case a person of ordinary skill
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`of the art. Their argument is would not combine the prior art to disclose the
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`capacitor limitations, specifically that they’re constructed by connecting M-
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`MOS transistors placed within the unit cell. And again, we believe that’s
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`wrong.
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`If I turn to Petitioner’s Slide 32, this is Claim 4. There’s no dispute
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`again, where these elements are taught, it’s just a motivation to combine
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`argument. And specifically it’s that last element that’s highlighted in yellow
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`wherein latch circuits, said logic circuits, said first and second capacitors,
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`which are a reference in the prior two elements, are constructed by
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`connecting MOS transistors. So when we look at that issue, if we turn to
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`Petitioner’s Slide 33. Here we’re combining the Douseki with Ramos. The
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`second discloses every element of those claims. What it doesn’t specifically
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`disclose type of capacitor? You can see it in the diagram here on the left in
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`Figure 4. There’s a first and second capacitor, those are the decoupling
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`capacitors. The use of decoupling capacitors (audio skip). For the purpose
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`of regulating voltages is probably as old as time, or at least as old as a
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`capacitor, is well known in the art.
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`If we then turn to Petitioner’s Slide 34, the next slide. This is where
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`we talk about Ramus. Ramus discloses the capacitor being used for a
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`decoupled capacitor. What’s important is they specifically identify that
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`they’re MOS transistors. And so, you know, this is a pretty basic motivation
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`to combine situation.
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`If we turn to Demonstrative Slide 35. So what we have is on one hand
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`Douseki discloses this integrated circuit using these decoupling capacitors,
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`but doesn’t tell you specifically how they’re made. The motivation would
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
`
`then be to find out, with two other arguments, put this together and so it’s
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`highlighted here in Demonstrative Slide 35. Again, this is an excerpt from
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`Dr. Holberg’s Declaration were highlighted in green. I’ll just read this for
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`the record. “The capacitors formed by the MOS transistors in the standard
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`cells can be distributed over the entire integrated circuit in small portions,
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`which can then effectively reduce circuit noise and increase voltage
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`stability.” There’s your motivation of what the stability would be reducing
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`circuit noise, which is, quite frankly, well known.
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`Lastly, on just more of the same on Petitioner’s Demonstrative Slide
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`36 further support from Dr. Holberg explains why one would be motivated
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`to combine these references. And there really would be no issue, it was
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`widely known to use MOS capacitors for those purposes, which is what he
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`highlights in his declaration. And again, I’ll reiterate the comment I made at
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`the beginning of my comments here. There is no expert testimony provided
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`by Patent Owner here to dispute, it’s purely attorney argument. And as we
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`all know, attorney argument, for better or for worse, gets minimum weight.
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`We need to rely on the expert opinions, and there are none here.
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`JUDGE HAGY: Counsel, you are now going a little bit into your
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`rebuttal, or were you wrapping up? Okay. Just letting you know.
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`MR. SPECHT: I’m going to wrap up. I will complete my comments
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`unless you have any further questions on these issues. But bottom line we
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`think this is a pretty straightforward case. (Audio skip) here, the five
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`challenged claims, the institution decision was like that. I know that’s
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`preliminary, but no reason to deviate from your findings in the institution
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`decision.
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`Thank you. Unless you have any other questions I’ll pause now.
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
`
`
`JUDGE HAGY: I just wanted to ask the court reporter. I’m getting a
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`little bit of choppiness at the end of your speaking. I just want to ask if the
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`court reporter is able to hear everything okay.
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`COURT REPORTER: Yes, Your Honor. I am also hearing that, but
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`I think when we put the words together we’ll be able to make out everything
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`that’s being said.
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`JUDGE HAGY: Okay.
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`COURT REPORTER: But you’re right, there is a little choppiness
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`there. The only thing that I would ask is that counsel comes back to the first
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`one, if you could try to move a little bit closer to your phone or the speaker it
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`might help.
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`MR. SPECHT: I just got a message from Pete, an IT person, to just
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`dial in so I’ll deal in and, you know, connect via phone. You’ll still have my
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`video.
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`JUDGE HAGY: Okay, that sounds good. I was able to follow your
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`argument but I just want to make sure that we do have a complete record.
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`MR. SPECHT: Yes, thank you, Your Honor.
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`COURT REPORTER: Thank you.
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`MR. SPECHT: Thank you.
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`JUDGE HAGY: Okay. Is Patent Owner ready to go?
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`MR. CHERNG: Yes, Your Honor, thank you.
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`JUDGE HAGY: Okay. Go ahead.
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`MR. CHERNG: Okay. The Petitioner in this case has not shown that
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`a person of ordinary skill in the art would have been motivated to combine
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`Urano or Mutoh with Mutoh021 to realize any of the circuit efficiencies that
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
`
`the claim would have actual predicates upon which their theories are based
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`have been shown, is not true.
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`And I would direct the Board’s attention to Slide 14 of Patent
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`Owner’s Demonstratives. As Mr. Specht has indicated, Mutoh021, the
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`secondary reference in this case, it contains the key limitation that Petitioner
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`contends, of a person of ordinary skill in the art would have been motivated
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`to use to modify the two primary references.
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`JUDGE HAGY: Counsel, I hate to interrupt. Just a quick question up
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`front. Patent Owner had raised some potential claim construction disputes.
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`Are those anything that you want to argue during this hearing? Anything
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`you’d like to --
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`MR. CHERNG: No, Your Honor. We don’t think that the dispute
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`turns on any of the constructions. But we do disagree with the constructions,
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`as we argued in the preliminary Response. But in our view because
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`Petitioner hasn’t shown a motivation to combine any of the references, that
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`the Board need not reach the issue of the construction of the terms.
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`JUDGE HAGY: Right. It also struck me at least that Patent Owner
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`was arguing for broader constructions than what Petitioner seemed to be
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`arguing for in general. And so I think at least as we found in the DI that it
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`wasn’t really material to our decision. So I just wanted to, you know, give
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`you a chance to say anything that you felt like you needed to say on that.
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`Okay. Go ahead.
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`MR. CHERNG: All right. Thank you, Your Honor. So as the Board
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`can see from Slide 13, the Petition cites to Paragraph 35 of Mutoh021,
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`Paragraph entitled “Effects of the Invention” to justify the supported
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`advantages to the on all sides of arrangement. But as you can see from
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`IPR2019-01525 (Patent 6,239,614 B1)
`IPR2019-01526 (Patent 6,895,519 B2)
`
`Paragraph 35, the cite of the bolded portion is the portion that Petitioner
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`cited to. But the full quote shows that Mutoh021 didn’t disclose or didn’t
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`disclose any advantages to any particular arrangement. What it says there is
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`“A cell array composed of second basic cells have a high threshold voltage
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`field effect transistors is arranged adjacent to a cell array composed of first
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`basic cells having low voltage field effect transmission.” And “as a result, a
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`MT-CMOS circuit using high threshold transition voltage transistors and
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`low threshold voltage transistors can be realized on a single LSI chip
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`without reducing cell utilization rate.”
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`You see there the reported advantage which stems only from the
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`second basic cells being arranged adjacent to the unit cell and not in
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`particular because of any arrangement disclosed in Mutoh021.
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`So not having any basis in Mutoh021 to contend that the proposed
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`combination has any advantages, Petitioner relies on the testimony of Dr.
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`Holberg to supply the purported motivation to combine.
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`If you turn your attention, please, to Slide 18. Slide 18 duplicates the
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`portion of Dr. Holberg’s conclusory testimony regarding the purported
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`motivation to combine. In particular Dr. Holberg asserts that a person of
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`ordinary skill in the art would have wanted to have make this asserted
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`combination to realize certain circuit design efficiencies, reducing wiring
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`complexity, reducing resistance between components, decreasing response
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`times between certain components, and increased layout pattern density.
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`But Dr. Holberg doesn’t explain why any of these circuit design efficiencies
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`are achieved through the asserted claim combination.
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`Turning to Demonstrative Slide 25, Dr. Holberg testifies that making
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`the asserted combination would reduce wiring complexity but he doesn’t
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`IPR20