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`AQUILA - Ex. 2003
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`b. The term "said comparator being in operation at a supply voltage above the
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`secondlimit value" is construed to mean “said comparatoris turned on at a supply
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`voltage above the secondlimit value, andis turned off at a supply voltage below the
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`second limit value.” See col.4 1.62 - col.5 1.4; col.3 Il. 36-43.
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`c. The term "the oscillator being in operation at a supply voltage above the
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`secondlimit value" is construed to mean “the oscillator is turned on at a supply voltage
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`above the secondlimit value, and is turned off at a supply voltage below the second limit
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`value.” See col.3 Il. 17-19; col.3 11.48-50; col.4 II.5-7, 47-53; col.5 1114-21.
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`2. The term “activation signal” is construed to mean "a signal, other than thereset signal,
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`that turns on or resumesoperation of the processorunit." The intrinsic evidence providesthat the
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`processor unit “is not activated until the activation signal As appears,” to the exclusion of the
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`eeaaaEnageeeapIPCEigSgrRNSREReES,aPPAttsRETDe
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`reset signal Rs. Col.3 Il.50-51; Fig.1.
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`II. U.S. Patent No. 6,076,159
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`1. The term “loop instructions” is construed to mean “a statement or expression
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`consisting of an operation and its operands(if any), which can be interpreted by a computer in
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`order to perform a loop function or operation.” There is no intrinsic evidence to support limiting
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`this term to conditional jump instructions, which the patent distinguishes from loops. See col.7
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`11.5-8.
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`2. The term "a secondpipeline for executing loop instructions" is construed to mean "a
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`pipeline that only executes loop instructions." The claimed architecture requires a dedicated
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`1999 at 3; Resp. dtd. Oct. 8, 1999 at 5). Where there is one “main”pipeline as in Claim 5,the
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`pipeline for loop instructions. Col.2 1.67 - col.3 1.2; D.I. 164 at 22, 28 (Off. Action dtd. July 12,
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`TeieSeeeenenAtOPRPEINTH
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`dedicated pipeline is the “second pipeline,” and where there are two “main”pipelines, the
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`dedicatedpipelineis the “third pipeline.” E.g., Fig.3; col.2 1.67 - col.3 1.2.
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`III. U.S. Patent No. 6,653,963
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`|. The terms "in a channel-specific way as a function of a signal channel whichis to be
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`converted," "in a channel-specific way as a function of the signal channel to be converted," and
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`"in a channel specific way .
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`.
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`. as a function of the signal channel to be converted"are given their
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`plain and ordinary meaning. Atmel’s proposed construction does notlimit or clarify the terms.
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`2. The term "assigning certain settings for the operating parameters of the A/D converter
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`arrangement which are to beset, to individual requesting means"is given its plain and ordinary
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`meaning. Atmel drawsits proposed limitations from claim 18. (D.I. 154 at 35). Because these
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`limitations are already explicitly claimed in independent claim 18, there is no reason to import
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`them into this claim term, which appears in independent claim | and its dependentclaims.
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`3. The term “setting the operating parameters of the A/D converter arrangement which
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`are to be set, in agreement with the settings assigned to said requesting means making a request”
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`is given its plain and ordinary meaning. Atmel’s proposedlimitation is not supported by the
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`specification and doesnotclarify the term.
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`IV. U.S. Patent No. 6,665,802
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`1. The term “bus interface” is construed to mean “a bus interface that includes a software
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`configuration register.” “Bus interface” has a plain and ordinary meaning. Theintrinsic
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`evidence indicates that to accomplish the goal of the invention (decentralized and independent
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`power managementfor peripheral units), each peripheral unit’s bus interface (“FPI’”) includes a
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`software configuration register.
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`‘802 Patent at [57]; col.2 1.62-col.3 1.6. Claim 7 includes the
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`additional elementthat each register“allow(s] a corresponding peripheral device to respond
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`independently to the power managementcontrols.” Claim 5 already requires that the peripherals
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`receive “power managementcontrols” throughtheir bus interface, so it is not proper to limit the
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`term “businterface” to require “storing power modes” as Atmel suggests.
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`2. The term “each peripheral device including a businterface” is construed to mean
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`"each peripheral device has its own bus interface." To accomplish the goal of the invention
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`(decentralized and independent power managementfor peripheral units), each peripheral unit has
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`its own businterface. Fig.1; col.2, ll.62-65; col.3, ll.1-6; D.I. 164 at 76-77, 83-85 (Resp. dtd.
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`June 19, 2003 at 9-10, 16-18).
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`3. The term "individually configuring a response of each of the one or more subsystems
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`to the global power management commandthrougha correspondingregister in each of the one or
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`more subsystems" is construed to mean "each subsystem is separately configured to respond to
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`the global power management command throughits own separate register." To accomplish the
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`goal of the invention (decentralized and independent power managementfor peripheralunits),
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`eachperipheral unit has its own bus interface (“FPI’”) that includes a software configuration
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`register.
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`‘802 Patent at [57]; Fig.1; col.2, 11.62-65; col.3, ll.1-6; D.I. 164 at 76-77, 83-85 (Resp.
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`dtd. June 19, 2003 at 9-10, 16-18). V. U.S. Patent No. 6,769,065
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`1. The term “access authorization monitoring device" (“AAMD”)is construed to mean "a
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`security device that monitors and prevents any attempted access by a debugger device to
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`protected on-chip components,unless the debugger device has verified authority.” The AAMD
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`monitors for verified authority; neither the AAMDnorthe debugger mustverify or generate that
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`authority, and other appliances can producethe authority. Col.4 II.1-7, 55-57. “Permission”is
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`too broad; the patent discloses the additional concept of verification. D.I. 171 at 14; col.4 II.1-7.
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`2. The term “verified authorization” is construed to mean “access permitted only to
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`authorized holders of a debugging device or other appliance but not to others.” Theintrinsic
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`evidence provides that authorization verification can be produced by “the debuggeror other
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`appliance” and authorizes holders of those devices to access the claimed programmable unit.
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`Col.4 I1.55-57.
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`VI. U.S. Patent No. 6,788,235
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`1. The term "synchronizing the analog-to-digital converter with at least one other
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`analog-to-digital converter of the plurality of analog-to-digital converters" is construed to mean
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`"using a bidirectional procedure to cause the analog-to-digital converter to start simultaneously
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`with at least one other analog-to-digital converter of the plurality of analog-to-digital converters."
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`Theintrinsic evidence indicates that synchronizing is performedbidirectionally, with a preferred
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`embodiment via handshaking. Col.5 11.13-19; D.I. 165 at 20 (Resp. dtd. July 30, 2002at 3).
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`During prosecution, the applicant disclaimed an unidirectional procedure to overcomepriorart.
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`(D.I. 165 at 20). While the patent discloses analog-to-digital conversions implemented
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`“absolutely simultaneously or time-synchronously,” or with “minimal time offset,” during
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`prosecution synchronization was narrowed to modeswith “an elementof signaling at the
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`beginning or at an impending beginning of an analog-to-digital conversion.” D.I. 165 at 10-11,
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`21 (Resp. dtd. Feb. 1, 2002 at 4; Resp. dtd. July 30, 2002 at 4); see col.3 11.20-24; col.5 I1.13-19.
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`Describing the conversionsas “simultaneous” encompassesthis element.
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`VII. U.S. Patent No. 7,000,148
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`1. The term “peripheral units” is construed to mean "two or more on-chip units external
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`to the CPU that can be used for non-debugging functions." No party objects to the language “two
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`or more on-chip units external to the CPU.” (D.I. 171 at 33). The patent’s goal is to perform
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`debugging through peripheral units “that are provided in any case” and have functions other than
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`debugging, therefore saving space on the chip that otherwise would be dedicated to debugging.
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`Col.2 1.65-col.3 1.3; col.4,l1.21-26; col.6 11.28-41.
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`2. The patent claims items “connected to” each other differently from items “connected
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`to” each other “through” another item. Those two phrases must have different meanings. See
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`Exxon Chem. Patents, Inc. v. Lubrizol Corp., 64 F.3d 1553, 1557 (Fed. Cir. 1995). Infineon’s
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`proposal, thatall items connected to another item be “linked or capable of communicating,”fails
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`to distinguish from the two claim types, and is meaningless in the context of a microcontroller on
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`which nearly every componentis “linked” or “capable of communicating” with nearly every
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`other component. Accordingly:
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`a. The term “peripheral units connected to said first internal bus” is construed to
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`mean “peripheral units interfacing directly with thefirst internal bus.”
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`b. The term "being transmitted through said second internal busandatlease [sic]
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`one of said peripheral units connected to said second internal bus" is construed to
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`mean “being transmitted through the secondinternal bus andatleast one of the
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`peripheral units interfacing directly with the second internal bus.”
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`c. The term “saidintelligent system is connected to said second internal bus”is
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`construed to mean “the intelligent system interfaces directly with the secondinternal
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`bus.”
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`d. The term “peripheral units connectedto said first internal bus and said CPU
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`through said first internal bus" is construed to mean “peripheral units interfacing
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`directly with the first internal bus and interfacing with the CPU via thefirst internal
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`bus.”
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`e. The term "said debug resources and said peripheral units .
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`.
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`. being connected to
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`one anotherthrough said secondinternal bus" is construed to mean “the debug
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`resources and peripheral units interface with one another via the secondinternal
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`TreheGeataaELRaTETETATEa
`SFAAeeeTSPRSPmA
`Pmarareenaen
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`minegril:egalSREenSEPREE
`eers
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`seitpnritenhAap
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`bus.”
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`VIII. U.S. Patent No. 5,493,534
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`1. The term "power conversion meansto generate voltage levels necessary for clearing
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`the electrically programmable and erasable read only memory cells and writing therein"is
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`construed as a meansplus function term, with the function being “to generate voltage levels
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`necessary for clearing the electrically programmable and erasable read only memory cells and
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`writing therein,” and the structure being “charge pump and Y-select transistors and equivalents.”
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`Theparties agree that the structure for this claim term is at least a charge pumpand Y-select
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`transistors. The patent discloses a generic charge pumpas the structure, with a preferred
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`embodimentindicated in Figs. 1la and 11b. Col.1 11.62-67;col. 4 II.16-18; col.4 1.67 - col.5 1.1.
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`Infineon’s additional proposed structure (col.7 11.13-30) is unnecessary to the claimed voltage
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`level generation function.
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`2. The term "charge pump meansfor converting the low voltage supply to a voltage level
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`which programsanderases theelectrically programmable and erasable read only memory
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`transistors" is construed as “a charge pump.” This recognized, sufficient structure rebuts the
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`presumptionthat this claim is a means-plus-function claim. See Allen Eng’g v. Bartell Indus.,
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`299 F.3d 1336, 1347-48 (Fed.Cir. 2002).
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`3, The term “flash transistor array” does not require construction.
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`IX. U.S. Patent No. 5,606,532
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`1. The term "erasable and programmable sub-page sectors" is construed to mean "block of
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`memory cells less than one memory pagethat can be individually selected for erasing and
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`programming." This term does not have a plain and ordinary meaning. Theintrinsic evidence
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`indicates that the sub-page sectors can beerasedselectively, i.e. individually, as well as
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`collectively. ‘532 Patent at [57]; col.3 11.1-6.
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`2. The term “write cache” is construed to mean "single buffer connected to the main
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`memory core for temporarily storing data bytes, not parity bits." During prosecution, the
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`patentee disavowedstoring parity information in the write cache. D.I. 163 at
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`IFKATML0002091-93 (Resp. dtd. July 1, 1996). The patentee also disavowed having more than
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`one write cache.
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`/d. at IFXKATML0002090-92. Finally, the patentee indicated that the write
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`cache communicates directly with the main memory.
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`/d. at IFKATML0002092; 2089-90; 2078-
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`79. This intrinsic evidence is more useful andreliable than Atmel’s proffered extrinsic expert
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`interpretation of this prosecution history. See Phillips v. AWH Corp., 415 F.3d 1303, 1317-18
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`(Fed. Cir. 2005) (“[E]xpert reports and testimony [are] generated at the time of and for the
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`purposeoflitigation and thus can suffer from biasthat is not presentin intrinsic evidence.”).
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`AcaraSaayRRtnerRPSaemeTaar
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`earnSer
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`oneRTatarEarpactneMerebeeannaAenRHgeyAPEeARRARRREEoF
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`3. The term "a data bus for accessing a data word section of a memory unit" is construed
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`to mean "set of conductors for carrying only the data word section of a memory unit separate
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`from the parity bus," and the term "a parity bus for accessing a parity bit section of a memory
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`unit" is construed to mean “set of conductors for carrying only the parity bit section of a memory
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`unit separate from the data bus.” The data bus andparity bus are claimed as separate elements,
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`and the specification indicates two separate routes. Col.10 I1.52-55; col.11 11.29-31; col.8 11.52-
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`55. As explained supra, the patentee disavowed transmitting parity bits through the write cache,
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`necessitating separate parity and data routes and busses.
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`X. U.S. Patent No. 5,732,017
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`
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`1. The parties informed the Court that they were working towardastipulated
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`construction for the term “address decoding and select means connectedto said addresslines to
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`receive address signals therefrom for accessing a memory location in a selected one ofsaid
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`memory arrays, said address decoding and select means including a shared row decoderthatis
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`commonto both memory arrays for accessing in said selected memory array a word line
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`corresponding to said addresssignals." (D.I. 172 at 84). The Court will not construe this term
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`unlessit is notified that the parties could not reach agreement.
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`2. The terms "control means responsive to input control signals for selecting one of said
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`memory arrays and selecting a read or write operation for said selected memory array" / "control
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`means responsive to input control signals for controlling operation of at least said first and
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`second column decode andselect circuitry and said row address latch circuit to carry out a
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`selected read or write operation in a selected memory array" are construed as meansplusfunction
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`terms, with the functions being “selecting one of said memory arrays and selecting a read or write
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`encner
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`
`HRTFTETHTTRRReeteneneAngerapanemiaHTAPpAin:
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`tneianrereae
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`operation for said selected memory array / controlling operation of at least said first and second
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`column decode andselect circuitry and said row addresslatch circuit to carry out a selected read
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`or write operation in a selected memory array,” and the structure being “controllogic circuitry
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`and equivalents.” See col.3 11.5-25; col.3 1.53-col.6 1.3; Figs. 1, 2A, 2B. This adoption of
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`Atmel’s proposed construction is without prejudice to Infineon’s ability to argue the claims as
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`construed are indefinite, with an expert witness who can aid the Court in understanding, inter
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`alia, the claimed functions and whatoneof ordinary skill would require to implement them.
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`XI. U.S. Patent No. 5,822,245
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`1. The term “flash memory array” does not require construction.
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`acetTSrmemneTESAahaneSRARRRPEtRiSMAPneRSSTheaEDYeSTPoyererHTRRROGETEtma
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`2. The term "input/output conductors" is construed to mean “electrical conductors
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`between two components for two-way communication of data.” The patent discloses “I/O”lines
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`with two-way arrows,as distinguished from the claimed “output conductor” with a one-way
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`arrow. Figs. 1, 2A; cls. 3, 4, 6, 7, 13, 14, 21, 22, 29, 30. The decision to claim both a one-way
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`output conductor and input/output conductors creates a presumption of a difference in meaning
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`and scope. See Tandon Corp. v. U.S. Int’l Trade Comm’n, 831 F.2d 1017, 1023 (Fed. Cir. 1987).
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`The embodiment Atmel argues is excluded by this construction actually shows conductors D1-
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`D8 as two-way conductors capable of being in a one-way write mode. Fig.2A;col.6 11.56-65.
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`3. The terms "while saidfirst data is being written to said [flash memory
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`array/non-volatile memory array]" and "while said first data is being transferred [outof/into] said
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`flash memory buffer" are construed to mean "during a write operation concurrently while said
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`first data is being written to said [flash memory array/non-volatile memory array]." The parties
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`10
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`agree that the write need notstart or stop simultaneously, but rather need only overlap to some
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`extent. (D.I. 172 at 103).
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`XII. U.S, Patent No. 6,879,518
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`1. The term “security bit” is construed to mean “a single memory bit located within a
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`security row of the non-volatile memory.” The parties agreed upon these limitations. The
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`Summary ofthe Invention providesthat “in one exemplary embodiment,” the security row
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`elements can be programmedto an unlocked or locked state. Col.2 11.9-16. This cannot serve to
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`additionally limit the term as Atmel proposes.
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`2. The terms “lockbit / lock bit” are construed to mean "memory bits or elements within
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`the non-volatile memory that enable and disable external access to the non-volatile memory”in
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`accordance with the patent’s specific definition. See col.1 11.26-31. Infineon’s proposed
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`limitation improperly relies on col.2 11.5-8, which describesuse of the lockbits, but does not
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`define them.
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`XIII. U.S. Patent No. 7,428,610
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`1. The term “write command”doesnot require construction.
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`2. The term “address” is construed to mean “a series of usually alphanumeric characters
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`that specifies the storage location ofparticular information,” whichis the dictionary definition
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`Atmel proffered and Infineon adopted.
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`(D.I. 153 at 99-100).
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`1
`Entered this A day ofDecember, 2012.
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` United States Djstrict Judge
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