United States Patent [19J
`Fallisgaard et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US005952890A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,952,890
`Sep.14,1999
`
`[54] CRYSTAL OSCILLATOR PROGRAMMABLE
`WITH FREQUENCY-DEFINING
`PARAMETERS
`
`[75]
`
`Inventors: John W. Fallisgaard, Seattle, Wash.;
`Eugene S. Trefethan, Fort Myers, Fla.
`
`[73] Assignees: Fox Enterprises, Inc., Fort Myers, Fla.;
`Jet City Electronics, Seattle, Wash.
`
`FOREIGN PATENT DOCUMENTS
`
`0 203 756
`0 437 634 A1
`0 053 561 A2
`0 637 876
`2-291161
`3-297223
`2 282 500
`
`12/1986
`7/1991
`6/1992
`2/1995
`11/1990
`12/1991
`4/1995
`
`European Pat. Off ..
`European Pat. Off ..
`European Pat. Off ..
`European Pat. Off ..
`Japan .
`Japan .
`United Kingdom .
`
`OTHER PUBLICATIONS
`
`[21] Appl. No.: 08/795,978
`
`[22] Filed:
`
`Feb. 5, 1997
`
`[51]
`
`Int. Cl.6
`
`................................ H03B 5/32; H03L 7/06;
`H03L 7/18
`[52] U.S. Cl. .............................. 331/18; 331/16; 331/158;
`331!179
`[58] Field of Search .................................. 331!16, 18, 25,
`331!116 R, 116 FE, 158, 179; 327/105,
`156-159; 375/376; 455/260
`
`[56]
`
`References Cited
`
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`5,323,125
`5,349,544
`5,446,420
`5,451,912
`
`4/1977 Hoffmann eta!. ................ 331/36 C X
`3/1982 Wulfsberg eta!. ................... 331!18 X
`8/1982 Uetrecht ................................... 84/1.24
`7/1984 Lane ........................................ 331!135
`8/1984 Monticelli ........................... 331!113 R
`12/1984 McCallister eta!. ................... 364/607
`5/1986 Saulson et a!. .
`8/1987 Talbot ..................................... 331!1 A
`5/1989 Coster ... ... ... ... .... ... ... ... ... ... .... ... ... 331!2
`1!1991 Geier et a!. ............................. 364/401
`10/1991 Schemmel ............................. 331/36 C
`11/1991 Vale et a!. ................................. 331/60
`8/1992 Lada, Jr. et a!. ... ... ... .... ... ... ... ... . 331!14
`9/1992 Williams et a!. ......................... 331!75
`6/1993 Protheroe ................................ 364/412
`11/1993 Hashimoto et a!. ...................... 331!45
`4/1994 Bitting ...................................... 331!45
`6/1994 Hiben et a!. ............................ 332/100
`9/1994 Wright eta!. ........................... 364/600
`8/1995 Westwick ................................ 331!179
`9/1995 Torode .. ... ... ... .... ... ... ... ... ... .... .. 331/108
`
`D. Soderquist, "Digitally programmed oscillator is suitable
`for ,uP control", Electronic Design 13, Jun. 21, 1997, pp.
`102-104.
`A. Foard, "Voltage controlled oscillator," Radio and Elec(cid:173)
`tronics Constructor, vol. 28, No. 10, pp. 590-595, May
`1975.
`T.G. Giles, "A universal frequency synthesizer IC," Philips
`Telecommunication Review, vol. 37, No. 3, Aug. 1979, pp.
`177-181.
`Cypress Semiconductor Marketing Brochure "Graphics Fre(cid:173)
`quency Synthesizers" Published Nov., 1993, pp. 5-7, a
`publication of Cypress Semiconductor, San Jose, California.
`
`(List continued on next page.)
`
`Primary Examiner-David Mis
`Attorney, Agent, or Firm-Finnegan, Henderson, Farabow,
`Garrett & Dunner, L.L.P.
`
`[57]
`
`ABSTRACT
`
`A programmable crystal oscillator is provided having a
`memory for storing frequency-defining parameters.
`Typically, one of these parameters is used to program an
`adjustable capacitive load circuit coupled to a crystal to
`thereby adjust the crystal source frequency. Additional
`parameters are used to program the output frequency of a
`phase locked loop circuit coupled to receive the adjusted
`source frequency. A further parameter can also be used to
`divide the output frequency of the phase locked loop circuit
`to supply a specified output frequency. The oscillators can be
`manufactured as generic programmable crystal oscillators
`without regard for output frequency and then quickly pro(cid:173)
`grammed to produce customer-specified output frequencies
`with a high degree of accuracy.
`
`(List continued on next page.)
`
`33 Claims, 4 Drawing Sheets
`
`VSS VDD
`
`AMD EX1014
`U.S. Patent No. 6,895,519
`
`0001
`
`

`

`5,952,890
`Page 2
`
`U.S. PATENT DOCUMENTS
`
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`5,465,076
`5,467,373
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`5,563,554
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`5,579,231
`5,636,346
`5,668,506
`
`10/1995 Westwick .......................... 331!116 FE
`11/1995 Yamauchi et a!. ...................... 331!179
`11/1995 Ketterling ........................... 332/128 X
`8/1996 Watanabe eta!. ................ 331/36 C X
`10/1996 Mizuno ..................................... 331!57
`10/1996 Eberhardt et a!. .
`11/1996 Sudou et a!. .
`6/1997 Saxe ........................................ 395/201
`9/1997 Watanabe eta!. ............ 331!116 FE X
`
`01HER PUBLICATIONS
`
`IC Designs, "Satellite Oscillator," Model No. ICD2031A
`Preliminary Data Sheet May 1991.
`IC Designs, "Programmable Clock Oscillator," Model No.
`ICD2053A Programmable Products.
`IC Designs, "Frequency Multiplier," Model No. ICD2032
`Preliminary Data Sheet, May 1991.
`"ICD6233 Characterization Data," & "Dutycycle Data",
`1994; 32 pages 1994.
`IC Designs, "Dual Programming Clock Oscillator," Model
`No. ICD2051, May 1991.
`MF Electronics Corp., "Phase Locked VCXO 10 MHz to
`32.768 MHz," 1994., 1 page.
`MF Electronics Corp., "20 to 200 MHz Programmable
`ECL," 1994, pp. 18-20.
`M-Tron "MV Series VCXO Oscillators," 1994, 1 page.
`M-Tron, "MV Series VCXO Oscillators," 1995, 1 page.
`Vectron Labs.,
`"Sonet Clock Recovery Module
`SCRM-622," Nov. 94., 4 pages.
`Wenzel Associates Inc., "Custom Oscillator Configura(cid:173)
`tions." 1 page.
`Connor-Winfield Corp., "SM PECL PLL Frequency Multi(cid:173)
`plier," 1995., 2 pages.
`Epson, "Programmable Multi-Output Crystal Oscillator
`MG-5010," Mar. 7, 1993., 3 pages.
`
`M-Tron, "MT1135 Series Dual Baud Rate Generators,"
`1987., 2 pages.
`Hybrids International, Ltd., "Voltage Controlled Crystal
`Oscillators," pp. VCX-1 to VCX-3, 1995.
`National Semiconductor, "IMX2306/2316/2326 PLLatinum
`Low Power Frequency Synthesizer for RF Personal Com(cid:173)
`munications," Jan. 1998., 18 pages.
`Hybrids International, Ltd., "Frequency Products," Sep. 23,
`1994, 1 page.
`MF Electronics Corp., "Voltage Controlled Oscillators 1
`MHz to 175 MHz," 1994, p. 9.
`Hybrids International, Ltd., "Product Summary," Aug.
`1993., 1 page.
`Hybrids International, Ltd., "Crystal Oscillators: Voltage
`Controlled," pp. VC-1 to VC-3, Mar. 1993.
`Cypress-Semiconductor Corporation, "One-Time Program(cid:173)
`mable Clock-Oscillator ICD6233," Apr. 1995, 3 pages.
`Fox Electronics, "F3000/HCMOS/TTL Tri-State Enable/
`Disable Oscillator," 1992, 2 pages.
`Fox Electronics, "F6053NTri-State HCMOS Program(cid:173)
`mable Clock Oscillator," 1993, 4 pages.
`Fox Electronics, "F6151/Tri-State Dual Programmable
`Clock Oscillator," 1993, 4 pages.
`Fox Electronics, "Programmable Crystal Oscillators for R.F.
`Applications," 1993, 2 pages.
`Fox Electronics, Frequency Control Products Catalog,
`1995-96; vol. XVI, pp. 1-72.
`W. Ooms, "Improved Frequency Synthesizer," Motorola
`Technical Disclosure Bulletin, vol. 6, No. 1, pp. 4-6, Oct. 1,
`1986, Schaumbourg, Illinois, USA
`E. Mielke, "Programmierbarer 50-MHz-Muttertaktimpul(cid:173)
`segenerator," Radio Fernsehen Elektronik, vol. 39, No. 9,
`pp.
`560--563,
`Jan.
`1,
`1990, Berlin, Germany.
`
`0002
`
`

`

`U.S. Patent
`U.S. Patent
`
`Sep.14,1999
`Sep. 14, 1999
`
`Sheet 1 of 4
`Sheet 1 of 4
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`5,952,890
`5,952,890
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`

`

`U.S. Patent
`U.S. Patent
`
`Sep.14,1999
`Sep. 14, 1999
`
`Sheet 3 of 4
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`U.S. Patent
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`Sep.14,1999
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`Sheet 4 of 4
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`

`5,952,890
`
`1
`CRYSTAL OSCILLATOR PROGRAMMABLE
`WITH FREQUENCY-DEFINING
`PARAMETERS
`
`BACKGROUND OF THE INVENTION
`
`5
`
`2
`Advantages of the invention will be set forth in part in the
`description which follows, and in part will be obvious from
`the description, or may be learned by practice of the inven(cid:173)
`tion. Additionally, advantages of the invention will be real-
`ized and attained by means of the elements and combina(cid:173)
`tions particularly pointed out in the appended claims.
`It is to be understood that both the foregoing general
`description and the following detailed description are exem(cid:173)
`plary and explanatory only and are not restrictive of the
`10 invention, as claimed.
`The accompanying drawings, which are incorporated in
`and constitute a part of this specification, illustrate embodi(cid:173)
`ments of the invention and together with the description,
`serve to explain the principles of the invention.
`
`15
`
`The present invention relates to programmable crystal
`oscillators. In particular, the present invention is directed
`toward a programmable crystal oscillator having an adjust(cid:173)
`able capacitive load circuit coupled to the crystal.
`Crystal oscillators are widely used to generate timing
`signals for electronic hardware, such as computers,
`instrumentation, and telecommunications equipment. Crys(cid:173)
`tal oscillators typically include a quartz crystal and an
`oscillator circuit, which electrically excites the crystal so as
`to generate an oscillating signal at a resonant frequency
`determined by physical characteristics of the crystal. The
`oscillator circuit or a separate output circuit (buffer) wave(cid:173)
`shapes the oscillating signal into a timing pulse train accept(cid:173)
`able to the electronic hardware.
`Timing frequencies are specified by the electronic hard(cid:173)
`ware manufacturers and thus vary over a wide frequency
`range. However, a crystal's resonant frequency is deter(cid:173)
`mined by its physical characteristics, e.g., size, shape, crys(cid:173)
`talline structure, etc. Trimming the crystal's resonant fre- 25
`quency can be achieved by selective metal plating the crystal
`faces. Consequently, the manufacture of crystal oscillators is
`an involved process that is both time consuming and costly.
`Thus, suppliers of crystal oscillators stock large numbers of
`crystal oscillators manufactured to a variety of standard 30
`output frequencies. However, if a customer requires a cus(cid:173)
`tom frequency, a manufacturer generally must "start from
`scratch" by dicing an ingot into crystal wafers of specific
`dimensions and then subjecting the crystal wafers to numer(cid:173)
`ous processing steps (lapping, etching, and plating), all 35
`designed to achieve the custom output frequency. Custom
`crystal oscillators come at premium prices and require long
`manufacturing leadtimes (months).
`Since virtually all crystals are capable of oscillating,
`manufacturing yield is quite high. However, if the crystal's 40
`resonant frequency cannot be trimmed to meet one custom(cid:173)
`er's frequency specification, the crystals are typically inven(cid:173)
`toried in the hope that they can be used to meet another
`customer's frequency specification. In the case of custom
`crystal oscillators, it is not uncommon for manufacturers to 45
`produce an oversupply of custom crystals to ensure a
`sufficient volume of crystals capable of meeting customer
`requirements in terms of both output frequency and quantity.
`The excess crystal oscillators are then placed in inventory.
`Maintaining large crystal inventories represents a significant so
`manufacturing expense.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a plan view illustrating an exemplary package
`configuration for a programmable crystal oscillator package
`20 in accordance with an embodiment of the present invention;
`FIG. 2 is a block diagram of a programmable crystal
`oscillator in accordance with an embodiment of the present
`invention;
`FIG. 3 is a detailed circuit schematic of a programmable
`capacitive load circuit included in the programmable crystal
`oscillator of FIG. 2; and
`FIG. 4 is a schematic diagram of a phase locked loop
`circuit included in the programmable crystal oscillator of
`FIG. 2.
`
`DETAILED DESCRIPTION
`
`Reference will now be made in detail to the presently
`preferred embodiment of the invention, an example of which
`is illustrated in the accompanying drawings. Wherever
`possible, the same reference numbers will be used through-
`out the drawings to refer to the same or like parts.
`Consistent with the present invention, a programmable
`crystal oscillator is provided with a memory for storing
`output frequency-defining parameters. Typically, one of
`these parameters is used to program an adjustable capacitive
`load circuit coupled to the crystal, thereby to adjust the
`source (resonant) frequency of the crystal. Additional
`parameters are used to program the output frequency of a
`phase-locked loop circuit coupled to receive the adjusted
`source frequency. A further parameter can also be used to
`divide the frequency output of the phase-locked loop circuit
`to thereby supply the desired output frequency. As a result,
`by storing appropriate parameters as program data in the
`memory and programming in accordance with these
`parameters, nearly any crystal capable of oscillation may be
`utilized in a crystal oscillator in accordance with the present
`invention, which can then be programmed to generate a wide
`range of specified output frequencies. Moreover, such fre-
`ss quency programming can be performed expeditiously and at
`little expense.
`An embodiment of a programmable crystal oscillator, in
`accordance with the present invention, is illustrated in FIG.
`1. This oscillator 20 may be produced in a variety of industry
`standard sizes and in two basic package configurations, pin
`through and surface mounted (SMD), depending upon the
`manner in which the oscillator is to be mounted in its
`particular application. The illustrated embodiment has six
`input/output (110) terminals, consisting of a Signature clock
`terminal 21, a dedicated Program input terminal 22, a
`ground (VSS) terminal23, a supply voltage (VDD) terminal
`24, a Signature output terminal25, and a clock signal output
`
`SUMMARY OF THE INVENTION
`Systems and methods consistent with this invention
`resolve certain disadvantages of conventional approaches by
`providing a timing circuit comprising a crystal for generat(cid:173)
`ing a source frequency, an oscillator circuit coupled to the
`crystal, and a programmable load circuit coupled to the
`crystal. A frequency multiplier circuit is coupled to the
`oscillator circuit to receive the adjusted source frequency. 60
`Further, a programming circuit is included to supply first
`programming data to the programmable load circuit to adjust
`the crystal source frequency and second programming data
`to the frequency multiplier circuit. The frequency multiplier
`circuit, in turn, supplies an output frequency equal to a 65
`product of the adjusted source frequency and a multiplica(cid:173)
`tion factor designated by the second programming data.
`
`0007
`
`

`

`5,952,890
`
`20
`
`3
`(Fout)/programming clock pulse input (CLK;n) terminal 26.
`As will be described in detail below, programming data is
`entered via terminal22 at a timing controlled by clock pulses
`(CLK;J applied to terminal 26.
`When programmable crystal oscillator 20 is programmed 5
`by the programming data, it produces a clock signal output
`(Fout) on terminal26 of a programmed frequency conform(cid:173)
`ing to a customer specified target frequency anywhere
`within a wide range, e.g., 380 KHz to 175 MHz, with an
`accuracy of ±100 ppm (parts per million) or better. In terms 10
`of percentage, 100 ppm is equal to ±0.01% of the target
`frequency. In accordance with a feature of the present
`invention, crystal oscillator 20 includes a programmable
`read only memory (PROM) 50, (FIG. 2), into which pro(cid:173)
`gramming data in the form of customer data may be entered 15
`via Program terminal 22, under timing control imposed by
`clock pulses (CLK;J applied to terminal 26 by the manu(cid:173)
`facturer at the time the oscillator is programmed. Thereafter,
`the customer data may be read out on terminal 25 by
`applying clock pulses to terminal 21. If this Signature data
`feature is omitted, the crystal oscillator package configura(cid:173)
`tion illustrated in FIG. 1 may be reduced to four terminals.
`Programmable crystal oscillator 20, illustrated in greater
`detail by the block diagram of FIG. 2, includes a crystal
`blank 30 electrically connected between pads 31 and 32 on 25
`an integrated circuit chip for excitation by an oscillator
`circuit 34 and thus to generate a source oscillating signal.
`This oscillator circuit includes an arrangement of resistor,
`capacitor, and inverter components well known in the crystal
`oscillator art and, thus, need not be described here. The 30
`frequency of the source oscillating signal, appearing at the
`output of oscillator circuit 34 as a reference frequency signal
`F ref' is largely determined by the physical characteristics of
`the crystal wafer.
`In accordance with a feature of the present invention,
`programmable crystal oscillator 20 accommodates a wide
`range of source frequencies, e.g., 5.6396 MHz to 27.3010
`MHz. That is, the source frequency may vary from crystal to
`crystal within this range without jeopardizing the ability of
`crystal oscillator 20 to be programmed to output clock
`signals at any target frequency specified by a customer
`within, for example, a 380 KHz-175 MHz range, with the
`industry standard accuracy of at least 100 ppm. In fact, the
`diverse crystal source frequencies need not be known in
`advance of programming.
`Still referring to FIG. 2, oscillator circuit 34 outputs the
`reference frequency F ref' which is applied to a frequency
`multiplier 36, illustrated in greater detail in FIG. 4. The
`frequency multiplier outputs clock signals at a frequency F pll
`to a frequency divider 38, which divides the frequency FP11
`by a programmable parameter N, received from program(cid:173)
`ming network 42, to produce clock signals F out of a pro(cid:173)
`grammed frequency conforming to customer specification.
`The F out and F ref signals are applied as separate inputs to a
`multiplexor 40. Under the control of program control logic
`in programming network 42, imposed over line 43, multi(cid:173)
`plexor 40 outputs either clock signals F out or F ref through an
`output buffer 44 and onto terminal 26.
`In accordance with another feature of the present
`invention, crystal oscillator 20 further includes a pair of load
`circuits 46 and 48 that may be programmed, if necessary, to
`adjust the capacitive load on crystal 30 and, in turn, pull the
`crystal source frequency into a range of frequencies condu(cid:173)
`cive to optimal programming of crystal oscillator 20 to
`achieve not only the output frequency accuracy specified by
`a customer, but also a low phase locked loop frequency
`conducive to stable operation of frequency multiplier 36.
`
`4
`Load circuits 46 and 48 are illustrated in greater detail in
`FIG. 3. Load circuits 46 and 48 can include, for example,
`pluralities of capacitors 771 to 77 n and 871 to 87 m respec(cid:173)
`tively. Capacitors 771 to 77 n are respectively connected
`between ground and source electrodes of first switching
`elements or transistors 78 1 to 78n, and capacitors 871 to 87 n
`are respectively connected between ground and source elec(cid:173)
`trodes of second switching elements or transistors 88 1 to
`88n. As further shown in FIG. 3, the gate of each of
`transistors 781 to 78n is connected by a corresponding one of
`output leads 76 1 to 76n from programming network 42,
`indicated collectively at 76 in FIG. 2. The drain electrodes
`of these transistors are connected in common to a source
`frequency input line 79 connecting crystal pad 31 to oscil(cid:173)
`lator circuit 34. In a similar fashion, the gate electrodes are
`respectively connected to output leads 861 to 86n from
`programming network 42, (collectively indicated at 86 in
`FIG. 2), and the drain electrodes of transistors 88 1 to 88n are
`connected in common to source frequency input line 89
`connecting crystal pad 32 to oscillator circuit 34.
`Additionally, fixed capacitors 75 and 85 (each having a
`capacitance of, e.g., 35 pf) are provided as a nominal
`capacitance load for crystal blank 30.
`In response to a parameter stored in memory network 42,
`selected output lines 76 1 to 76n and 86 1 to 86n are driven
`high to activate or turn-on corresponding ones of transistors
`781 to 78n and 88 1 to 88n. As a result, those of capacitors 771
`to 77 n and 871 to 87 n associated with the activated transistors
`are coupled to one of source frequency input lines 79 and 89.
`Thus, the capacitive loading of crystal blank 30 can be set
`in accordance with the parameter stored in memory network
`42, and the crystal source frequency can therefore be
`"pulled" into a desired range, leaving gross output frequency
`adjustment to be accomplished by multiplier circuit 36. If no
`35 crystal frequency pulling is necessary, none of transistors
`781 to 78n and 881 to 88n is activated.
`Each of capacitors 771 to 77 n and 871 to 87 n may have a
`capacitance of, for example, 5 pf. Moreover, capacitors 771
`to 77 n and 871 to 87 n are symmetrically connected into
`40 source frequency input lines 79 and 89, respectively, such
`that for each one of capacitors 771 to 77 n connected to
`source frequency input line 79, a corresponding one of
`capacitors 871 to 87 n is connected to source frequency input
`line 89. Accordingly, pairs of capacitors 771 to 77n and 871
`45 to 87 n (one from each group of capacitors 771 to 77 n and 871
`to 87 n) are respectively connected to input lines 79 and 89,
`and the incremental change of capacitance associated with
`each pair of capacitors may be 2.5 pf. As noted previously,
`this capacitance loading adjustment is effective to pull the
`50 crystal source frequency up or down as required to adjust the
`reference clock signal frequency F ref to a value appropriate
`for optimal frequency programming of crystal oscillator 20.
`As seen in FIG. 4, frequency multiplier 36 includes a
`frequency divider 52 that divides the reference frequency
`55 F ref by a programmable parameter Q stored in programming
`network 42 and applies the resultant clock signal frequency
`to a phase detector 54 of a phase locked loop (PLL). The
`phase locked loop includes a charge pump 56, a loop filter
`60, and a voltage controlled oscillator 58 that produces the
`60 clock signal frequency FP11 going to frequency divider 38 in
`FIG. 2. This clock signal frequency FP11 is also fed back
`through a frequency divider 64 to a second input of phase
`detector 54. Divider 64 divides the FP11 frequency by a
`programmable parameter P also stored in programming
`65 network 42.
`During operation, parameters Q and P, further defined
`below, are supplied to program divider circuits 52 and 64,
`
`0008
`
`

`

`5,952,890
`
`5
`respectively, from programming network 42. Reference fre(cid:173)
`quency F ref is thus divided by the programmed parameter Q
`in divider circuit 52. As noted above, Frefcorresponds to the
`source frequency of crystal 30, and is therefore typically in
`a range of 5.64 MHz to 27.3 MHz. If Q is an integer within 5
`a range of 132 to 639, the quotient FreJQ, i.e., the output of
`divider 52, can be made to fall within the range of 32 KHz
`to 50 KHz, regardless of the crystal source frequency. The
`quotient F re/Q is the loop frequency of the phase locked
`loop circuit shown in FIG. 4.
`The loop frequency is supplied to phase comparator 54,
`along with the output of divider 64, which outputs a control
`signal typically at a frequency substantially equal to the
`difference between the output frequencies of dividers 52 and
`64. The control signal, in turn, is supplied to charge pump 56
`which outputs a DC signal proportional to the frequency of
`the control signal. The loop filter 60 is provided at the output
`of charge pump 56 in order to define the response of the
`phase-locked loop circuit.
`The DC signal is next supplied to voltage controlled
`oscillator (VCO) 58, which outputs clock signal FP11 of a
`frequency controlled by the potential of the DC signal.
`Clock signal F PLL is next fed back to one of the inputs of
`phase detector 64 via P divider 64. Accordingly, with this
`phase locked loop arrangement, F PLL is equal to the product
`of the loop frequency multiplied by programmable P, an
`integer in the range of 2048 to 4097, so that F PLL is within
`the range of 87.5 MHz to 175 MHz. Clock signal F PLL is
`also supplied to divider circuit 38 (see FIG. 2), where it is
`divided by any programmed one of the following integer
`parameters retrieved from programing network 42: 1, 2, 4,
`8, 16, 32, 64, 128 or 256, and then outputted as frequency
`F out through multiplexor 40 and output buffer 44.
`Phase detector 54, charge pump 56, loop filter 60 and
`VCO 58 are intended to represent a broad category of
`circuits utilized to phase lock two input signals, which are
`well known in the art and will not be described further.
`Generally, the output frequency F PLL and F ref satisfy the
`following equation:
`
`6
`GRAMMING CRYSTAL OSCILLATORS TO CUS(cid:173)
`TOMER SPECIFICATION, Ser. No. 08!795,980 filed
`concurrently herewith, the disclosure thereof being incor(cid:173)
`porated herein by reference, the P, Q, and N parameters
`alone may be insufficient to achieve an output frequency
`sufficiently close, e.g., within 100 parts per million (100
`ppm) of a specified target frequency. In which case, the
`crystal source frequency is pulled, as discussed above, to
`bring the resulting output frequency into the acceptable
`10 accuracy range.
`Thus, the programmable crystal oscillator in accordance
`with the present invention can be used to generate an output
`frequency based on a wide range of crystal source frequen(cid:173)
`cies. The output frequency is obtained by adjusting the
`15 source frequency with a programmable capacitive load, and
`operating the phase-locked loop circuit at a relatively low
`loop frequency. As a result, for any crystal having a source
`frequency within the relatively wide range of, e.g., 5.6396
`MHz to 27.3010 MHz, crystal oscillator output frequencies
`20 within 100 ppm or less of a specified target frequency can be
`achieved by simply storing appropriate P, Q, N and crystal
`pulling parameters in a PROM included in programming
`network 42. As pointed out in the cited copending
`application, crystal oscillators 20 may be manufactured as
`25 generic programmable crystal oscillators, without regard to
`customer-specified output frequencies and simply pro(cid:173)
`grammed in a matter of seconds to generate output frequen(cid:173)
`cies in accordance with customer specifications.
`Consequently, there is no need to manufacture the crystals to
`30 a plurality of standard frequencies, thus simplifying,
`expediting, and cost-reducing the manufacturing process.
`Lead times from customer purchase order to product delivery
`may thus be dramatically reduced.
`While the present invention has been described in the
`35 context of using a standard microprocessor-type crystal
`blank that oscillates in the range of 5.6396 MHz to 27.3010
`MHz, as noted above, it will be understood that the present
`invention may be achieved using an industry standard watch
`crystal mass produced to oscillate at 32.768 KHz. In this
`40 case, the desired low phase-locked loop frequency may be
`achieved without the need for frequency divider 52 in
`frequency multiplier 36 of FIG. 4. Crystal blank 30 would
`then, in effect, be coupled in direct drive relation with the
`phase-locked loop circuit. Since watch crystals, by virtue of
`45 mass production, are significantly less expensive than
`microprocessor-type crystals, further economies in the pro(cid:173)
`duction of programmable crystal oscillators in accordance
`with the present invention may be achieved.
`It will be apparent to those skilled in the art that various
`50 modifications and variations can be made in the program(cid:173)
`mable crystal oscillator of the present invention and in
`construction of this programmable crystal oscillator without
`departing from the scope or spirit of the invention.
`Other embodiments of the invention will be apparent to
`55 those skilled in the art from consideration of the specifica(cid:173)
`tion and practice of the invention disclosed herein. It is
`intended that the specification and examples be considered
`as exemplary only, with a true scope and spirit of the
`invention being indicated by the following claims.
`What is claimed is:
`1. A timing circuit comprising:
`a programmable load circuit coupled to a crystal that
`generates a source frequency;
`an oscillator circuit coupled to receive said source fre(cid:173)
`quency;
`a frequency multiplier circuit coupled to said oscillator
`circuit for receiving said source frequency; and
`
`F PLL ~F,e)P/Q).
`
`Thus, F PLL is a multiple of the loop frequency. Accordingly,
`for relatively low loop frequencies, F PLL can be finely
`adjusted in small increments of the loop frequency. If the
`loop frequency is too low, the phase locked loop can become
`unstable, resulting in jitter. Thus, it has been determined that
`an optimal loop frequency range is 32 KHz to 50 KHz, with
`a preferred range of 42.395 KHz to 43.059 KHz. Loop
`frequencies above this range, but less than 200 KHz, can
`also be used with output frequency resolution better than
`that obtainable by conventional crystal oscillator PLLs.
`Conventional crystal oscillator phase locked loops used in
`digital circuit timing applications, however, operate at a
`significantly higher loop frequency, i.e., greater than 200
`KHz. At these frequencies, such conventional crystal oscil(cid:173)
`lators cannot achieve the same high frequency resolution
`attainable with the present invention. Typically, polysilicon
`capacitors, for example, and other low noise components,
`are incorporated into the phase-locked loop typically used in 60
`the present invention so that it can operate with a loop
`frequency within the preferred range of 42.395 KHz to
`43.059 KHz with relatively little jitter.
`As discussed in greater detail in applicants' related patent
`application, entitled WORLDWIDE MARKETING 65
`LOGISTICS NETWORK INCLUDING STRATEGI(cid:173)
`CALLY LOCATED CENTERS FOR FREQUENCY PRO-
`
`0009
`
`

`

`5,952,890
`
`7
`a programming circuit configured to supply stored first
`programming data to said programmable load circuit to
`adjust said source frequency and stored second pro(cid:173)
`gramming data to said frequency multiplier circuit,
`such that said frequency multiplier circuit supplies an 5
`output frequency which is substantially equal to a
`product of said adjusted