000000808080000
`
`United States Patent
`US 6,681,336 B1
`(10) Patent No.:
`(12)
`Nakazato et al.
`(45) Date of Patent:
`Jan. 20, 2004
`
`
`5,768,613 A *
`6/1998 Asghar... FI2/35
`
`5,835,885 A * 11/1998 Lin...
`wees 702/99
`5,845,111 A * 12/1998 Linet al. woe 713/501
`6,044,417 A *
`3/2000 Muljonoet al,
`.............. 710/52
`6,442,700 Bl
`*
`8/2002 Cooper ....cccecee 713/320
`FOREIGN PATENT DOCUMENTS
`-
`10-124200
`5/1998
`11-259162
`9/1999
`
`2001117663 A *
`
`4/2001
`
`seeeesssesee GO6E/1/04
`
`(54) SYSTEM AND METHOD FOR
`IMPLEMENTING A USER SPECIFIED
`PROCESSING SPEED IN A COMPUTER
`SYSTEM AND FOR OVERRIDING THE
`USER SPECIFIED PROCESSING SPEED
`DURING A STARTUP AND SHUTDOWN
`PROCESS
`
`h
`
`‘alena
`
`D).
`
`(5) Tnventor: APavamlMoetaOmetey y
`
`IP
`JP
`
`IP
`
`(73) Assignee: Kabushiki Kaisha Toshiba, Kawasaki
`(JP)
`
`(*) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 586 days.
`
`(21) Appl. No.: 09/595,931
`
`(22)
`
`Filed:
`
`Jun. 16, 2000
`
`OTHER PUBLICATIONS
`.
`.
`;
`.
`Intel, Mobile Pentium III Processor in BGA2 and Mir-
`co-PGA2 Packages, 2000.*
`*etted Ky meatus
`y
`Primary Examiner—Dennis M. Butler
`Assistant Examiner—Mark Connolly
`(74) Altorney, Agent, or Firm—Finnegan, Henderson,
`Farabow, Garrett & Dunner, L.L.P.
`_
`(57)
`ABSTRACT
`(30)
`Foreign Application Priority Data
`
`
`Tun. 18,1999|@P) vem The CPU operates at the highest speed in start processing of
`agains
`ant
`stat eeeanb fearsestircsblaeeresaitie
`RO ae
`an operating system. When a power-saving driver receives a
`Oct..21,.1999
`QP) osceis 11-299700
`start completion message from the operating system,
`the
`61) teCl pcosBOSE 132
`power-saving driver waits for a predetermined period until
`eens. 713/322: 713/1
`(52) USM scscscceessrcaisics
`user operation to a computer systemis enabled, and then sets
`
`(58) Field of Search .......sscsseseseseseeeeeeeeese 713/300, 320
`the processing speed of the CPU to a user-designated speed.
`713/322. 500, 501 "502
`;
`When the power-saving driver receives from the OS an OS
`aaa termination start message representing the start of shutdown
`processing, the power-saving driver cancels setting of the
`user-designated speed, and returns the CPU to, e.g., the
`highest speed, Hence, start processing/shutdown processing
`can be executedat a high speed regardless of the set value
`of the user-designated speed.
`
`(56)
`
`References Cited
`
`;
`U.S. PATENT DOCUMENTS
`5,167,024 A * 11/1992 Smith et al
`cosscesescsseee 713/322
`8/1996 Bland et al. w......0..... 713/501
`5,546,568 A *
`5/1998 Holzhammer etal.
`5,754,869 A
`5,768,602 A
`6/1998 Dhuey
`
`21 Claims, 16 Drawing Sheets
`
`USER-DES | GNATED
`SPEED IS SET
`
`SETTING OF USER-DES|GNATED
`SPEED IS CANCELED
`
`CPU SPEED
`
`HIGHEST SPEED
`
`USER-DESIGNATED SPEED
`
`| HIGHEST SPEED
`
`HIGHEST SPEED
`
`LOW SPEED
`
`
`
`i
`'
`OS START
`OS TERMINATION
`=:
`COMPLETION
`POWER OFF
`START MESSAGE
`i
`MESSAGE
`POWER ON
`SS
`OS START
`‘
`OS SHUTDOWN
`
` sated aniaPROCESS I NG PROCESS | NGi————eri ert: USER OPERABLE PERIOD
`
`
`
`
`
`START
`PROCESS I NG
`SUCH AS APL
`
`TIME
`
`0001
`0001
`
`AMD EX1008
`AMD EX1008
`U.S. Patent No. 6,895,519
`U.S. Patent No. 6,895,519
`
`

`

`US 6,681,336 BL
`
`eu3H|eloY|8Aldans}{AuaLiva}~zai|Wou-sola|7)
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`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 1 of 16
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`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 2 of 16
`
`US 6,681,336 B1
`
`CPU SPEED
`
`© HIGHEST SPEED
`
`© HIGH SPEED
`
`© MIDDLE SPEED
`
`CPU SPEED SETTING WINDOW
`
`FIG. 4A
`
`@ LOW SPEED
`
`© LOWEST SPEED
`
`DESIGNATED:
`
`0003
`0003
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 3 of 16
`
`US 6,681,336 BL
`
`
`
`
`
`d33dSLSSHDIH|daadSdaLV¥N91S3q-Y3snQ3adSLSSHOIH
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`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 4 of 16
`
`US 6,681,336 BI
`
`START OS
`
`All
`
`
`
`0S
`
`POWER-SAVING DRIVER
`
`-
`
`POWER-SAVING DRIVER
`
`'
`PEOLESS
`Al3
`
`SUCH AS APLDRIVERal POWER-SAVING
`
`
`
`OS START
`PROCESSING +
`
`PROCESS
`
`IN
`
`TERMINATION
`
`FIG.5
`
`SET CPU SPEED TO USER-
`DES!GNATED PROCESSING
`SPEED USER USE
`
`
`USER USE
`
`A16 SET CPU SPEED TO
`
`
`
`
`A15
`
`OS TERMINATION MESSAGE
`(Sys_VM_Terminate)
`
`
`
`
`
`HIGHEST SPEED
`
`POWER-SAVINGDRIVER
`
`POWER ON
`
`
`
`
`
` POST PROCESSING
`(SET CPU SPEED TO
`HIGHEST SPEED)
`
`A102
`
`START OS BOOT
`
`3
`
`FIG. 7
`
`0005
`0005
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 5 of 16
`
`US 6,681,336 B1
`
`OS
`
`POWER-SAV ING
`DRIVING
`
`HW
`(VIA BIOS OR DIRECTLY)
`
`QL
`
`L
`BS
`w*
`a
`i
`=
`
`QoQ
`LL
`Ww
`ow
`w~
`
`Sys_Critical_Init
`
`CALL-BACK TIMER
`1S SET
`
`CPU SPEED IS
`SET TO USER-
`DESIGNATED SPEED
`
`ae
`
`es© @°f
`
`hB
`
`Sys_VM_Terminal.|Ser TO HIGHEST
`
`CPU SPE
`
`=
`
`Qo
`Lu
`Be
`ow
`
`a3k
`
`e
`oo
`
`
`
`SPEED
`
`FIG.6
`
`0006
`0006
`
`

`

`
`
`‘Id¥SVHONSi
`ON1SS390Ud8JIs
`
`—NUMLSY
`
`
`
`
`40SONILIAS
`
`—Ysn
`
`
`
`d3ad$fd9
`
`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 6 of 16
`
`US 6,681,336 BL
`
`
`AldVdad0YaSN;AWNSSYSOQNSdSNS F1aVusddYSSNprinJOVSSANNOY4MO0d440YSMOd
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`
`daadSM071
`
`0007
`0007
`
`
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 7 of 16
`
`US 6,681,336 BI
`
`START OF SUSPEND
`
`A21
`
`SUSPEND START MESSAGE
`(APM_SUSPEND)
`
`0S
`
`SUSPEND
`
`SET CPU SPEED T0
`HIGHEST SPEED
`
`CHANGE MACHINE TO
`SUSPEND STATE
`
`A22
`
`A23
`
`A24
`
`POWER-SAVING DRIVER —
`
`OS
`BIOS
`
`RETURN FROM SUSPEND
`IN RESPONSE TO POWER|BIOS
`BUTTON, ETC.
`
`A25
`
`RETURN MESSAGE
`(APM_Resume_Suspend)|9S
`
`RESUME
`
`READ TIMER
`
`A26
`
`A27
`
`POWER-SAVING DRIVER
`
`SET CALLBACK TIMER
`
`POWER-SAVING DRIVER
`
`A28
`
`POWER-SAVING DRIVER
`
`SET CPU SPEED TO
`USER-DES | GNATED
`PROCESSING SPEED
`
`END OF RETURN
`
`FIG.9
`
`0008
`0008
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 8 of 16
`
`US 6,681,336 B1
`
`0S
`
`POWER-SAV I NG
`DRIVING
`
`HW
`(VIA BIOS OR DIRECTLY)
`
`APM_SUSPEND
`
`CPU SPEED IS
`SET TO HIGHEST
`
`USER—
`DES | GNATED
`SPEED
`
`HIGHEST
`SPEED
`
`a -
`APM_Resume_Suspend CALL-BACK TIMER
`
`HI
`ca
`
`|
`
`IS SET
`
`CPU SPEED |S
`SET TO USER-
`DESIGNATED SPEED
`
`USER-
`DES|GNATED
`SPEED
`
`FIG. 10
`
`0009
`0009
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 9 of 16
`
`US 6,681,336 B1
`
`CPU SPEED 1S SET
`“~==+.._|TO HIGHEST SPEED
`
`WARNING EVENT
`SMI PROCESSING
`CPU SPEED !S
`DECREASED
`
`
`
`
`
`CPU=LOW SPEED
`
`
`
`
`
`
`
`
`
`
`POWER ON —
`
`BIOS
`POST PROCESSING
`
`0S
`BOOT PROCESSING
`
`OS OPERAT!ON
`
`
`
`
`
`CPU=
`HIGHEST SPEED
`
`CPU=
`USER-DES | GNATED
`SPEED
`
`FIG. 11
`
`0010
`0010
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 10 of 16
`
`US 6,681,336 BI
`
`0S/DRIVER
`
`READ VALUE (T1) OF TIME STAMP COUNTER (TSC)
`
`EXECUTE INSTRUCTION JMP$ N TIMES
`
`
`
`
`
` EXECUTE
`
`
`READ VALUE (T2) OF TIME STAMP COUNTER (TSC)
`
`IN LOAD
`
`CALCULATE TIME T PER INSTRUCTION JMP$
`(T2-T1)/N
`
`
`
`SAVE T AS REFERENCE VALUE OF LOOP
`COUNTER FOR COUNTING WAIT TIME
`
`FIG. 12
`
`
`
`B15
`
`WARNING EVENT
`
`WARNING EVENT
`SMI PROCESSING
`
`PROCESS| NG
`END ?
`
`NO
`
`CHECK FACTOR ?
`
`B21
`
`TURN OFF AC
`ADAPTER
`
`B22
`
`TEMPERATURE RISE
`
`DECREASE CPU SPEED
`
`DECREASE CPU SPEED
`
`
`
`SET TIME-OUT FLAG TO ”ON”
`
`
`
` OS BOOT
`
`
`
`
`
`
`
` FIG. 18
`
`0011
`0011
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 11 of 16
`
`US 6,681,336 BI
`
`
`
`POWER ON ——> POST PROCESSING
`(SET CPU SPEED TO
`HIGHEST SPEED)
`
`WARN NG EVENT,(DECREASE [CPU SPEED)
`
`
`
`OS OPERATION
`
`
`
`BOOTPROCESS!NG
`
`
` SWITCH CPU SPEED
`
`‘
`SMI PROCESSING #2
`
` CHECK RUNNING OS
`
`
`OS CORRESPOND TO DYNAMIC
`SPEED-UP ?
`
`SPEED-UP
`EVENT
`
`
`
`B110
`
`<0Tine-ouT
`
`
`
`INCREASE CPU SPEED
`
`FIG.13
`
`0012
`0012
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 12 of 16
`
`US 6,681,336 BI
`
` POWER ON ——>
`
`
`POST PROCESSING
`(SET CPU SPEED TO
`
`HIGHEST SPEED)
`
`WARN IN° EXEN'.(DECREASE [CPU SPEED)
`
`
`
`
`
`
`
`INSTALL/ACCESS
`DEDICATED DEVICE
`DRIVER
`
`
`
`BOOTPROCESSING
`
`
`
`OS OPERATION
`
`
`
`
` SWITCH CPU SPEED
`
`'
`SMI PROCESSING #2
`
`
` CHECK RUNNING OS
`OS CORRESPOND TO DYNAMIC
`
`
`SPEED-UP
`EVENT
`
`SPEED-UP ?
`
`0013
`0013
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 13 of 16
`
`US 6,681,336 B1
`
`
`POST PROCESSING
`(SET CPU SPEED TO
`
`WARNING EVENT
`ae >(DECREASE :CPU SPEED)
`
` SPEED-UP
`
`HIGHEST SPEED)
`B101 POWER ON ——>
`
`
` BOOTPROCESSING
`
`CONTINUE OS
`BOOT PROCESS! NG
`
`KB INPUT
`BY USER
`
`B107
`
`WARNING EVENT
`B108 eo
`
`SWITCH CPU SPEED
`
`OS OPERATION
`
`EVENT
`
`'
`
`SMI PROCESSING #2
`
` CHECK RUNNING OS
`SPEED-UP ?
`
`QS CORRESPOND TO DYNAMIC
`
`<0TiMe-0uT
`
` B110
`INCREASE CPU SPEED
`
`
`
`FIG. 15
`
`0014
`0014
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 14 of 16
`
`US 6,681,336 BI
`
`
`
`POST PROCESSING
`(SET CPU SPEED TO
`HIGHEST SPEED)
`WARNING EVENT.(DECREASE :CPU SPEED)
`
`
`
`
`
`
`
`
`B106 =B107 eC
`
`WARNING EVENT ~
`
`
`
`BOOTPROCESSING
`
`
`
`OS OPERATION
`
`
`
` SWITCH CPU SPEED
`
`
`‘
`SMI PROCESSING #2
`
` CHECK RUNNING OS
`
`
`OS CORRESPOND TO DYNAMIC
`SPEED-UP ?
`
`SPEED-UP
`EVENT
`
`
`
`INCREASE CPU SPEED
`
`
`!
`
`‘FIG. 16
`
`0015
`0015
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 15 of 16
`
`US 6,681,336 BI
`
`POWER ON
`
`POST PROCESSING
`
`WARNING EVENT------------------ > (DECREASE CPU SPEED)
`
`END OF BOOT
`
` B405
`
`CHECK USER-DESIGNATED SPEED
`
`B406
`
`B407
`
`NO
`
`
`
`
`HIGHEST SPEED? “
`
`
`
`YES
`
`B408
`
`SWITCH CPU SPEED
`
`SPEED-UP EVENT
`
`FIG. 17
`
`CHECK RUNNING OS
`OS CORRESPOND TO DYNAMIC
`SPEED-UP ?
`
`INCREASE CPU SPEED
`
`0016
`0016
`
`

`

`U.S. Patent
`
`Jan. 20, 2004
`
`Sheet 16 of 16
`
`US 6,681,336 B1
`
`CPU=USER-
`DESIGNATED SPEED
`
`OS OPERAT!ON
`
`SHUTDOWN EVENT
`
`
`“==...|TO HIGHEST SPEED
`
`;
`
`CPU SPEED IS SET
`
`SHUTDOWN
`PROCESS I NG
`
`CPU = HIGHEST
`SPEED
`
`POWER OFF
`
`FIG. 19
`
`0017
`0017
`
`

`

`US 6,681,336 B1
`
`2
`expected value even when the specific instruction is repeti-
`lively executed the same number of times. To normally
`operate a device, at least a wait time equal to or longer than
`the wait time defined by the device must be assured.
`Even if system start processing is executed at a CPU
`speed which is not the highest, and then the CPU speed is
`increased by user’s designation or another predetermined
`factor, device operation fails. In some cases, a serious error
`occurs such that an instruction or data cannot be normally
`read.
`
`BRIEF SUMMARY OF THE INVENTION
`
`it is an object of the present invention to
`Accordingly,
`provide a computer system for implementing high-speed
`start processing or the like, and a CPU speed control method
`therefor.
`
`10
`
`15
`
`1
`SYSTEM AND METHOD FOR
`IMPLEMENTINGA USER SPECIFIED
`PROCESSING SPEED IN A COMPUTER
`SYSTEM AND FOR OVERRIDING THE
`USER SPECIFIED PROCESSING SPEED
`DURING A STARTUP AND SHUTDOWN
`PROCESS
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is based upon and claims the benefit of
`priority from the prior Japanese Patent Applications No.
`11-173015, filed Jun. 18, 1999; and No. 11-299700, filed
`Oct. 21, 1999, the entire contents of which are incorporated
`herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a computer system such
`as a personal computer and, more particularly, to a computer
`system capable of setting the processing speed to a process-
`ing speed designated by user operation, and a processing
`speed control method therefor.
`In recent years, various portable laptop or notebook type
`battery-operable personal computers (to be referred to as
`PCshereinafter) have been developed. For PCs of this type,
`high-speed (high-performance) CPUs have been developed.
`This allows the user to easily obtain a comfortable use
`environment.
`
`a higher-speed CPU requires higher power
`However,
`consumption, increasing the power consumption amount of
`the whole PC and decreasing the battery operating time.
`Recently, in order to save power, a technique for setting
`the processing speed of the system to a predetermined
`processing speed designated by user operation has been
`developed. The processing speed of the system can be set to
`one ofa plurality of speed levels from the highest to lowest
`speeds by, e.g., intermittently operating the CPU at a pre-
`determined period or switching the operating frequency or
`voltage of the CPU. Which of speed levels is to be used
`during the user job period is determined by user’s designa-
`tion.
`
`However, in a conventional system, the processing speed
`designated by user operation effectively acts even during a
`period in which the user cannot actually operate the com-
`puter system, for example, during the start or shutdown
`period of the computer system. For this reason, start or
`shutdownprocessing of the computer system requires a long
`time.
`
`When the CPU speed is switchedto the highest speed by
`user’s designation or another predetermined factor after the
`CPU operates at a low speed during system start processing,
`normal operation may not be assured depending on the
`operating system or drivers. This is because most of oper-
`ating systems and drivers obtain an absolute time necessary
`for a device response wait by software using a software loop
`counter.
`
`More specifically, the operating system or driver calcu-
`lates and registers in system start processing a time neces-
`sary for repetitively executing a specific instruction N times.
`In actually accessing a device,
`the repetitive execution
`number ofthe instruction necessary for a device response
`wail is determined using the registered information. If the
`CPU speedis set, e.g., twice as high as the speed in system
`start processing,
`the actual wait
`time becomes half the
`
`20
`
`30
`
`35
`
`It is another object of the present invention to provide a
`computer system for improving the reliability of system
`operation, and a CPU speed contro! method therefor.
`According to one aspect of the present invention, there is
`provided a computer system comprising: means for desig-
`nating a user to designate a processing speed of a processor;
`meansfor controlling the processing speed of the processor;
`and means for setting the processing speed by the means for
`controlling, setting the processing speed to a highest speed
`a5 during a period for start processing of an operating system
`for the computer system, and the processing speed to the
`user-designated speed during a period other than that for the
`start processing of the operating system.
`invention,
`According to another aspect of the present
`there is provided a computer system comprising: means for
`designating a user to designate a processing speed of a
`processor; means for setting the processing speed of the
`processor; and meansfor setting the processing speed by the
`means for controlling, setting the processing speed to a
`highest speed during a period for shutdown processing/
`suspend processing of the computer system, and the pro-
`cessing speed to the user-designated speed during a period
`other than that for the shutdown processing/suspend pro-
`cessing.
`According to still another aspect ofthe present invention,
`there is provided a processing speed contro] method applied
`to a computer system, comprising the steps of: designating
`a user to designate a processing speed of a processor; and
`operating the processor at a highest speed during a period for
`start processing of an operating system for the computer
`system, and operating the processor at the user-designated
`speed during a periodother than thatfor the start processing
`of the operating system.
`Accordingto still another aspect ofthe present invention,
`there is provided a processing speed control method applied
`to a computer system, comprising the steps of: designating
`a user to designate a processing speed of a processor; and
`operating the processor at a highest speed during a period for
`shutdown processing/suspend processing of the computer
`system, and operating the processor at the user-designated
`speed during a period other than that for the shutdown
`processing/suspend processing.
`Additional objects and advantages of the invention will be
`set forth in the description which follows, and in part will be
`obvious from the description, or may be learned by practice
`of the invention. The objects and advantagesof the invention
`may be realized and obtained by means of the instrumen-
`talities and combinations particularly pointed out hereinaf-
`ter.
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`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
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`The accompanying drawings, which are incorporated in
`and constitute a part of the specification, illustrate presently
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`US 6,681,336 B1
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`3
`preferred embodiments of the invention, and together with
`the general description given above and the detailed descrip-
`tion of the preferred embodiments given below, serve to
`explain the principles of the invention in which:
`FIG, 1 is a block diagram showing the arrangement of a
`computer system common to both the first and second
`embodiment of the present invention;
`FIG, 2 is a view showing an example of a CPU speed
`setting window for the user in the first embodiment;
`FIG. 3 is a view for explaining the principle of system
`control method used in the first embodiment;
`FIGS 4A and 4B are block diagrams cach showing the
`logical relationship between a power-saving driver, OS,
`BIOS, and hardware used in the first embodiment;
`FIG. 5 is a flow chart showing the flow of a series of
`control operations executed from the start to the termination
`of the system in the first embodiment;
`FIG. 6 is a view showing a processing sequence when
`attention is given to exchange of messages between the OS
`and power-saving driver used in the system of the first
`embodiment;
`FIG. 7 is a flow chart showing processing procedures
`when the CPU processing speed in start processing is set to
`the highest speed by a BIOS used in the system of the first
`embodiment;
`FIG. 8 is a view for explaining the principle of system
`contro] method in suspend/resume processing in the system
`of the first embodiment;
`FIG. 9 is a flow chart showing the flow of a series of
`control operations executed in suspend/resumein the system
`of the first embodiment;
`FIG. 10 is a view showing a processing sequence when
`attention is given to exchange of messages between the OS
`and power-saving driver used in the first embodiment;
`FIG. 11 is a view for explaining the principle of system
`control method used in the second embodiment of the
`present invention;
`FIG. 12 is a flow chart showing an example of software
`loop countersetting processing executed by an OSordriver
`used in the second embodiment in loading the OS or drive
`FIG. 13 is a flow chart showing the first example for
`implementing the system control method of the second
`embodiment
`
`FIG. 14 is a flow chart showing the second example for
`implementing the system control method of the second
`embodiment;
`FIG. 15 is a flow chart showing the third example for
`implementing the system control method of the third
`embodiment;
`FIG. 16 is a low chart showing the fourth example for
`implementing the system control method of the fourth
`embodiment;
`FIG. 17 is a flow chart showing the fifth example for
`implementing the system contro] method of the fifth
`embodiment;
`FIG, 18 is a flow chart showing the procedures of warning
`event SMI processing used in the second embodiment; and
`FIG, 19 a view showing CPU speed control during
`shutdown processing in the second embodiment.
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`Preferred embodiments of the present invention will be
`described below with reference to the several views ofthe
`
`accompanying drawing.
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`FIG. 1 shows the arrangement of a computer system
`common to both the first and second embodiments of the
`present invention.
`This computer system is a battery-operable notebook type
`personal computer (PC). When poweris externally supplied
`via an AC adapter 181, the PC operates by the external
`power, and a battery 182 is charged. When the AC adapter
`181 is not connected to the PC main body, e.g., the PC is
`used in a mobile environment, the PC operates by power
`from the battery 182.
`the PC main body includes a
`As shown in FIG. 1,
`processor bus 1, PCI bus 2, ISA bus 3, CPU 11, host-PCI
`bridge 12, main memory 13, display controller 14, PCI-ISA
`bridge 15, 1/O controller 16, BIOS-ROM 17, power supply
`controller 18, keyboard controller (KBC) 19, and CMOS
`memory 20.
`The CPU 11 controls the operation of the whole PC, and
`executes the BIOS in the BIOS-ROM 17, an operating
`system loaded to the main memory 13, and various other
`programs. This system can control the processing speed of
`the CPU 11 at multiple stages (a plurality of levels), The
`CPUspeedis controlled using a CPU throttling function(to
`be described later) and a function called a speed-step or
`GEYSERVILLEfunction.
`
`The CPU speed level to be used is determined by user’s
`designation or another predetermined factor. This system
`operates the CPU 11 al a predeterminedarbitrary processing
`speed (e.g., highest speed) regardless of the user-designated
`processing speed during a period except for a user operable
`period. The CPU speed variably-setting function will be
`described in detail below.
`
`The CPU 11 in FIG. 1 includes the following system
`management functions.
`That is, the CPU 11 includes a real mode, protected mode,
`and virtual 86 mode for executing an application program or
`a program such as an OS,and in addition an operation mode
`called a system management mode (SMM) for executing a
`system management program.
`In the real mode, a maximum of a 1-Mbyte memory space
`can be accessed. A physical address is determined by an
`offset value from a base address represented by a segment
`register. In the protected mode, a maximum of a 16-Mbyte
`memory space can be accessed. A linear address is deter-
`mined using an address mapping table called a descriptor
`table. This linear address is finally converted into a physical
`address by paging. In the virtual 86 mode, a program written
`to operate in the real modeis operated in the enhanced mode.
`A program in the real mode is processed as one task in the
`enhanced mode.
`
`The system management mode (SMM)is a pseudo real
`mode in which no descriptor table is referred to and no
`paging is executed. When a system management interrupt
`(SMI)is issued to the CPU 1, the operation mode of the
`CPU11 is switched from thereal, protect, or virtual 86 mode
`to the SMM. In the SMM, a system management program is
`executed.
`
`The SMI is a kind of non-maskable interrupt NMI, which
`is an interrupt having the highest priority, compared to a
`normal NMI or maskable interrupt INTR. This SMI can be
`issued to start various SMI service routines prepared as
`sysiem management programs independently of a running
`application program or the OS environment,
`The host-PCI bridge 12 is a bridge device for bidirection-
`ally connecting the CPU bus 1 and PCI bus 2. The host-PCI
`bridge 12 incorporates a memory control
`function for
`access-controlling the main memory 13.
`
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`US 6,681,336 B1
`
`5
`The main memory 13 stores an operating system, appli-
`cation programs/utilities to be processed, drivers, data cre-
`ated by these programs, and the like. When the CPU 11
`shifts to the SMM, the CPU status, Le., the register ofthe
`CPU 11 upon generation of an SMI is saved with a stack
`format in an SMRAM mappedinto a predetermined address
`space in the main memory 13. This SMRAM stores an
`instruction for calling the system management program of
`the BIOS-ROM 17. This instruction is executed first when
`the CPU 11 shifts to the SMM. By executingthis instruction,
`the control shifts to the system management program.
`The display controller 14 displays display data stored in
`an image memory (VRAM) 141 on oneor both of an LCD
`142 and external CRT143 attached to the PC main body. The
`display controller 14 can operate as the bus master of the
`PCI bus 2.
`
`The PCI-ISA bridge 15 connects the PCI bus 2 and ISA
`bus 3, and can operate as the bus master of the PCI bus2.
`The PCI-ISA bridge 15 includes an SMI generation circuit
`151 and CPU speed control circuit 152.
`The SMI generation circuit 151 generates an SMI signal
`to the CPU 1. The SMI signal is generated by a software
`SMI, an I/O trap SMI, or an SMI caused by a specific
`hardware event.
`
`The software SMI is generated using a register or down
`counter accessible by software. That
`is, when software
`writes data in the internal register of the SMI generation
`circuit 151, an SMI signal
`is generated, Further, when a
`value corresponding to a time till generation of an SMI
`signal
`is set
`in the internal down counter of the SMI
`generation circuit 151, an SMI signal is generated in time-
`out.
`
`The I/O trap SMI is generated by executing an IN or OUT
`instruction by software using a predetermined I/O address.
`An I/O address value to be monitored at which an 1/O trap
`SMI is wanted to be generated is set in the SMI generation
`circuit 151. Then, whenthis I/O address is accessed, the I/O
`trap SMI can be generated.
`The SMIby a specific hardware event is generated by
`hardware upon occurrence ofan event necessary for system
`management, ¢.g., upon a change in CPU temperature or
`insertion/removal of the AC adapter 181.
`The CPU speed control circuit 152 controls the processing
`speed of the CPU 11, and has a throttling controller for
`switching the CPU speed using the “CPU throttling
`function”, and a frequency/voltage controller for switching
`the CPU speed using the “GEYSERVILLE”function.
`These functions are used to variably set
`the processing
`speed of the CPU 11 using the “CPU speed variably-setting
`function” according to the present invention.
`
`1) “CPU Throttling Function”
`
`The “CPUthrottling function” is a function of switching
`the average CPU processing speed by performing intermit-
`tent operation of operating/stopping the CPU LI at a prede-
`termined interval. This function may be called an interval
`stop clock function or intermittent operation function.
`Astate in which the “CPU throttling function” is disabled,
`i.¢., the CPU 11 always operates corresponds to the highest
`speed of the CPU LL. A state in which the “CPU throttling”
`is enabledat an arbitrary % (ratio of the stoppedstate to the
`operating state) corresponds to a speed which is not
`the
`highest speed. By changing the ratio of the stopped state to
`the operating state,
`the CPU speed can be controlled at
`multiple stages.
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`In this system, a state in which the CPU 11 always
`operates is defined as a default state.The CPU 11 always
`operates at
`the highest speed until
`the “CPU throttling”
`starts. The operating/stopped state of the CPU LL is switched
`using a stop clock signal (STPCLK). The stop clock signal
`(STPCLK) ts a clock state control signal supported by CPU
`486SL or Pentium™available from INTEL Corp.
`
`2) “GEYSERVILLE Function”
`The “GEYSERVILLE function” is the function of CPU
`
`MobilePentium3™ available from INTEL Corp., and
`dynamically switches the operating frequency and voltage of
`the CPU. A state in which the operating frequency and
`voltage are set
`to high-order ones supported by the CPU
`corresponds to the highest speed of the CPU. A state in
`which the operating frequency and voltage are set to low-
`order ones corresponds to a speed which is not the highest
`speed.
`In the use of either the function 1) or 2), the CPU speed
`can be switched by writing necessary data in the internal
`register of the CPU speed control circuit 152.
`The PCI-ISA bridge 15 has a function of monitoring the
`CPU temperature using a temperature sensor 21 andits drive
`circuit 22, and a function of monitoring insertion/removal of
`the AC adapter via the power supply controller 18. When the
`CPU temperature reaches a predetermined temperature or
`more, or the ACadapter is removed to turn off the AC
`adapter power supply, the PCI-ISA bridge 15 notifies the
`system BIOS by an SMI of occurrence of a warning event
`which influences the safety of system operation. In this case,
`processing of forcibly decreasing the CPU speed is done
`under the control of the system BIOS,
`The I/O controller 16 incorporates a bus master IDE
`controller for controlling an IDE device such as an HDD
`161. The bus master IDE controller can operate as a bus
`master for data transfer between the HDD 161 and the main
`memory 13, The [/O controller 16 can also control DVD and
`CD-ROM drives. The HDD 161 records setting information
`managed by the operating system, in addition to various
`programsand data.
`The BIOS-ROM 17 stores a system BIOS (Basic Input/
`Output System), and is constituted by a flash memory so as
`to rewrite a program, The system BIOS operates in the real
`mode. This system BIOS includes a POST (Power-On Self
`Test) routine executed in powering on or restarting the
`system, a device driver for controlling various I/O devices,
`a BIOS setup routine for setting the system environment,
`and a system management program (run time) for executing
`various SMI processes.
`The BIOS setup routine presents to the user a setup
`window including varioussetting items such assetting of the
`CPU speed, thereby setting the system to a user-designated
`environment.
`
`The power supply controller 18 controls power-on/olf
`operation of the PC, and has a state monitoring function of
`monitoring ON/OFFoperation of a power switch 183, the
`residual capacity of the battery 182, insertion/removal of the
`AC adapter 181, and ON/OFF operation of the open/close
`detection switch of the display panel.
`The keyboard controller (KBC) 19 controls the keyboard
`and mouse. The CMOS memory 20 holds various pieces of
`system setting information, and is backed up by its own
`battery. CPU speed information designated by the user is
`saved in, e.g., the CMOS memory 20.
`The above-described arrangement is common toboth the
`first and second embodiments.
`
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`US 6,681,336 B1
`
`7
`Next, the arrangement related to the first embodiment will
`be described below.
`In the first embodiment, variable setting of the processing
`speed of the CPU 11 in the CPU speed control circuit 152 is
`executed by, ¢.g., a power-saving driver (program) which
`runs on the operating system. This power-saving driver
`originally sets the processing speed of the CPU 11 to a
`user-designated speed. In the first embodiment, the power-
`saving driver has the above-mentioned CPU speedvariably-
`setting function of operating the CPU LI at a predetermined
`arbitrary processing speed (e.g., highest speed) regardless of
`the user-designated processing speed during a period except
`for a user operable period. The power-saving driver controls
`the CPU speed control circuit 152 via the system BIOS or
`directly without the mediacy of the system BIOS.
`Setting processing of the CPU speed by the user may be
`done using the above-described BIOS setup routine. The
`first embodiment assumesthatsetting processing of the CPU
`speed by the user is done using the power-saving driver. In
`practice, the power-saving driver itself does not present a
`setting window including various power-saving setting
`items to the user, but a setting window like the one shown
`in FIG. 2 is presented via a dedicated program such as a
`power-saving utility, CPU processing speed information set
`by GUI operation bythe user is recorded in a predetermined
`area (e.g., registry area) of the HDD 161 to which the
`power-saving driver can refer.
`<Principle of System Control Methodin First Embodiment>
`The principle of system control method used in thefirst
`embodiment will be explained with reference to FIG. 3.
`If a system start event (power-on operation,reset, restart,
`or the like) occurs, POSTprocessing (hardware check and
`initialization processing) is executed by the system BIOS,
`and start processing (OS bootstrap sequence) of the operat-
`ing system (OS)starts. At this time, the CPU 11 operates at
`a predetermined default speed. In the first embodiment, the
`highest speed is selected as the default speed of the CPU U1,
`and the CPU IL automatically operates at the highest speed
`until the power-saving driver performs setting processing.
`The OS bootstrap sequence has several stages. Start
`processing of the OS itself is completed via load of a kernel,
`load of various device drivers, and their initialization pro-
`cessing. In loading device drivers, the power-saving driver
`of this embodiment is also loaded.
`The power-saving driver detects completion of start pro-
`cessing of the OS itself upon reception of a start completion
`message from the OS. The start completion message
`changes depending on the type of OSin use. In many cases,
`a plurality of messagesare issued from the OSat aninterval
`in accordance with the stage of start processing. Thus, the
`final detectable message is detected as an OSstart comple-
`tion message. For example, in Windows 95/98™available
`from Microsoft Corp., a message Sys
`_VM_
`Init is prefer-
`ably used as an OSstart completion message. Sys_WM _
`Init notifies each driver (VxD) of initialization of a virtual
`machine (System VM).
`If the power-saving driver detects from the OS start
`completion message that OSstart processing is substantially
`completed, the driver waits for