US006516422B1
`(10) Patent No:
`a2) United States Patent
`US 6,516,422 B1
`Doblaretal.
`(45) Date of Patent:
`Feb. 4, 2003
`
`
`(54) COMPUTER SYSTEM INCLUDING
`MULTIPLE CLOCK SOURCES AND
`FAILOVER SWITCHING
`Inventors: Drew G. Doblar, San Jose; Leo Yuan,
`Los Altos; Emrys J. Williams,
`Sunnyvale, all of CA (US)
`Sun Mi
`t
`Inc., Santa Cl
`73)
`Assi
`>:
`3) SENETOe nes Sala
`cates)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`(75)
`
`(*) Notice:
`
`lara,
`
`Motorola, Inc., Semiconductor Technical Data, “Dynamic
`Switch PLL Clock Driver,” Sep. 1997, pp. 1-6.
`“Synchronization Between DMS Exchanges”, Probert,
`Northern
`Tel
`Canada Ltd., ISS 81 CIC Montreal 21-25
`Sep 1981— ,
`—s
`* cited by examiner
`Primary Examiner—Icfircy Gaffin
`Assisiant Examiner—Harold Kim
`(74) Attorney, Agent, or Firm—Meyertons Hood Kivlin
`Kowert & Goetzel, P.C.; B. Noél Kivlin
`(57)
`ABSTRACT
`
`(21) Appl. No.: 09/320,794
`
`Filed:
`May27, 1999
`(22)
`4
`Int. C1.eee esc nenereneeeeies GO6F 11/00
`(51)
`(52) U.S. CD.eee 713/503; 713/500; 327/295;
`395/180
`(58) Field of Search oo... 713/500, 503;
`327/295; 395/180
`
`(56)
`
`References Cited
`
`Asystem and methodfor providing redundant, synchronized
`clocks in a computer system. Upon a failure of a master
`clock signal, the system switchesoverto a slave clock signal
`synchronized with the master clock signal. Switching logic
`is coupledto receivea first clock signal and a second clock
`signal. The switching logic selects either the first clock
`signal or the second clock signal as a local clock signal. The
`switching logic further monitors the first clock signal for a
`failure. If a failure is monitored, the switching logic accepts
`the second clock signal as the local clock signal in place of
`the first clock signal. One or more clock local loads operate
`accordingto the local clock signal. The switching logic may
`control the input to a phase locked loop (PLL)that provides
`U.S. PATENT DOCUMENTS
`‘the eal clos signalto the Ieeal clock toads.ine method
`4,025,874 A
`S/L9T7 ADDY ceesessecsssssssesteeeee 3315
`eludes, @. BLL synchronizing, am cutput clecksignal ‘wit
`4,282,493 A
`8/1981 Morea oeccesscessseessseessees ggio,
`
`the master clock signal. The output clock signal is used by
`4.511.859 A
`. 33/1
`A985 Domibrowslel seven
`at least one local clock load for timing. The switching logic
`.......... 331/2
`5.416.443 A *
`5/1995 Cranford, Ir. et al.
`monitors the master clock signal and the slave clock signal
`ce 375/357
`5,422,915 A *
`6/1995 Byers et al.
`.........
`
`
`5,515,403 A for a failure. Uponafailure of either the master clock signal5/1996 Sloanet al. cecccccsessecese 375/371
`
`
`6/1996 Yamasaki... 327/20
`5,523,708 A *
`or the slave clock signal,
`the switching logic notifics a
`5,530,726 A
`6/1996 Ohno wees
`we 375/357
`system controller of the failure. Upon the failure of the first
`
`5,648,964 A
`7/1997 Inagakietal. .
`vee 370/228
`clock signal, the switching logic switches the second clock
`5,774,705 A *
`6/1998 Leshem ...........
`we 395/556
`signal in place of thefirst clock signal as the master clock
`5,852,728 A * 12/1998 Matsudact al.
`..
`.. 395/556
`signal
`for
`the PLL, causes the second clock signal
`to
`5,883,533 A
`3/1999 Matsuda etal. ..
`+ 327/156
`fail-over and to take over as the master clock source to the
`5,969,558 A
`10/1999 Abe oe vee 327/292
`PLL, and causes the second clock source to provide a
`
`6,194,969 Bl—2/2001 Doblar .....eceeeecce 331/2 reference control signal to the second clock source. Clock
`switching is automatic and does not interrupt or interfere
`CHER PUBLICATIONS
`with operation of the computer system.
`International Search Report, Application No. PCT/US
`00/13442, mailed Oct. 6, 2000.
`
`14 Claims, 7 Drawing Sheets
`
`CONTROL
`432
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`PLL 300 || SWITCHING
`
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`106
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`SELECT |
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`AMD EX1006
`AMD EX1006
`U.S. Patent No. 6,895,519
`U.S. Patent No. 6,895,519
`
`

`

`U.S. Patent
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`Feb.4, 2003
`
`Sheet 1 of 7
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`US 6,516,422 B1
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`100 ‘\
`
`
`
`CLOCK
`CLOCK
`BOARD 0
`
`
`
`BOARD1
`
`
`
`105A
`105B
`
` 106A ~_
`
`
`abo— 1068
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` SYSTEM
`
`CONTROLLER
`
`410
`SYSTEM
`
`BOARD
`
`120
`
`
`FIG. 1
`
`0002
`0002
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`

`

`U.S. Patent
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`Feb.4, 2003
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`Sheet 2 of 7
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`US 6,516,422 B1
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`CLOCK
`COURCES
`
`
` OTHER
`
`
`C3
`
`
`
`
`REF_SEL_L
`
`
`
`DETECTOR
`
`210A
`208B
`
` CLOCK
`COURCES C3
`
`
`CLOCK BOARD 1 105B
`
`FANOUT BUFFER
`
`
`
`REF_SEL_L
`
`REF_SEL
`
`0003
`0003
`
`
` PHASE
`
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`DETECTOR
`
`210B R7 | 2u88
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`

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`U.S. Patent
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`Feb. 4, 2003
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`Sheet 3 of 7
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`US 6,516,422 B1
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`Feb. 4, 2003
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`Feb. 4, 2003
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`U.S. Patent
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`Feb. 4, 2003
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`US 6,516,422 Bl
`
`1
`COMPUTER SYSTEM INCLUDING
`MULTIPLE CLOCK SOURCES AND
`FAILOVER SWITCHING
`
`FIELD OF THE INVENTION
`
`This inventionrelates to timing in electronic systems, and,
`more particularly,
`to systems employing redundant, syn-
`chronous clock distribution.
`
`10
`
`DESCRIPTION OF THE RELATED ART
`
`2
`In a further embodiment,the first clock source is incor-
`porated on a first clock board, and the second clock source
`is incorporated on a second clock board. The system further
`includes, in this embodiment, a system board, and a system
`controller. The system board. is coupled to receive both the
`first clock signal and the second clock signal. The system
`board is configured to selectively use either the first clock
`signal or the second clock signal as a local clock signal. The
`system controller is coupled to the first clock board, the
`second clock board, and the system board. The system
`controller is configured to monitor both the first clock signal
`and the second clock signal for a failure. The first clock
`board may be removed from the system, such as upon a
`failure, and a third clock board placed in the system in place
`of the first clock board. The second clock board is switched
`
`The need to generate a local signal which is synchronized
`with an external reference signal is critical in many elec-
`tronics applications such as frequency synthesis, clock
`from being the slave clock source to the master clock source.
`recovery, clock generation and frequency demodulation.
`The third clock board is configured to operate as the slave
`This coherence between the reference signal and the local
`clock source upon being placed in the system. The remov-
`replica is referred to as “phase synchronization”. This
`able clock board may advantageously result in higher uptime
`implies either that local signal is typically either in phase
`for the system as a failed clock board may be replaced while
`with the external reference signal or is offset from the :
`the system is in use,
`reference signal by some phase constant.
`A method is likewise contemplated for providing
`At
`the heart of many such synchronization circuils is
`redundant, synchronous clock signals. The method
`some form of a phase locked loop (PLL). Phase-locked
`comprises, in one embodiment, a first clock source provid-
`loops are feedback control loops, whose controlled param-
`ing a first clock signal as a master clock signal to a phase
`eter is the phase of a locally generated replica of an 2
`locked loop (PLL). A second clock source provides a second
`incoming reference signal. Phase-locked loops have three
`clock signal as a slave clock signal to the PLL, where the
`basic components: a phase detector, a loop filter, and a
`slave clock signal is synchronized with the master clock
`voltage-controlled oscillator.
`signal. The PLL synchronizes an output clock signal with the
`Generally speaking, electronic systems such as computer
`master clock signal. The output clock signal is used by at
`systems produce a master clocking signal from a crystal. The
`least one local clock load for timing. The switching logic
`master clocking signal may be fed into a PLL to produce
`monitors the master clock signal and the slave clock signal
`many identical clock signals (e.g. fanout) that are used to
`for a failure. Uponafailure ofeither the master clock signal
`synchronize the components of the computer system.
`or the slave clock signal,
`the switching logic notifies a
`The master clock signal is a critical component of the
`system controller of the failure. Upon the failure of the first
`computer system. The failure of the master clock signal may
`clock signal, the switching logic switches the second clock
`disable the entire system. Thus, to alleviate this problem,
`signal in place of the first clock signal as the master clock
`some systems incorporate two master clock signals, one of
`signal for the PLL. Also uponreceiving notice of the failure
`which is redundant. Upona failure of the first master clock
`of the first clock signal, the system controller causes the
`signal, the system is shut down and maybereinitialized
`second clock signal
`to fail-over and to take over as the
`using the second master clock signal. However, such a
`master clock source to the PLL. Uponreceiving notice of the
`requirement disrupts system operation. Accordingly,
`it
`failure of the first clock signal, the system controller further
`would be desirable to provide a system that can fail-over
`causes the second clock source to provide a reference
`from one clock source to another clock source without
`control signal to the second clock source. The method may
`advantageously maintain continuous operation of the com-
`puter system while switching between clock sources.
`In preferred embodiments, clock switching from a failed
`master clock to a redundant slave clock is automatic and
`
`causing a disruption to system operations.
`
`45
`
`SUMMARY OF THE INVENTION
`
`The problems outlined above are in large part solved by
`a system and method for providing redundant, synchronized
`clocks in a computer system. Upon a failure of a master
`clocksignal, the system switches over to a slave clock signal
`synchronized with the master clock signal.
`In one
`embodiment, switching logic is coupled to receive a first
`clock signal and a second clock signal. The switching logic
`is configured to select either the first clock signal or the
`second clock signal as a local clock signal. The switching
`logic is further configured to monitor the first clock signal
`fora failure. Ifa failure of the first clock signal is monitored,
`the switching logic is further configured to accept the second
`clock signal as the local clock signal in place of the first
`clock signal. The system also includes one or more clock
`local loads that operate according to the local clock signal.
`In another embodiment, the switching logic controls the
`input to a phase lock loop that providesthe local clock signal
`to the local clock loads. This configuration may advanta-
`geously allow a redundant, synchronous slave clock to
`replace a master clock upon failure of the master clock.
`
`does not interrupt or interfere with the operations of the
`computer system. No halt and restart are necessary.
`‘The
`clock changeis transparent to the local clock loads using the
`local clock signal.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Other objects and advantages of the invention will
`become apparent upon reading the following detailed
`description and upon reference to the accompanying draw-
`ings in which:
`FIG. 1 is a block diagram of an embodiment of a
`generalized computer system including two clock boards
`and a system board;
`FIG. 2 is a block diagram of an embodimentof the clock
`boards of FIG. 1;
`FIG. 3 is a block diagram of an embodimentof the system
`board of FIG. 1;
`FIG. 4 is a block diagram of an embodimentofthe select
`phase locked loop of FIG. 3;
`
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`US 6,516,422 Bl
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`10
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`3
`FIGS. 5A and 5B are block diagrams of embodiments of
`the phase detector of FIG. 4, which incorporates a supple-
`mental correction pulse generator and a pulse limiting
`circuit; and
`FIG. 6 is a timing diagram illustrating an embodiment of
`advanced operations of the select phase locked loop of FIG.
`4, including switchover to a backup clock source, limited
`width phase error signal pulses, and a supplemental error
`correction pulse.
`While the invention is susceptible to various modifica-
`tions and alternative forms, specific embodiments thereof
`are shown by way of example in the drawings and will
`herein be described in detail.
`It should be understood,
`however, that the drawings and detailed description thereto
`are not intended to limit the invention to the particular form
`disclosed, but on the contrary, the intention is to cover all
`modifications, equivalents and alternatives falling within the
`spirit and scope of the present invention as defined by the
`appended claims.
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`4
`voltage within the operating voltage range of the VCXO
`220A, wherein the control voltage causes the VCXO 220A
`to generate a reference output
`frequency, such as,
`for
`example, 75 MHz. In a preferred embodiment, the operating
`voltage range is from 0-3.30 V, and the fixed reference
`voltage is 1.65 V.
`The frequency output of the VCXO 220Ais preferably
`one of several clock inputs that may be multiplexed into the
`circuit. The selected output of the multiplexer is provided to
`a fanout buffer 208A. Fanout buffer 208A outputs a plurality
`of clock signals 106A for various destinations, such as for
`clocking on clock board-0 105A, clock board-1 105B,
`system board 120, or other boards, components, ctc. of
`computer system 100. As noted, other clock sources may
`also be provided to the multiplexer. Examples of other clock
`sources include VCXOs with differing operating frequency
`ranges, fixed frequency sources, other VCOs,etc.
`Clock board-0 105A may also include a phase detector
`210A coupled to receive one of the clock signals 106A from
`the fanout buffer 208A. The phase detector 210A is also
`coupled to receive another clock signal, such as clock signal
`106B, as shown. The phase detector 210A outputs a phase
`error signal in response to receiving, the two clock signals
`FIG. 1—Generalized Computer System
`106A and 106B. In the embodimentillustrated, the phase
`Turning to FIG. 1, a block diagram of an embodimentof
`error signal is output as an UP signal and/or a DOWNsignal,
`a generalized computer system 100 is shown. A first clock 2
`reflecting the phase of the first input clock signal being
`source, shown as clock board-0 105A,providesa first clock
`behind or ahead of the second input clock signal. ‘the phase
`signal 106A to clock board 1 105B and to system board 120.
`Clock board-1 105B is illustrated as a second clock source,
`error signal
`is filtered by an active filter 215A formed
`collectively in the illustrated embodiment by a network of
`which provides a second clock signal 106B to clock board-0
`resistances R1-RS, capacitances C1—C3, and an operational
`105A and to the system board 120. A system controller 110
`amplifier 216A. The filter 215A preferably acts as a low pass
`is coupled to the two clock boards 105A and 105B as well
`filter and integrator of the UP and DOWNpulses from the
`as to the system board 120.
`phase detector 210A.
`As is described below in more detail, the system board
`The output of the filter 215A may be presented to the
`120 receives both the first clock signal 106A and the second
`switch 218A.In the open, or master position, the feedback
`clock signal 106B. The first clock signal 106A and the
`dependentsignal from the phase detector 210A and thefilter
`second clock signal 106B are preferably in phase ona rising
`215A are not provided to the VCXO 220A.
`Instead, a
`edge, phase and frequency locked, although the frequencies
`constant voltage, such as established by a voltage divider
`of each clock signal 106A and 106B maydiffer by an integer
`formed by resistors R6 and R7, is provided to control the
`multiple. Upon a failure of one of the clock signals 106A or
`VCXO 220A.
`106B, which is currently serving as the master clock signal,
`Whenthe switch 218Ais in the slave, or closed, position,
`the system controller 110 switches in the other clock signal,
`the output of the filter 215A is presented to the switch 218A.
`106A, 106B, previously serving as the slave clock signal, as
`It is noted that the drive associated with the filter 215A,
`the new master clock signal. ‘hus, the slave clock signal,
`whenthe switch 218Ais closed,is sufficient to overdrive the
`perhaps from clock board-1 105B, takes over as the master
`constant control voltage established by the resistors R6 and
`clock signal, such as when clock board-0 105A fails to
`R7. In the illustrated embodiment, the switch 218A is a
`provide the expected master clock signal 106A.
`It is noted that system controller 110 or parts thereof may passgate, implemented usingapair offield effect transistors.
`
`be incorporated on any of clock board-@ 105A, clock
`Other embodiments of the switch 218A are contemplated
`board-1 105B, system board 120, or any other board or
`where the signal from thefilter 215A selectively controls the
`component of computer system 100, as desired.
`In the
`VCXO 220A, along with an alternative source for the
`embodiments illustrated in FIGS. 2-5, a portion of the
`control signal 205A. For example, one embodiment of
`system controller 10 may be comprised on each board
`switch 218A selects between the output of the filter 215A
`shown, even when not expressly illustrated. A portion of
`and a power supply voltage as the control voltage 205A.
`system controller 110 may be included in each select PLL
`The switch 218A is controlled by the reference select
`300, as described below with respect to FIG. 3.
`signals, REF_SEL and a REF_SEL_L,a pair of comple-
`FIG. 2—Clock Boards and Clock Signals
`mentary control signals. In one embodiment, the controller
`Turning now to FIG. 2, an embodiment of two clock
`110 generates the reference select signals.
`boards 105A and 105B and the coupling of their respective
`In a preferred embodiment, clock board-1 105B and clock
`clock signals 106A and 106Bare illustrated. Clock board-0
`board-0 105A are duplicates of each other and
`105A includes a voltage controlled crystal oscillator
`interchangeable, capable of operating in a similar manner. In
`(VCXO) 220A coupled to receive a control signal 205A. As
`this embodiment, with clock board-@ LOS5A acting as a
`illustrated, the source of the control signal 205A is deter-
`master clock source with the output of the VCXO 220Aat
`mined by a switch 218A. When the switch 218Ais in the
`a fixed frequency, clock board-1 105B acts as a slave clock
`mastcr position (off, in this casc), making clock board-0
`source. The master clock 106A is fcd into phase detector
`105A the master clock source, the source of the control
`210B as the reference clock, with the output of clock
`signal 205A is preferably a fixed reference voltage. In one
`board-1 105B also input into phase detector 210B as the
`embodiment,
`the fixed reference voltage generated is a
`feedback clock. With switch 218Bin the slave position, the
`
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`

`

`US 6,516,422 Bl
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`5
`circuit shown on clock board-1 105B functions as a PLL.
`Clock signal 106B is continually phase aligned with clock
`signal 106A.
`As will be described below with reference to FIG. 3, each
`board(e.g. clock boards 105A and 105B, system board 120,
`etc.) in computer system 100 may include one or moreselect
`PLLs 300 coupled to receive both the master clock signal
`106A and the slave clock signal 106B. Each select PLL 300
`is further configured to output clock signals for local use by
`local clock loads at frequencies that are fractions or mul-
`tiples of the master clock frequency, including a multiplier
`of one.
`
`In various embodiments, upon a failure of the master
`clock source, the system controller 110 determines and/oris
`notified of the failure. The system controller 110 then
`switches the slave clock source over to function as the new
`
`10
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`15
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`20
`
`master clock source. The system controller 110 may also
`notify the computer system 100, e.g. the computer user via
`a display, that the master clock source has failed. The failed
`clock source, e.g. a clock board, may be replaced without
`interrupting or interfering with the operations of the com-
`puter system 100. Clock switching thus occurs automatically
`and “onthe fly”. Preferably, the change in the clock source
`is transparent to the synchronouslogic relying on the clock
`source. Once a replacement clock board has been added to 2
`the computer system 100, the system controller 110 prefer-
`ably switches the replacement clock board into slave mode,
`to provide a new phase-aligned redundant clock source.
`It is noted that failure of a clock signal may be due to
`many causes, such as clock source failure, wiring or con-
`nection failure, etc. The cause of the clock signal failure is
`less important than the knowledgethat the clock signal is not
`correctly propagating through the system. It is also noted
`that in various embodiments, the VCXO 220 may be any
`type of VCO 220.
`In an embodiment in which VCXOs 220A and 220B are
`
`used, the relatively small operating frequency range of a
`VCXO, compared to a conventional VCO, mayprovide for
`advantageous operation. Upon the loss of the input clock
`signal 106A, the output of the VCXO 220B will onlyfall in
`frequency by a relatively small amount, such as 200 PPM.
`When the slave VCXO 220B fails-over to become the
`master clock source, the VCXO 220B input will be a step
`function increase or decrease in frequency due to switching
`in the constant control voltage described above. The VCXO
`220B preferably limits the rate of change of the frequency to
`within the operating response range of the select PIIs 300
`and other downstrcam local clock loads 350, both discussed
`in FIG. 3 below.
`
`FIG. 3—System Board
`FIG. 3 illustrates an embodiment of a system board 120.
`Clock signals 106A and 106B are provided to the system
`board 120 to a select PLL 300. The select PLL 300is also
`coupled to receive status and control signals over control bus
`330. Control bus 330 may be implementedas, for example,
`an I?C bus. The control bus 330 provides a communications
`pathway between the system controller 110 and the local
`control mechanismsof the select PLL 300.
`The select PLL 300 produces a clock signal synchronized
`with the appropriate input clock signal 106. The select PLL
`300 may output multiple clock signals at different frequen-
`cies. The output clock signals are provided to one or more
`fanout buffers, such as fanout buffers 208C and 208D, as
`shown. The fanout buffers 208C and 208D provide multiple
`local clock signals to the local clock loads 350. As shown,
`fanout buffer 208C providesa first clock frequency, such as
`75 MHz,to selected ones of the local clock loads 350, while
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`fanout buffer 208D provides a second clock frequency, such
`as 150 MHz,to other selected ones of the local clock loads
`350.
`
`It is noted that the local clock loads may include any
`device on the system board 120 that uses a local clock signal
`for synchronization or timing, including but not limited to
`synchronous logic, memory, and/or other electronic ele-
`ments. It is further noted, that the system board 120 may be
`representative of any board or component in the computer
`system, such as an input/output board, memory sub-system,
`clock board, etc. In various embodiments, the system board
`is incorporated in a personal computer, a network computer,
`or a server computer, although other computcr systems are
`also contemplated. Additional details of the operation of the
`select PLL 300 is shown below with respect to FIGS. 4-6.
`FIG. 4—PLL with Switching Logic and Supplemental Error
`Correction
`
`Turning to FIG. 4, a block diagram of a phase locked loop
`(PLL) circuit is illustrated. Preferably implemented as a
`monolithic integrated circuit, select PLL 300 includesa first
`multiplexer coupled to receive a first
`input clock signal
`106A from the first clock source and the second input clock
`signal 106B from the second clock source. The multiplexer
`is controlled by a signal from an OR block coupled to
`receive a select clock input SEL_CLK and the output of
`switching logic 430. The select clock input sets the identity
`of the primary clock input. Switching logic 430 receives
`control inputs 432 and input clocks 106 and outputs status
`outputs 431.
`The output of the input multiplexer is the input clock
`signal provided to the phase detector 414 and to an output
`multiplexer. The phase detector 414 receives the input clock
`signal 106 from the input multiplexer and a feedback signal
`421 from a feedback multiplexer. The phase detector is
`configured to produce a phase error signal 415 indicative of
`the difference between the input clock signal 106 and the
`feedback signal 421. As shown, the phase error signal 415
`comprises an UP pulse and a DOWNpulse, each preferably
`being digital signals. The UP pulse is indicative of a phase
`difference between the feedback signal 421 and the input
`clock signal 106 when an edge of the feedback signal 421
`occurs after a corresponding edge of the input clock signal
`106. ‘The DOWNpulse is indicative of a phase difference
`between the feedback signal 421 and the input clock signal
`106 when an edge of the feedback signal 421 occurs before
`a corresponding edge of the input clock signal 106.
`A loop filter 416 is coupled to receive the phase error
`signal and to output an crror correction signal to a voltage
`controller oscillator (VCO) 418. In a preferred embodiment,
`the loop filter comprises an active low-passfilter configured
`as an integrator. The VCO 418 is coupled to receive the error
`correction signal from the loop filter 416 and to produce
`oscillations indicative of the error correction signal. The
`oscillating signal is presented as a second input to the output
`multiplexer. A PLL enable signal PLL__ENis provided to
`provide either the output of the VCO 418 orthe input clock
`signal 106A, 106B to output 420.
`In the illustrated
`embodiment, the output of the output multiplexer is multi-
`plied or divided in a multiplier/divider circuit 419, such as
`by 1, 2, or 4, to produce one or more PLL output signals 420
`A/B. The feedback signals 421A and 421B are shown
`coupled to the output signals of the PLL 420A/B.
`Exemplary control signals 432, which may be input to the
`switching logic 430, include a resct signal and/or a manual
`override signal. Exemplary status signals 431 that may be
`output by the switching logic 430 include an indication
`signal of which input clock signal is selected and/or an
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`indication signal if either or both input clock signals have
`failed. As an example, the select PLL.300 may be configured
`to use the second input clock 106B uponthe failure of the
`first input clock 106A until the reset signal is received. The
`manual override signal would disable the switching logic
`430 to enable manual selection of the input clock signal
`106A or 106B to use as the local clock reference signal.
`In one embodimentof the redundant clocking system, the
`switching logic 430 determines that the input clock 106A
`has failed and automatically switches over to the redundant
`backup clock 106B. The failover should take only a small
`number of clock cycles, ideally three or fewer. At some
`(preferably short) time following the failover,
`the system
`controller 110 may switch all other select PLLs 300 to the
`redundant backup clock 106B andalso set the slave clock
`source 105B to master mode, if the master clock source
`105A has failed. Clock switching is preferably automatic
`and does not interrupt or interfere with operation of the
`computer system. No halt and restart are necessary. The
`clock change is preferably transparent to the local clock
`loads using the local clock signal.
`It is noted that in various embodiments, the switching
`logic 430 may also be configured to monitor the phase error
`signal 415 or other signals, as desired, in order to detect a
`failure of the input clock signal 106A, 106B or the feedback 2
`signal 421. Likewise, additional control signals 432 and
`status signals 431 are also contemplated. For example, status
`signals 431 may include a clock select signal indicating
`which input clock signal is currently the local master clock
`signal and input clock invalid signals indicating the failure
`of a particular input clock signal. Thus, before a failure, the
`clock selected could be input clock signal 106A and no input
`clock invalid signals are indicated. Upon a failure of input
`clock signal 106A, the clock select signal would indicate
`input clock signal 106B and the input clock invalid signal for
`input clock signal 106A would be indicated.
`FIG. 5—Phase Detector
`Turning now to FIG. 5, an embodiment of the phase
`detector 414 is illustrated. In FIG. 5, the input clock signal
`106 and the feedback signal 421 are provided to phase
`comparison logic 520 of phase detector 414. The phase
`comparison logic 520 provides a signal indicative of the
`phase ditference between the input clock signal 106 and the
`feedback signal 421 to output logic 530. The output logic
`530 further receives the one or more status signals 431 and
`one or more control signals 432. In a preferred embodiment,
`as shown,
`the output
`logic 530 includes a supplemental
`correction pulse gencrator 535 and a pulse width limiting
`circuit 537. The output logic 530 provides the phase error
`signal 415 to the loop filter 416. It is noted that in the
`embodimentillustrated in FIG. 5, the phase error signal 415
`comprises a digital UP signal and a digital DOWNsignal.
`Operation of one embodimentof the phase detector 414 is
`as follows. The input clock signal 106 and the feedback
`signal 421 are provided to the clock inputs of the phase
`comparison logic 520. The phase error signal includes one or
`more digital pulses, UP and/or DOWN,generated based on
`the phase difference betweenthe input clock signal 106 and
`the feedback signal 421. A minimum UP and a minimum
`DOWNpulse may be generated upon a zero phase differ-
`ence. The maximum pulse width for the UP and/or DOWN
`pulse is limited to a predetermined amount by the pulse
`width limiting circuit 537.
`the
`Upon the failure of the input clock signal 106,
`supplemental correction pulse generator 535 is configured to
`output a maximum pulse, either UP or DOWN as
`appropriate, upon receiving notification of a failure of the
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`input clock signal 106 from the present clock source. The
`notification may come from the switching logic 430, the
`system controller 110, and/or the phase detector 414 itself.
`In one embodiment, the supplemental correction pulse gen-
`erator 535 includes a resettable one-shot. Other circuits
`capable of providing a pulse are also contemplated.
`In FIG. 5B, one specific embodiment of phase detector
`414 is shown as phase detector 414B. It is noted that a
`variety of circuits and components may be substituted for
`those shown,as suggested in FIG. 5A. The input clock signal
`106 and the feedback signal 421 are provided to the clock
`inputs of a pair of flip-flops 524A and 5248,respectively,
`which have their data input
`lincs held HIGH. Upon the
`receipt of a respective clock edge, the flip-flops 524A and
`524B each output a logical “1”. The output is maintained at
`logical “1” until both output lines are high. The output lines
`of the flip-flops 524A and 524B are combined bya logical
`AND, with the result provided to the RESET inputs of both
`flip-flops 524A and 524B. Thus, the flip-flops 524A and
`524B reset when both flip-flops 524A and 524B output a
`logical “1”. The outputs of the flip-flops 524A and 524Bare
`provided to logical ANDsonthe output of the phase detector
`414B, both directly and through delay elements 512A and
`512B, respectively.
`The supplemental correction pulse genera