UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`ADVANCED MICRO DEVICES, INC.
`Petitioner
`
`Vv.
`
`AQUILA INNOVATIONS, INC.
`Patent Owner
`
`Case IPR2019-01526
`U.S Patent No. 6,895,519 B2
`
`DECLARATIONOF DAVID H. ALBONESI
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`AMD EX1003
`U.S. Patent No. 6,895,519
`
`

`

`TABLE OF CONTENTS
`
`Il.
`
`TI.
`
`TV.
`
`VI.
`
`Tintroduction.......eeeceeceseceesseeseeceeeeeeeeneeeeeceeeeeacersaeeeaceeaaeceaeeeaeceaeseneeseeaeeeneneees 1
`
`Qualifications 2.2... ..cececccececceseseeccccceeeeceeeecececesseececeeeecseseaesssssaeaeseseeeceeeeneeeeeseeees 2
`
`Materials considered 000.0... cceececeeeseeeseeeeecaeeceteceeeeeeseseeeseeeetestaeeesessaassaeeneees 6
`
`Legal Standards.......ccccceeecccseceeseececeeseeceeeeeeeeeeaeeeeeeaeeeeeeeaaaeseenaeseseesaeeseeaeeeetes 9
`A. My Understanding of Claim Construction... ccc cceecseeneeneeeeteneaeee 9
`B.
`A Person of Ordinary Skill in the Art... cece cseeereeeneeeeeneeeees 9
`C. My Understanding of ODVIOUSNESS...... elec eeeeee ese eeeceeeeeeeeteeeeeeeeees 10
`Level of Ordinary Skill in the Art 200.0... eee ceeeceeceeeeeeeeeneeceeneeseeeteeeeeseees 12
`Backgroundof the Technology ............ccceccceseeceesceceeseeeeseeeeeeeceeeeeeeeeeseaeeenenes 12
`
`AL
`
`ACPD oeieecccceccccsceseseesseseseeseeeseeseeeeseaeeasecsaeeeeeeaaecsseeeecsaaeeeseseeaeenseaaee 13
`
`B.—Fine Grain Microcontroller Clock Control .........cccecsessseceeeeseeeeeeeee 15
`
`VII.
`
`Power Management Libraries Using Cu... eee eceeeeceeeeeeeteeeeeeeeeees 16
`C.
`The 7519 patent occ cc ccccseecsseccseccseeeeeeseeaeeasesaeesecsaaecsseesaeceaaseessceeaeeeeseaee 19
`A.
`Overview of the 7519 Patente ee cccesseessecssessseesseesseeeaescaeeneeraaee 19
`
`B.
`C.
`
`Discussion of the *519 Patent’s Background Section ..... cece 20
`Discussion of the *519 Patent Specification’s Alleged Points of
`NOVEItY. ...ecceeecceseeeceseeeeseeceeaeeceeeeeenseceeaaeceseeeceseeesesaeseeeeecaeeeesaeeeeaeessaees 23
`Overview of Applied References 2.2.2... ..eccceeeeceeeseeeesceeeeeeeseeeeeeceeeeeneesseeeneeseees 25
`
`VII.
`
`Ae
`
`ODO occ ccc ceeeeeteenaeceeeeeeeceneeseeesseeeeasesseeeeeseaecsseseecsaeeseeeseeaseraeaaee 25
`
`B. NaaZatoo. ceeeccccce ccc c ce eececeeeeeeeeeeaaeeseeaeseessesesaesseeeeseasseeseeseeaeeeeaaae 27
`
`C.
`
`D.
`
`Cooper and Windows ACPI... cece eecccecsseceecceseeeeeseeeeeceeeeeeeesnaeeeeaeeees 30
`
`Doba8ec ccccsecsseeeeeccseeeeeesceaeeasessaeessecsaaecsseesaeceaaseasseeeaeeeeneaee 31
`
`IX.
`
`Claim Construction... csccssccssecsseeeeeceseaeeeesseaeesscesaesseeesaecsaasesceeeaeeeeneaee 33
`
`A.
`B.
`
`C.
`
`“system LST? cee ec eeecceseseecesseeseseeeesaecesececesceeeaeessaaeeceaeeeeaeeeeaeeenaees 33
` “aclock control library for controlling a clock frequencytransition
`between said ordinary operation MOdeS”oo... eee eeeeecessceeeeeeteneeeeeeees 34
`“an application program [wherein calling of said clock control
`library and changingof said register value are programmably
`controlled by said application program] to enable user selectable
`clock frequency transitions” ........ec ccc cceeceeeeeeeeeeeeaeceeeeeeeeensaaeennaees 35
`
`-i-
`
`

`

`“principal constituents of said central processing unit”... 35
`D.
`Ground 1: Claims | and 7, 10, 11 - Ober and Nakazato woe eeeeeees 36
`
`X.
`
`A,
`
`Bl
`
`OVOLVICW occ eee ceeececeeceeeseeeeneececeeeceeeesceeceeneeceseeeseacessneeceaeeetaeeeeneectenes 36
`
`Chat 1 eee eeccceeccesseeeesseesesceesececesaaeceeceesssaesseaaeceaeeeeseeseaeeeneaes 39
`
`1.
`
`“A system LST having a plurality of ordinary operation
`modes and a plurality of special modes in response to clock
`frequencies supplied to a central processing unit,
`comprising” [L.P] occ cc ccccsesseeessccseeceseseseceseaeeeescaeeneeseaee 39
`“a first memory that stores a clock control library for
`controlling a clock frequency transition between said
`ordinary operation modes” [1.1] .......c cece ceeeceeeeeeeeeeeeeeeeeees 47
`
`“a system control circuit which has a register, wherein said
`system control circuit carries out the clock frequency
`transition between said ordinary operation modesand said
`special modesin response to a change of a value in said
`register, and also carries out the clock frequency transition
`among said ordinary operation modes in response to said
`clock control library;” [1.2] ........eeeeeeceeeeeeceeececeeeeeseeeeeeneeeeeeees 56
`“a clock generation circuit that receives a plurality of
`standard clocks, wherein said clock generation circuit
`generates a clock supplied to said central processing unit
`according to control by said system control circuit; and”
`[DB] eee cece cee cceeeeeeeeeeeseceaeseseeseaeeeseeseseseeaeeseeeaaessteeeeeseeenes 60
`
`“a second memorythat stores an application program,
`wherein calling of said clock control library and changing of
`said register value are programmably controlled by said
`application program to enable user selectable clock
`frequency transitions,” [1.4] eee eeeeseeceseeeceeeeeeteeeteaeeeseees 62
`“wherein said special modes comprise a first special mode in
`which clock supply to principal constituents of said central
`processing unit is halted, a second special mode in which
`clock supply to an entirety of said central processing unitis
`halted, and a third special mode in which supply of powerto
`the entirety of said central processing unit is halted.” [1.5] .....66
`(a)
`First Special Mode... cece ceeceesseeeeeeeceeeeeeeeeeeaeetees 66
`(b)
`Second Special Mode ......ee eee ecceesseeeeeeceeceeeeeeeeaeetees 67
`
`-l-
`
`

`

`(c)
`
`Third Special Modeo0... eee cece ceseeeesseeceeeeeeeeeeesneeeeeeeeees 70
`
`Cc.
`
`Cain 7 oe cec ccc eecccccccecccccceecccccccecccssccecccececsesecaceeececseeeccusececccececenetesensees 70
`
`1.
`
`2.
`
`3.
`
`“A system LSI as claimed in claim 1, wherein said system
`control circuit comprises: [7.P.] a frequency divisionratio
`setting register that sets a frequency division ratio of the
`clock generated by said clock generation circuit;” [7.1] .......... 70
`
`“a clock halting register that receives the clock from said
`clock generation circuit and individually sets the clock to be
`halted or supplied; and” [7.2]... ..eeeeeeeeseeceeececeeeeeeeeeereeeeesnees 72
`“a status register that judgesa state of said central
`processing unit immediately after being released from said
`third special mode.” [7.3] ......eeeeescceceseeeseeceeeeeceeeeeeteeeteaeeeeseees 74
`
`D.C]atm 10 ccc cceeesseeceeccseeeeeesceaeeasessaeesseesaaecsseesaeceaasesseeeaeeeaseaee 75
`
`1.
`
`“A system LSI as claimed in claim 1, wherein saidfirst
`memory and said second memory are two independent
`memories which are separated from each other.”.......eeeeee 75
`
`B.Catm Lecce ecseecseccseeeeeesceaeeeesaeesecsaaecsseeeaecsaasesseeeaeeeaseaee 77
`
`l.
`
`“A system LSI as claimed in claim 1, wherein saidfirst
`memory and said second memory are formedto coexist in
`one memory, sharing memory area of said one memory.”....... 77
`XI. Ground 2: Claims 2-6 (Ober, Nakazato, Cooper and Windows ACPI)........ 78
`
`A.
`
`B.
`
`C.
`
`D.
`
`OVELVICW .ocecccccsssccssccceccecsssssccccessceucscesessssessesssseeusseseceasssusescsseceeueneseese 78
`
`Claim 2 vicceccecccscsssessscscesccssssssccccessceccsceeesessesesesssseeuvseseeeassseuscsseceeueseseese 84
`
`1.
`
`2.
`
`“A system LSI as claimed in claim 1, wherein said clock
`control library comprises: [2.P] a plurality of libraries that
`control said system control circuit and said clock generation
`circuit to transition the clock frequencies supplied to said
`central processing unit; and” [2.1]... eee eeeeeeeeeeeeeeeereeeeeeeees 85
`“a main library whichis called by said application program
`and selects any one of said libraries in correspondence with
`the clock frequency supplied to said central processing unit.”
`[22] ee eecesecnccecceeeceaecesecseeeaeeeeceaecaeeaeeeceseaecseeeeeeeeeaecaaeeaeeesenaees 88
`
`Claims 3 and 4 once cccccseessecceeceseeeeeesseaeesssesaecseessaecsaesescceeaeeeaseaee 91
`
`Claims 5: ann6... ceccccceccseeeeceeceaeeeesaeeseessessneeesaeceaaseasseeeaeeeaseaee 92
`
`XII. Ground 3: Ober in view of Nakazato and Doblar. wo...ccc eseeeeeeeeeees 94
`
`- ili -
`
`

`

`A.
`
`B.
`
`OVELVICW oie cccecccccccecccccceecccccceecectecceccuceececsesecacsseececseesccceeeeccececennecessnes 94
`
`Claim 8 ooo ceececccececccccceecccccccecccnsececcuccececcececacseeeceucecscccececccccccentecensees 99
`
`1.
`
`2.
`
`“A system LSI as claimed in claim 1, wherein said clock
`generation circuit comprises: [8.P] a PLL that receives a
`plurality of standard clocks and generates the clock if
`needed by multiplying said standard clocks; and”[8.1]........... 99
`
`“a frequency division/selection portion that carries out
`frequency division or selection of said standard clocks or
`said multiplied standard clock. [8.2] ..........eccceesceeeseeeeeeeeeteees 101
`
`CL
`
`CaM Dee eee cence ceseesseceeeeeeeseeeeeasceaeeeseesaaecsaeesaecsaeeeeseseeaeeneees 103
`
`1.
`
`“A system LSI as claimed in claim 8, wherein one ofsaid
`standard clocks uses a frequency of 32.768 kHz as a base
`OSCAatiON.” Lee eecceeeeeeseesteeeeeceneseescceeaeeeeseeeeesssesaacseeeseeenas 103
`
`MTT. Conclusion ......e ee cecscecsseesecseeceseceseeeeceveeeeeeeesaeceaeesacecaeeeaeseeeeeceeeeaeecseeenseenas 105
`
`-jv-
`
`

`

`I, David H. Albonesi, declare as follows:
`
`I.
`
`Introduction
`
`1.
`
`I have been asked by Advanced Micro Devices, Inc. (“AMD”) to
`
`provide expert opinions in the above-captioned Inter Partes Review proceeding
`
`involving U.S. Patent No. 6,895,519 (‘the °519 patent’), whichis entitled “System
`
`LSI.”
`
`2.
`
`This declaration is directed to the Challenged Claims of the *519
`
`patent, and sets forth the opinions I have formed, the conclusions I have reached,
`
`and the bases for each.
`
`3.
`
`Based on my experience, knowledge of the art as of the effective
`
`filing date of the ’519 patent, analysis of prior art references, and the understanding
`
`a person of ordinary skill in the art “‘POSITA”) would have had of the claim terms
`
`in light of the specification as of the effective filing date, it is my opinion that the
`
`Challenged Claims of the *519 patent are unpatentable as being obvious over the
`
`prior art
`
`references discussed below.
`
`In forming my opinions, counsel
`
`for
`
`Petitioner has informed me to assumethe effective filing date of the °519 patent is
`
`February 25, 2002.
`
`4.
`
`I am being compensated by AMD on an hourly basis for the time I
`
`spend in connection with this proceeding. My compensation is not dependent in
`
`any wayon the substance of my opinionsor in the outcomeofthis proceeding.
`
`

`

`II.
`
`Qualifications
`
`5.
`
`A copy of my curriculum vitae is provided as Ex. 1009, which
`
`contains further details on my education, experience, publications, and other
`
`qualifications.
`
`6.
`
`Tam currently a Full Professor of Electrical and Computer
`
`Engineering at Cornell University in Ithaca, New York, where I have been teaching
`
`and performing research in computer architecture since 2004. Between 1996 and
`
`2004, I was an Assistant Professor and then Associate Professor at the University of
`
`Rochester in Rochester, New York where I also taught and performed research in
`
`computer architecture.
`
`7.
`
`My educational background includes a Ph.D. in Computer
`
`Engineering from the University of Massachusetts at Amherst in 1996, an M.S. in
`
`Electrical Engineering from Syracuse University in 1986, and a B.S. 1n Electrical
`
`Engineering from the University of Massachusetts at Amherst in 1982.
`
`8.
`
`I also have ten years of industry experience. Between 1982 and 1986,
`
`I was an Engineer and Senior Associate Engineerin the area of computer memory
`
`system developmentfor International Business Machines (“IBM”). My
`
`responsibilities included computer chip design and verification, board and
`
`backplane bus analysis, and hardware prototype debugging and integration with
`
`other subsystems.
`
`

`

`9.
`
`Between 1986 and 1992, I was a Principal Engineer and Section
`
`Managerin computer processor developmentat Prime Computer, Inc. My
`
`responsibilities included project manager and computer architect for high
`
`performance multi-processor system bus, cache, main memory, Input/Output, and
`
`system managerdesigns.
`
`10.
`
`I received three Excellence Awards, a Patent Plateau Award, and four
`
`U.S. patents during my development of industry products.
`
`11.
`
`|My academicresearch is in computer systems architecture, and has
`
`resulted in eight U.S. patents and over eighty publications.
`
`12.
`
`[have been elected Fellow of the Institute of Electrical and Electronic
`
`Engineers (“IEEE”) and am a memberof the International Symposium on
`
`Microarchitecture Hall of Fame. I am a three time recipient of the IBM Faculty
`
`Award, have been honored with the IEEE Micro Top Picks in Computer
`
`Architecture Award three times, and have received the National Science Foundation
`
`CAREER Award. At Cornell, I received the Kenneth A. Goldman ’71, Michael
`
`Tien ’72 and Ralph S. Watts ’72 College of Engineering Excellence in Teaching
`
`Awards, and the Ruth and Joel Spira Award for Excellence in Teaching in
`
`Electrical and Computer Engineering (twice). I am also a recipient of the IEEE
`
`Computer Society Golden Core Award.
`
`

`

`13.
`
`From 2006-2010, I was Editor-in-Chief of IEEE Micro, the premier
`
`publication of the top worldwide computer engineering professional society that
`
`showcases industry computer systems and leading edge research. I currently serve
`
`on the Advisory Board of IEEE Micro and on the Editorial Board of IEEE
`
`Computer. I have been General Chair and Program Committee Chair of top
`
`computer architecture conferences (for instance, I was co-General Chair of the
`
`International Symposium on Microarchitecture in 2009, and Program Chair of the
`
`International Symposium on Computer Architecture in 2015); I recently served on
`
`the IEEE Harry S. Goode and IEEE/ACM Eckert-Mauchley Award Committees
`
`and the IEEE Computer Society Fellows Evaluation Committee; I have served on
`
`numerous Program Committees of the leading computer architecture conferences
`
`and workshops; and IJ have organized tutorials and workshops for practicing
`
`professionals and researchers in computer architecture. I have served as a proposal
`
`review panelist for many programs at the National Science Foundation and a
`
`reviewer for the California MICRO program.
`
`14.
`
`In 2009, I was invited to teach a course on computer systems design
`
`as related to power managementandreliability at the ACACES European Summer
`
`School. Ph.D. students, professors, and industry engineers from throughout Europe
`
`attended the course.
`
`

`

`15.
`
`[have significant industry and academic experiencethatis directly
`
`related to the subject area of the °519 patent. In my industry work, I developed
`
`complex computer systems that incorporated multiple Application Specific
`
`Integrated Circuit (ASIC) chips.
`
`16.
`
`Specifically, as noted above, at IBM, I was a computer engineer
`
`working on the design of high performance systems related to IBM’s mainframe
`
`computers. One of my responsibilities included ASIC design for IBM memory
`
`systems. As a lead architect and manager at Prime Computer, I developed high
`
`performance memory system and I/O system architectures that incorporated
`
`multiple ASIC designs.
`
`17.
`
`The primary focus of my research is computer systems power
`
`management. In particular, my work involves dynamically adapting the system
`
`architecture to meet performance demands. This involves dynamic frequency and
`
`voltage scaling, and dynamically shutting down portions of the system when they
`
`are not being used. I have tens of publications and nine issued U.S. patents related
`
`to this research.
`
`18.
`
`For example, my book chapter “Power-Efficient Issue Queue Design,”
`
`which appeared as chapter 3 in the book Power Aware Computing by Kluwer
`
`Academic Publishers
`
`in 2002, discusses
`
`saving processor core power by
`
`

`

`dynamically shutting down portions of the issue queue hardware. This was one of
`
`several papers related to this research, and resulted in a U.S. patent.
`
`19. Another example is my paper “Energy Efficient Processor Design
`
`Using Multiple Clock Domains with Dynamic Frequency and Voltage Scaling,”
`
`which appeared in the International Symposium on High Performance Computer
`
`Architecture in February 2002. This research proposes processor cores that have
`
`multiple clock domains, for which the clock frequency and voltage are individually
`
`controllable. My research in this area led to several additional publications and two
`
`U.S. patents.
`
`20. At Cornell, I teach an advanced graduate course for Master’s and
`
`Ph.D.
`
`students on computer
`
`systems architecture. The course covers
`
`the
`
`architecture of the caches, main memories, and storage systems found within
`
`commercial products, in addition to advancedresearchin thefield.
`
`21. Altogether,
`
`I have more than 35 years of experience developing
`
`products and conducting research in the area of computer systems architecture,
`
`computer chip design, and power-efficient hardware design.
`
`Ill. Materials considered
`
`22.
`
`In formulating my opinions,
`
`I have relied upon my training,
`
`knowledge, and experience that are relevant to the 519 patent. Furthermore, I have
`
`

`

`considered specifically the following documents listed below in addition to any
`
`other documents cited in this declaration:
`
`
`Description
`Exhibit
`
`
`
`
`1001 U.S. Patent No. 6,895,519 B2 to Endo (“the 519 patent’)
`
`1002
`
`
`
`
`
` 3, 2019). (“Preliminary Infringement Contentions”)
`
`
`
`File history of U.S. Patent No. 6,895,519 B2 to Endo (519 file
`history”)
`1004 U.S. Patent No. 6,665,802 to Ober (“Ober”)
`“Draft ACPI Driver Interface Design Notes and Reference,”
`Microsoft Hardware White Paper, Microsoft Corporation, 1998
`
`(“Windows APCT’)
`1006 U.S. Patent No. 6,516,422 to Doblar et al. (‘Doblar’’)
`
`1005
`
`
`
`1007
`
`U.S. Patent No. 6,823,516 to Cooper (‘Cooper’)
`
`
`
`1008
`
`U.S. Patent No. 6,681,336 to Nakazatoet al. (“Nakazato’’)
`
`
`
`1009
`Curriculum vitae of Dr. David Albonesi
`
`
`McDaniel, G., /BM Dictionary of Computing, McGraw-Hill, 10th
`1010
`ed., (1993) (“IBM Dictionary”)
`“Aquila Innovations, Inc.’s Claim Construction Brief,” Aquila
`Innovations, Inc. v. Advanced Micro Devices, Inc., Case No. 1:18-
`cv-00554-LY (W.D. Tex.) (filed July 2, 2019). (“Claim
`Construction Brief’)
`‘Aquila Innovations, Inc.’s Preliminary Infringement
`Contentions,” Aguila Innovations, Inc. v. Advanced Micro
`Devices, Inc., Case No. 1:18-cv-00554-LY (W.D. Tex.) (filed Feb.
`
`1011
`
`1012
`
`1013
`
`Compaq Computer Corporation et al., “Advanced Configuration
`and PowerInterface Specification, Revision 2.0” (July 27,2000)
`(“ACPIspec’)
`
`

`

`
`
`
`
`
`
`1025
`
`1026
`
`U.S. Patent No. 5,260,979 to Parkeret al. (“the 979 patent)
`
`U.S. Patent No. 5,530,726 to Toshiaki Ohno(“the ’726 patent)
`
`
`
`
`
`Exhibit
`
`Description
`
`
`
`1014 U.S. Patent No. 5,952,890 to Fallisgaard ef al. (Fallisgaard)
`1015
`Intel Pentium IIT Processor/840 Developer Kit Manual (April
`
`2001) (“Intel Pentium IT Manual’’)
`
`TMS320C55x DSP Functional Overview June 2000) (°TMS
`1016
`
`Overview’)
`ST7 8-Bit MCU Family User Guide (July 2002)(“ST7 User Guide)
`
`
`
`1017
`
`1018
`
`U.S. Patent No. 7,155,617 B2 to Gary et al. (“the ’617 patent”)
`
`
`
`1019
`Microsoft Computer Dictionary, Microsoft Press, 5th ed.,
`(2002)(“Microsoft Dictionary)
`
`
`1020
`
`MICROSOFT.COM, OnNow and Power Management (“OnNow’”’)
`
`
`
`1021 Affidavit of Christopher Butler
`1022
`Olukotunet al., The Case for a Single-Chip Multiprocessor
`
`(1996).
`
`1023
`Albonesiet al., Tradeoffs in the Design ofSingle Chip
`Multiprocessors (1994)
`
`Bossenet al, Power4 Systems: Designfor Reliability (2001)
`
`
`
`1024
`
`Trevor Mudge, “Power: A First-Class Architectural Design
`1027
`Constraint,” TEEE Computer, April 2001
`
`
`
`

`

`23.
`
`Ihave also relied upon various legal principles (as explained to me by
`
`AMD’s counsel) in formulating my opinions. My understanding of these principles
`
`are summarized below.
`
`IV. Legal Standards
`
`A. My Understanding of Claim Construction
`
`24.
`
`I understand that during an inter partes review proceeding, claims are
`
`to be construed in light of the specification as would be read by a person of
`
`ordinary skill in the relevant art “‘POSITA”) at the time the application wasfiled.I
`
`understand that claim terms are given their ordinary and customary meaning as
`
`would be understood by a POSITA in the context of the entire disclosure.
`
`B.
`
`A Person of Ordinary Skill in the Art
`
`25.
`
`I understand that a POSITA is presumed to be aware ofall pertinent
`
`art,
`
`thinks along conventional wisdom in the art, and is a person of ordinary
`
`creativity—not an automaton.
`
`26.
`
`I have been asked to consider the level of ordinary skill in the field
`
`that someone would have had at the time the claimed invention was made. In
`
`deciding the level of ordinary skill, I considered the following:
`
`e
`
`the levels of education and experience of persons working in the
`
`field;
`
`e
`
`the types of problems encountered in the field; and
`
`

`

`e
`
`the sophistication of the technology.
`
`27. My opinion below explains how a POSITA would have understood
`
`the technology described in the references I have identified herein.
`
`28.
`
`Regardless if I use “I” or a “POSITA” during my technical analysis
`
`below, all of my statements and opinions are always to be understood to be based
`
`on how a POSITA would have understood or read a document at the time of the
`
`invention.
`
`C. My Understanding of Obviousness
`
`29.
`
`I have been advised and understand that a claimed invention is
`
`unpatentable if the differences between the invention and the prior art are such that
`
`the subject matter as a whole would have been obvious at the time the invention
`
`was made to a POSITA to which the subject matter pertains. This means that even
`
`if all of the requirements of the claim cannot be found in a single prior art
`
`reference that would anticipate the claim, the claim canstill be invalid.
`
`30.
`
`It is my understanding that obviousness is a question of law based on
`
`underlying factual findings: (1) the scope and content of the prior art; (2) the
`
`differences between the claims and thepriorart; (3) the level of skill in the art; and
`
`(4) objective considerations of nonobviousness.
`
`I understand that for a single
`
`reference or a combination of references to render the claimed invention obvious, a
`
`-10-
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`

`

`POSITA must have been able to arrive at the claims by altering or combining the
`
`applied references.
`
`31.
`
`I also understand that prior art references can be combined under
`
`several different circumstances. For example, it is my understanding that one such
`
`circumstance is when a proposed combination of prior art references results in a
`
`system that represents a predictable variation, which is achieved using prior art
`
`elements according to their established functions.
`
`32.
`
`J also understand that when considering the obviousness of a patent
`
`claim, one should consider whether a teaching, suggestion, or motivation to
`
`combine the references exists so as to avoid impermissibly applying hindsight
`
`when considering the prior art. I understand this test should not be rigidly applied,
`
`but that the test can be important to avoiding such hindsight.
`
`33.
`
`Further, I understand that certain objective indicia can be important
`
`evidence regarding whether a patent is obvious or nonobvious. Such indicia
`
`include: commercial success of products covered by the patent claims; a long-felt
`
`need for the invention; failed attempts by others to make the invention; copying of
`
`the invention by others in the field; unexpected results achieved by the invention as
`
`compared to the closest prior art; praise of the invention by the infringer or others
`
`in the field;
`
`the taking of licenses under the patent by others; expressions of
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`-I1-
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`

`

`surprise by experts and those skilled in the art at the making of the invention; and
`
`the patentee proceeded contrary to the accepted wisdom ofthepriorart.
`
`34.
`
`Myanalysis below is always from the perspective of a POSITA unless
`
`otherwise noted, even if that is not explicitly stated. My analysis of the prior art is
`
`always madeasofthe time the alleged invention was made from the perspective of
`
`a POSITA.
`
`V.
`
`‘Level of Ordinary Skill in the Art
`
`35.
`
`J have been advised and understand that a POSITA is presumed to be
`
`aware of all pertinent art, thinks along conventional wisdom in theart, and is a
`
`person of ordinary creativity, not an automaton. With this understanding, a
`
`POSITA in the context of the °519 patent as of February 25, 2002 (the earliest
`
`priority date of the *519 patent), would have a B.S. degree in Electrical
`
`Engineering, Computer Engineering, or an equivalent field as well as at least 3 to 5
`
`years of academic or industry experience in computer systems architecture or
`
`computer chip design, or comparable industry experience. As my educational and
`
`technical background demonstrates, I am well-qualified to determine the level of
`
`ordinary skill in theart.
`
`VI. Background of the Technology
`
`36. Having reviewed the ’519 patent, I have identified a few technological
`
`concepts therein that the 519 patent seems to claim as its own. I provide below a
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`-12-
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`

`history of these technological concepts in the time period leading up to the *519
`
`patent.
`
`37.
`
`For the decades leading up to the mid-1990s, the sole objective of the
`
`computer system hardware designer was to maximize application performance
`
`within die area constraints. During that
`
`time,
`
`the semiconductor technology
`
`supported, by today’s standards, modest clock frequencies and levels of chip
`
`integration. As a result, power consumption was at acceptable levels from the
`
`standpoint of heat and battery life.
`
`38.
`
`By the mid-1990s, the technology supported higher clock frequencies
`
`and levels of integration that caused power to begin rising to levels that could no
`
`longer be tolerated in terms of heat and battery life. By the late 1990s,
`
`the
`
`computer industry reached a breaking point where power could no longer be
`
`ignored. For computer hardware and software designers, power became a “first
`
`class design constraint” that necessitated a fundamental change from a pure
`
`performance centric approach EX1027.
`
`A.
`
`ACPI
`
`39.
`
`This new focus on power created a need for an open standard for
`
`power management, similar to the open standards for disk drives (such as SATA)
`
`and buses (such as PCI) that create interoperability for hardware and software
`
`-13-
`
`

`

`designers. This led to the creation of the Advanced Configuration and Power
`
`Interface (ACPI) standard by Intel, Microsoft, and Toshiba in 1996.
`
`40. ACPI permits operating systems to manage powerin conjunction with
`
`the hardware throughthe specification of standard interfaces between the hardware
`
`and software. These interfaces permit
`
`the operating system to delineate the
`
`capabilities of the system (e.g., the range of frequencies available in the processor
`
`and the effects of a frequency change) and to manage the system power(e.g., by
`
`writing a code into a frequency register to affect a change). These standard
`
`interfaces enable inoperability between ACPI compliant hardware and operating
`
`systems. ACPI also includes a special language (ACPI Source Language or ASL)
`
`for developers to create ACPI code.
`
`41. With power consumption reaching a breaking pointin the late 1990s,
`
`and version 2.0 of the ACPI standard released in 2000, ACPI became well-known
`
`within the industry as the standard for power management hardware and operating
`
`system design. For example, Microsoft
`
`included ACPI support starting with
`
`Windows 98. Intel began supporting ACPI in the Intel Pentium III processor
`
`EX1015, Intel Pentium I Manual, 3-10-11.
`
`42.
`
`For processor control, the ACPI specification defines specific states
`
`that indicate the current operational status of the processor. The COstate is defined
`
`as the working state of the processor where it executes instructions. Within the CO
`
`-14-
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`

`

`state are various P states (PO-Pn). The PO state is the highest performancestate,
`
`whereasin the P1-Pn states the processor executes instructions but performanceis
`
`degraded and poweris reduced (the most in Pn). The Cl-Cn states are defined as
`
`sleep states where the processor does not execute instructions. The Cl state
`
`requires the shortest time to return to the operating state, but the powersavingsis
`
`the smallest. The C2-Cnstates require progressively more recovery time but higher
`
`powersavings. The operating system affects a processor state change—andthusits
`
`performance level and power consumption—by writing ACPI specific processor
`
`registers.
`
`43.
`
`“Draft ACPI Driver
`
`Interface Design Notes
`
`and Reference”
`
`(“Windows ACPI’) is a whitepaper published by Microsoft. At the time of the
`
`invention, the Windows operating system was the most popular among all those
`
`available at
`
`that
`
`time. And thus, a POSITA or the interested public seeking
`
`information on how to integrate power management—suchasdisclosed in the *519
`
`patent, Ober, Nakazato, Cooper, or Doblar—with the Windows operating system
`
`would have known to look at the hardware development section the Microsoft.com
`
`website.
`
`B.
`
`Fine Grain Microcontroller Clock Control
`
`44. Due
`
`to the well-known quadratic
`
`(V°f)
`
`relationship between
`
`frequency, voltage, and dynamic power, system designers initially focused on
`
`-15-
`
`

`

`techniques
`
`that
`
`turned off
`
`(gated)
`
`the
`
`clock, or
`
`reduced its
`
`frequency.
`
`Desktop/laptop systems with a single high performance Central Processing Unit
`
`(CPU) chip, such as the aforementioned Intel Pentium III, only required that a
`
`single system clock be gated or scaled. Highly integrated microcontrollers that
`
`combine a less powerful CPU with other logic, such as on-chip peripherals, on a
`
`single chip, typically include multiple clocks for the CPU and otherlogic.
`
`45.
`
`In the late 1990s, developers of these systems had incorporated fine-
`
`grain clock control through separate clock domains, in which clocks to the CPU
`
`and logic could be individually gated through software. This approach provided
`
`more flexibility in terms of power control. For example, a processor could be clock
`
`gated when idle while peripherals remained active to receive requests, or a
`
`peripheral that has seen little activity could be clock gated while the CPU executed
`
`instructions. As
`
`one
`
`example of
`
`this
`
`approach,
`
`the Texas
`
`Instruments
`
`TMS320C55x included an Idle Control Register (CR) that permitted software to
`
`individually gate the clocks to the CPU, DMA, peripherals, clock generator,
`
`instruction cache, and external memory interface domains. EX1016, TMS
`
`Overview, 2-8.
`
`C.
`
`Power Management Libraries Using C
`
`46. At the time of the priority date of the ’519 patent, the C programming
`
`language was a popular choice for developing systems code for microcontrollers.
`
`-16-
`
`

`

`For example,
`
`the developers of the ST Microelectronics ST7 microcontroller
`
`referenced in the backgroundsection of the °519 patent promoted the use of C for
`
`system development: “Today, one language that prevails in microcontroller
`
`programming,
`
`that
`
`is C language.” EX1017, STF User Guide,
`
`55. As
`
`microcontrollers integrated power management functions, C became a natural
`
`choice for developing power managementlibraries.
`
`47.
`
`Texas Instruments is one example of a company that developed power
`
`management libraries in the C language for their TMS320C55x line of Digital
`
`Signal Processors (DSPs) around the time of the °519 patent. US Patent 7,155,617
`
`B2, filed as a provisional application on August 1, 2002, is entitled Methods and
`
`Systems for Performing Power Management Via Frequency and Voltage Scaling.
`
`As mentioned in the Field of the Invention, the invention “generally relates to
`
`software developmentsystems, and more specifically to improvements in software
`
`support for power management in systems and applications.” EX1018, ’617 patent,
`
`1:16-18. One embodiment of the invention includes “a memory storing a power
`
`scaling library executable to enable any entity of the digital system [to] change the
`
`frequency and voltage of the digital system.” /d., 7:62-65.
`
`-|7-
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`

`

`
`CONTROL
`APPLICATION
`
`
`APPLICATION
`
`THREAD
`
`
`
`
` POWER
`MANAGER
`(PWRM)
`
`
`
`1008Spaiver|cae
`
`wooedmd GT
`
`EX1018, FIG. 1
`
`48.
`
`The embodiment of Figure | shows a power management module
`
`(PWRM) 1000 that “provides a set of application program interfaces (APIs) that
`
`execute in the context of application control threads and device drivers.” EX1018,
`
`9:32-34. The PWRM permits application level control of idling of clock domains,
`
`id., 10:9-15, dynamic frequency and voltage scaling,
`
`id., 10:20-39, and sleep
`
`modes, id., 10:40-43. The Power Scaling Library (PSL) 1008 within the PWRM
`
`“logically isolates PWRM 1000 and the rest of the application from the low-level
`
`implementation details of the frequency and voltage control hardware.” /d., 9:64-
`
`67