UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________
`
`ADVANCED MICRO DEVICES, INC.
`Petitioner
`
`v.
`
`AQUILA INNOVATIONS INC.,
`Patent Owner
`
`_____________________
`
`Case IPR2019-01526
`Patent 6,895,519
`_____________________
`
`DECLARATION OF DAVID H. ALBONESI IN SUPPORT OF
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`AMD EX1028
`AMD v. Aquila
`IPR2019-01526
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`
`TABLE OF CONTENTS
`
`I.
`II.
`III.
`
`B.
`
`C.
`D.
`
`Introduction ...................................................................................................... 1
`Overview of Patent Owner Response .............................................................. 3
`The references disclose the alleged missing elements. ................................... 4
`A.
`Ground 1: Ober in View of Nakazato ................................................... 4
`1.
`Ober in view of Nakazato discloses a “plurality of ordinary
`operation modes.” ....................................................................... 4
`(a)
`It would have been obvious to a POSITA to reduce
`the CPU clock frequency of Ober during “ordinary
`operations.” ....................................................................... 7
`(b) Ober’s CPU is capable of operating at reduced clock
`speeds. ............................................................................. 11
`Ober in view of Nakazato discloses “a first memory that
`stores a clock control library for controlling a clock
`frequency transition between said ordinary operation
`modes.” ..................................................................................... 13
`A POSITA would have been motivated to combine Ober and
`Nakazato, and would have had a reasonable expectation of
`success. ...................................................................................... 18
`(a)
`Ober is not limited to decentralized power
`management. ................................................................... 19
`(b) Modifying Ober as proposed would have been well
`within the abilities of a person of ordinary skill in the
`art. ................................................................................... 21
`A POSITA would have had a reasonable expectation of
`success modifying the unused bits of Ober’s SFR 62. ............. 23
`Ground 2: Ober in view of Nakazato, Cooper and Windows ACPI ... 25
`1.
`A POSITA would have been motivated to combine Ober
`with Windows ACPI. ................................................................ 25
`A POSITA would have found EX1005. ................................... 26
`2.
`Ground 3: Ober in view of Nakazato and Doblar ............................... 32
`The Dependent Claims are Unpatentable for the Reasons Set Forth
`in My Previous Declaration. ................................................................ 33
`
`2.
`
`3.
`
`4.
`
`- i -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`IV. Conclusion ..................................................................................................... 34
`
`
`
`- ii -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`
`I, David H. Albonesi, declare as follows:
`
`I.
`
`Introduction
`I have been asked by Advanced Micro Devices, Inc. (“AMD”) to
`1.
`
`provide expert opinions in the above-captioned inter partes review proceeding
`
`involving U.S. Patent No. 6,895,519 (“the ’519 patent”), which is entitled “System
`
`LSI.”
`
`2.
`
`Specifically, I have been retained as a technical expert by AMD to
`
`study and provide my opinions on the technology claimed in, and the patentability
`
`or unpatentability of, claims 1-11 of the ’519 patent (“the Challenged Claims”).
`
`For purposes of this declaration, I was not asked to provide any opinions that are
`
`not expressed herein.
`
`3.
`
`I previously submitted a declaration in support of the Petition for inter
`
`partes review of the ’519 patent. This declaration is in support of Petitioner’s
`
`Reply to Patent Owner’s Response in IPR2019-01526.
`
`4.
`
`I understand that Patent Owner submitted a Response (Paper 19)
`
`(“POR”) and the declaration of Steven A. Przybylski in support of the POR
`
`(EX2005). I have also been asked to provide my technical review, analysis, and
`
`insight regarding both the POR and Mr. Przybylski’s declaration in support
`
`thereof.
`
`- 1 -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`5. My background and qualifications were provided in paragraphs 5-21
`
`of my original declaration, Exhibit 1003, and my CV was provided as Exhibit
`
`1009. My statements in my original declaration regarding my review of the ’519
`
`patent and related materials remain unchanged. In reaching my opinions, I
`
`carefully reviewed Patent Owner’s Response, the Petition for inter partes review
`
`of the ’519 patent, my original declaration, and the materials reviewed as part of
`
`my original declaration. In addition, I reviewed and refer to the following
`
`materials:
`
`Exhibit
`1029
`
`1030
`
`1031
`
`1032
`
`6.
`
`7.
`
`
`
`Description
`Deposition Transcript of Dr. Steven A. Przybylski, August 14,
`2020.
`Internet Archive capture of http://www.microsoft.com, June 10,
`2001 (accessed August 27, 2020).
`Internet Archive capture of
`http://www.microsoft.com/windows/default.asp, June 9, 2001
`(accessed August 27, 2020).
`Internet Archive capture of http://www.microsoft.com/HWDev/,
`June 11, 2001 (accessed August 27, 2020).
`
`I have also reviewed all other materials cited herein.
`
`I have also relied upon various legal principles (as explained to me by
`
`AMD’s counsel) in formulating my opinions. My understanding of these principles
`
`was summarized in my original declaration and remain unchanged for the purposes
`
`of this declaration.
`
`- 2 -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`I am being compensated by AMD at my standard hourly rate of $500
`
`8.
`
`dollars per hour for the time I spend in connection with this proceeding. My
`
`compensation is not dependent in any way on the substance of my opinions or in
`
`the outcome of this proceeding.
`
`9.
`
`In his declaration, Mr. Przybylski makes several statements regarding
`
`the ’519 patent, the prior art references, and the relevant technology at issue in this
`
`proceeding, which I believe to be inaccurate and misleading. My responses to these
`
`statements are detailed below.
`
`II. Overview of Patent Owner Response
`10. Based on my review, it is my opinion that Patent Owner has not
`
`rebutted AMD’s showing that the challenged claims of the ’519 patent are
`
`unpatentable.
`
`11. Patent Owner’s primary argument is that the references fail to disclose
`
`the claimed “plurality of ordinary operation modes” because Ober only explicitly
`
`discloses multiple clock frequencies being provided to the subsystems during
`
`normal mode. Patent Owner also argues that Ober’s unused bits could not be
`
`modified to support multiple RUN mode frequencies. But these arguments fail to
`
`account for the knowledge and skills of a POSITA.
`
`12. Patent Owner also argues that the references fail to disclose the
`
`claimed “first memory storing a clock control library for controlling clock
`
`- 3 -
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`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`frequency transitions between said ordinary operation modes,” arguing that Ober’s
`
`unused bits could not be modified based on Nakazato. This, again, ignores the
`
`abilities and knowledge of a POSITA.
`
`13. Finally, Patent Owner argues that a POSITA would not have been
`
`motivated to combine Ober with Nakazato, Ober with Windows ACPI, and Ober
`
`with Doblar.
`
`14. As I discuss in detail below, I disagree with these arguments for
`
`multiple reasons. First, I believe that the Patent Owner repeatedly ignores the skills
`
`and knowledge of a POSITA. Second, it is my opinion that the references disclose
`
`or otherwise teach these limitations, and that the original combinations of
`
`references still render the claims obvious for substantially the same reasons as
`
`discussed in my original declaration. Based on my review, even if interpreted in
`
`the manner proposed by Patent Owner, the art still discloses and/or teaches the
`
`claims.
`
`III. The references disclose the alleged missing elements.
`A. Ground 1: Ober in View of Nakazato
`1. Ober in view of Nakazato discloses a “plurality of ordinary
`operation modes.”
`In my opinion, the combination of Ober and Nakazato discloses the
`
`15.
`
`claimed “plurality of ordinary operation modes.” In particular, as I explained in my
`
`previous declaration, Ober discloses that a variety of clock are divided, including
`
`- 4 -
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`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`during “normal mode” (e.g., ordinary operation). EX1003, ¶¶87-88. As a result of
`
`these teachings, I explained that it would have been obvious to “a POSITA for the
`
`clock to be adjusted during ‘normal mode’ similarly to how it is adjusted during
`
`‘SLEEP mode….’” Id., ¶88.
`
`16. As I stated, “Ober does not explicitly describe how [this occurs]
`
`during ‘normal mode.’” Id. But this is where Nakazato applies—“Nakazato
`
`discloses a ‘CPU speed control circuit 152’ that ‘controls the processing speed of
`
`the CPU 11, and has a throttling controller for switching the CPU speed.” Pet, 17
`
`(citing EX1008, 5:44-49). Nakazato further explains that these CPU frequency
`
`changes occur during an ordinary operation mode of the computer: “the power-
`
`saving driver waits for a predetermined period until user operation to a computer
`
`system is enabled, and then sets the processing speed of the CPU to a user-
`
`designated speed.” EX1008, Abstract (emphasis added).
`
`17.
`
`In my opinion, a POSITA would have been motivated to combine
`
`Ober and Nakazato because they each “explicitly relate to managing the power of
`
`computing system.” EX1003, ¶91. Moreover, the CPU is one of the largest power
`
`consumers in any computing system, especially for systems on a chip, such as
`
`those described in Ober. And as acknowledged by Ober and Dr. Przybylski, it was
`
`well-known that reducing the clock frequency of a CPU was one method of
`
`reducing its power consumption. EX1004, 2:17-20;EX1029, 54:20-55:2, 62:8-
`
`- 5 -
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`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`63:5. This would have further motivated a POSITA to reduce the speed of the CPU
`
`during “normal mode” of a computer operations to achieve even greater power
`
`savings.
`
`18.
`
`Patent Owner appears to focus its arguments on Ober alone.
`
`Specifically, Patent Owner argues that Ober does not disclose the claimed
`
`“ordinary operation modes” because: (1) to the extent Ober discusses dividing
`
`clocks during “normal mode,” it is allegedly limited to only Ober’s subsystems,
`
`not the CPU core; and (2) Ober’s system allegedly cannot divide the CPU clock
`
`either during “sleep mode” or “normal mode.” POR, 28-29. I believe this analysis
`
`is incorrect. As I set forth in my previous declaration, I rely on the combination of
`
`Ober and Nakazato to disclose this limitation. Yet Patent Owner ignores
`
`Nakazato’s explicit teachings regarding reducing CPU clock frequency during
`
`“ordinary operations.” It is my opinion that the teachings of Nakazato cannot be
`
`disregarded, as they clearly demonstrate both a motivation and ability to operate a
`
`CPU and its core at different frequencies during normal operations of a computer.
`
`19.
`
`Specifically, Nakazato describes a “CPU speed control circuit 152,”
`
`which can vary the CPU speed by simply changing the value in a register. EX1008,
`
`6:19-21. Nakazato further discloses that this occurs during the ordinary operation
`
`mode of a computer by way of a computer utility, which Nakazato illustrates in
`
`Figure 2. EX1008, Abstract.
`
`- 6 -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`
`
`
`EX1008, FIG. 2.
`
`I repeatedly cited to these teachings in my original declaration. See, e.g., EX1003,
`
`¶¶88-89. Therefore, it is my opinion that the combination of references render this
`
`obvious. And as I explain further below, Patent Owner’s arguments also
`
`mischaracterize the teachings of Ober and the positions set forth in the Petition.
`
`(a)
`
`It would have been obvious to a POSITA to reduce
`the CPU clock frequency of Ober during “ordinary
`operations.”
`20. Patent Owner first argues that the divided clock programmed by SFR
`
`register 116 is only available to Ober’s “subsystems 30-40” during “normal mode,”
`
`not Ober’s core 22, and thus it would not have been obvious to modify the
`
`frequency of the clock of Ober’s core 22. POR, 29-31. But this argument misses
`
`important teachings in Ober. Specifically, in my previous declaration, I discussed a
`
`different register—register 62. Ober explains that “register 62” includes a field
`
`- 7 -
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`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`“SLPCLK,” that “is used to program ‘the frequency of the system clock during a
`
`sleep mode of operation.’” Pet, 33 (citing EX1004, 11:31-33). Dr. Przybylski
`
`appears to agree with me that a POSITA would understand that the CPU core clock
`
`is necessarily adjusted when the system clock is adjusted. EX1029, 90:9-16 (“If
`
`you divide the system clock during run mode that would affect the frequency of the
`
`core and the execution of instructions.”). This is because, as shown below in
`
`annotated Figure 1 from Ober, there is only a single system clock for Ober that is
`
`the input clock for every subsystem and peripheral of Ober, including the CPU
`
`core 22:
`
`EX1004, FIG. 1 (annotated).
`
`
`
`21. Accordingly, by dividing the system clock, one necessarily divides the
`
`input clock for all of Ober subsystems, which would likewise result in a divide
`
`- 8 -
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`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`CPU clock frequency being used by the core 22 for executing instructions. This is
`
`why I previously explained that it is register 62 that would be modified using the
`
`teachings of Nakazato to adjust the CPU core clock: “[T]here are at least six
`
`available bits in the SFR register. This would have been more than sufficient for
`
`configuring the clock division during normal operation mode.” EX1003, ¶126.
`
`22. Therefore, although Ober describes that “a divided clock” may be
`
`provided to “subsystem[s]” during “normal mode[],” it’s irrelevant to my analysis
`
`whether those “subsystems” are described as including Ober’s CPU core or not.
`
`Rather, I merely cited this explanation because the fact that Ober describes
`
`supplying a divided clock to the subsystems, this would have suggested to a
`
`POSITA that such a divided clock can also be supplied to Ober’s core 22. EX1003,
`
`¶¶110-112. My citation to register 62 and Ober’s system clock merely explain one
`
`manner in which such a divided clock can be supplied to Ober’s CPU.
`
`23. But even if one were to assume that Ober’s explanation of dividing
`
`clocks is somehow limited to Ober’s “subsystems 30-40,” as Patent Owner
`
`contends, Patent Owner’s theory is still incorrect because it ignores what I
`
`contended was Ober’s CPU. As shown below in annotated Figure 1 from my
`
`previous declaration, I explained that Ober’s CPU includes not only core 22, but
`
`also FPIs 42-52:
`
`- 9 -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`
`
`
`EX1003, ¶97. Patent Owner does not challenge my interpretation of Ober’s CPU.
`
`And according to Ober, “each of the subsystems 30-40 include a FPI peripheral
`
`interface 42-52.” EX1004, 7:36-41 (emphasis added). Thus, even assuming POs
`
`arguments that dividing the clock during “normal mode” is limited to “subsystems
`
`30-40,” since FPIs 42-52 are part of those subsystems, their clocks are also divided
`
`during “normal mode.” It seems, therefore, that by acknowledging that Ober’s
`
`“subsystems 30-40” can have their clocks adjusted during “normal mode,” Patent
`
`Owner agrees that Ober’s CPU, as I previously identified it, also has a divided
`
`clock during “normal mode” because FPIs 42-52 are part of the CPU. When these
`
`adjustments occur, this would result in the FPIs, which are part of the CPU,
`
`- 10 -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`operating at a lower clock frequency at a time when the core 22 is carrying out
`
`instructions (e.g., normal mode).
`
`(b) Ober’s CPU is capable of operating at reduced clock
`speeds.
`24. Patent Owner next argues that Ober’s CPU is incapable of executing
`
`instructions at different clock speeds because Ober allegedly only describes
`
`operating at a single frequency during its “RUN mode,” which Patent Owner
`
`equates to an “ordinary operation mode.” Patent Owner appears to rely primarily
`
`on a disclosure from Ober that states that during its “RUN” state, a variable named
`
`“Low Speed Clocks” is set to “False.” Patent Owner equates “Low Speed Clocks”
`
`to a reduced system clock speed. POR, 32-33. Patent Owner further argues with
`
`respect to Ober’s Table 7 that “RUN mode only runs on one frequency.” Id., 34.
`
`First, I note that Ober never suggests that “Low Speed Clocks” is equivalent to a
`
`reduced system clock. Additionally, Patent Owner’s analysis appears solely
`
`focused on Ober, whereas I relied on the combination of Ober and Nakazato. As I
`
`explained above, I previously set forth an obvious modification of Ober that would
`
`enable its CPU to execute instructions at different frequencies as taught in
`
`Nakazato. And I don’t see that Patent Owner has disputed that Nakazato teaches
`
`executing instructions at different CPU frequencies. Therefore, Patent Owner has
`
`not compelled me in any way to reject my earlier position that the combination of
`
`Ober and Nakazato render this limitation obvious.
`
`- 11 -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`I also disagree with Patent Owner’s arguments because they are solely
`
`25.
`
`focused on what Ober explicitly discloses, as opposed to what Ober suggests to a
`
`POSITA. And in fact, the portion of Ober cited by Patent Owner supports my
`
`position. Patent Owner argues that the “Low Speed Clocks” variable controls the
`
`speed of the system clock. Id., 35. As a consequence, Patent Owner also contends
`
`that although the “Low Speed Clock” variable can control the speed of the CPU, it
`
`does not because Ober allegedly “requires that the CPU’s clock be stopped while
`
`the system clock is low speed.” Id. But, to support this statement, Patent Owner
`
`merely argues that Ober never describes the CPU operating while “Low Speed
`
`Clocks” is true. Id. But even if this is true, Patent Owner overlooks that Ober’s
`
`“Low Speed Clocks” is a variable.
`
`26.
`
`Further, Patent Owner incorrectly assumes that if one adjusted Ober’s
`
`system clock during RUN mode, “Low Speed Clocks” would somehow no longer
`
`be set to “false.” Yet nothing in Ober links “Low Speed Clocks” to changes in the
`
`system clock, nor does Patent Owner cite any support for its assumption either.
`
`Moreover, as explained above, I proposed modifying Ober’s register in order to
`
`support the adjustment of CPU clock changes. So even if the “Low Speed Clocks”
`
`variable is changed based on a changed register value in Ober’s current system, as
`
`Patent Owner contends, nothing in my previous testimony or in Ober suggests that
`
`this would happen in the combined system of Ober and Nakazato. In other words, I
`
`- 12 -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`proposed using currently unused bits of a register to effectuate the clock change.
`
`Nothing in Ober suggests the same “Low Speed Clock” variable would be changed
`
`in response to this, nor did I ever propose this.
`
`27. A POSITA would have understood that variables are intended to be
`
`changed. Thus, assuming Patent Owner’s interpretation is correct in describing
`
`“Low Speed Clock” as a variable, Ober also suggests to a POSITA that system
`
`clock speed can be changed, including during “RUN” mode. Dr. Przybylski seems
`
`to agree with me that if the system clock is changed during “RUN” state, it would
`
`cause Ober’s CPU core 22 to execute instructions at a different clock frequency.
`
`EX1029, 90:9-16 (“If you divide the system clock during run mode that would
`
`affect the frequency of the core and the execution of instructions.”). Therefore, it is
`
`my opinion that the passages Patent Owner cites would have suggested to a
`
`POSITA that Ober’s CPU is capable of executing instructions at different clock
`
`speeds.
`
`2. Ober in view of Nakazato discloses “a first memory that
`stores a clock control library for controlling a clock
`frequency transition between said ordinary operation
`modes.”
`28. Based on my review, Patent Owner appears to largely restate its
`
`arguments relating to “the plurality of ordinary operation modes.” Thus, my
`
`testimony above relating to that limitation is likewise applicable here. Specifically,
`
`Patent Owner argues that Ober “does not suggest that the SFR 62 may be modified
`
`- 13 -
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`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`so that more than one frequency is supplied to the CPU in RUN mode.” POR, 37.
`
`But Patent Owner once again does not account for teachings of the combination.
`
`29. As I explained in my previous declaration, Ober in view of Nakazato
`
`discloses “a first memory that stores a clock control library for controlling a clock
`
`frequency transition between said ordinary operation modes” because Ober
`
`discloses a register 62 used for adjusting the system clock. See EX1003, ¶¶108-21.
`
`This register includes multiple unused bits that a POSITA would have recognized
`
`to be modifiable to also adjust the system clock during normal mode based on the
`
`teachings of Nakazato. Id., ¶¶112-13. Patent Owner argues that Ober’s register 62
`
`is only for SLEEP mode, that its unused bits cannot be used, and that any divided
`
`clock signal is not supplied to those peripherals, but rather is locally generated at
`
`those peripherals. However, this misinterprets of AMD’s proposed combination.
`
`30.
`
`In my previous declaration, I explained how Ober’s SFR 62 would
`
`have been modified to support different RUN mode clock frequencies. See id.,
`
`¶¶108-12. In response, Patent Owner argues that these modifications are not
`
`disclosed by Ober: “Ober does not suggest that the SFR 62 may be modified so
`
`that more than one frequency is supplied to the CPU in RUN mode.” POR, 37. But
`
`this is beside the point. I acknowledged in my earlier declaration that Ober doesn’t
`
`disclose modifying these registers. Rather I explain why a POSITA would have
`
`been motivated to modify Ober to support different clock speeds for Ober’s CPU
`
`- 14 -
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`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`during normal operations by changing the use of these registers. Patent Owner does
`
`not dispute this explanation, but instead focuses on the details I provided as to how
`
`a POSITA would go about modifying Ober to support this functionality, such as
`
`modifying register 62.
`
`31. For example, in my declaration, I explained that the bits of the SlpClk
`
`(register 62) can be adjusted to change the speed of the CPU, and that it would be
`
`obvious to use a similar mechanism to change the speed of the CPU during normal
`
`operations. EX1003, ¶¶112, 119-121. Patent Owner, however, focuses on the fact
`
`that Ober’s SlpClk is used to program the frequency of the system clock during a
`
`sleep mode of operation. POR, 38. During this time, Patent Owner alleges, the
`
`CPU is turned off and therefore cannot serve as the claimed “first memory … for
`
`controlling clock frequency transitions between said ordinary operation modes.”
`
`POR, 38 citing EX1004, 13:55 and 13:61. First, POs argument, even assuming it
`
`were true (and it is not) is irrelevant because AMD’s contentions relate to changing
`
`CPU speed during normal mode, not sleep mode. But Patent Owner’s position also
`
`ignores other relevant portions of Ober. For example, Ober discloses that “[i]n
`
`[SLEEP MODE (Clock Distributed)], the PLL and oscillator are not stopped and
`
`the clock is distributed to the system.” EX1004, 15:41-43 (emphasis added). A
`
`POSITA would have understood from this disclosure that the divided clock is at
`
`least provided to the CPU during SLEEP mode. Patent Owner instead chooses to
`
`- 15 -
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`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`ignore the implications of this disclosure in favor of a rigid interpretation of Ober.
`
`Specifically, as I previously argued and as Dr. Przybylski confirmed, Ober thus
`
`teaches that varying clock frequencies can be supplied to core 22 at the same time
`
`as they are provided to the peripherals. See Pet., 24-25, EX1029, 86:14-17.
`
`Because Ober discloses providing divided clocks to the peripherals during normal
`
`mode, it would have been obvious to likewise provide those clocks to the core
`
`during normal mode.
`
`32. Patent Owner also argues that my reliance on column 9:65-10:2 of
`
`Ober is misplaced because, according to Patent Owner, this passage implies that a
`
`divided clock signal is locally generated at the subsystems by their corresponding
`
`FPIs, and not distributed by the power management state machine. POR, 41; see
`
`also id., 39-41. Patent Owner thus argues that the divided clock referenced in the
`
`above passage is not provided to the peripherals, but rather is generated by those
`
`peripherals.
`
`33. During his deposition, Dr. Przybylski elaborated on this argument,
`
`explaining that this localized clock division was the result of some undisclosed
`
`“divider” at the FPI. EX1029, 124:16-22. But this argument lacks any basis in
`
`Ober. For example, Dr. Przybylski argued that this configuration is implied
`
`because in “Table 4 it says that that field is dividing a clock.” Id., 125:4-5. Table 4
`
`of Ober discloses the bits of the SFR register 116. See EX1004, 9:30-48. That
`
`- 16 -
`
`

`

`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`register includes an SDClk field that has two different possible settings: “Disable
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`During SLEEP (Default)”; and “Divided Clock During SLEEP as defined by
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`Peripheral.” Id. But this, in my opinion, is insufficient to demonstrate the existence
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`of some undisclosed divider within the FPI.
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`34. This argument is also wrong because based on Ober’s explanation that
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`the FPIs are nothing more than busses: “The FPI is a 32 bit de-multiplexed,
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`pipelined bus.” Id., 2:64-65. Consequently, the FPIs lack the functionality to divide
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`a received clock signal, meaning that the divided clock signal is instead generated
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`externally to the FPI (e.g., by the power management subsystem 26) and
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`transmitted to the FPI for use by the peripheral. Thus, as I presented in my original
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`declaration, Ober’s disclosure at 9:65-10:2 merely evidences that the divided clock
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`can be distributed during normal mode. EX1003, ¶87. But it is the register 62, in
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`the power management subsystem 26 that ultimately causes the generation and
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`distribution of the divided clock. Id., ¶110.
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`35. Additionally, I previously explained that “Ober does not explicitly
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`describe how the clock is divided during ‘normal mode.’” Id., ¶88. And thus, a
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`“POSITA looking to implement the teachings of Ober would need to understand
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`the circumstances under which CPU speed would be reduced, while a computer is
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`normally operating, and how such a system would control the CPU speed.” Pet,
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`17 (emphasis added). This is where Nakazato fits, because “Nakazato discloses a
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`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`‘CPU speed control circuit 152’ that ‘controls the processing speed of the CPU 11,
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`and has a throttling controller for switching the CPU speed.’” EX1003, ¶89 (citing
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`EX1008, 5:44-49).
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`36. Therefore, it is irrelevant in my opinion whether Ober discloses or
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`suggests the modifications that I discussed. These modifications are instead taught
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`by the combination and recognized by a POSITA, which I believe has been shown
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`and not been rebutted.
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`3.
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`A POSITA would have been motivated to combine Ober
`and Nakazato, and would have had a reasonable
`expectation of success.
`37. As I set forth in my original declaration, a POSITA would have been
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`motivated to combine Ober and Nakazato, at least because Ober alludes to the
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`adjusting of the CPU during normal operations as being well-known, whereas
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`Nakazato provides the teachings necessary to implement normal mode CPU
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`adjustments. EX1003, ¶¶110-21. Patent Owner disputes this, arguing that a
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`POSITA would not have been motivated to combine Ober and Nakazato for two
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`primary reasons: 1) modifying Ober as proposed would inject centralized aspects
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`into Ober’s decentralized system; and 2) changing the system clock “in an
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`unknown or unexpected manner” would cause certain peripherals to fail. POR, 49-
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`50, 52. But these arguments yet again rely on an overly narrow interpretation of
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`Ober.
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`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`(a) Ober is not limited to decentralized power
`management.
`38. Patent Owner first argues that modifying Ober in the manner proposed
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`would change Ober’s principle of operation because Ober is primarily concerned
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`with “independent control of peripheral power consumption,” and that modifying it
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`based on Nakazato would inject centralized power management aspects. Id., 49-50.
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`For substantially the same reasons, Patent Owner also argues that Ober teaches
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`away from a combination with Nakazato. Id., 54-61. But, in my opinion, this
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`misinterprets Ober.
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`39. Although Ober seeks to achieve decentralized power management in
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`some aspects, Ober achieves this via a centralized power management subsystem
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`26: “The management subsystem 26 includes a power manager 28 which controls
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`the power modes of the CPU core 22 as well as other subsystems to be controlled.”
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`EX1004, 5:37-41. Table 2 of Ober demonstrates the wide array of power
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`management functions carried out by the centralized power management
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`subsystem, including resetting FPI subsystems, distributing the system clock,
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`asserting IDLE and SLEEP modes. Id., 7:1-18. Additionally, Ober explains with
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`respect to the clock subsystem 64 how the power management subsystem 26
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`generates the various clock frequencies used during the different modes of
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`operation. Id., 8:53-9:18. Therefore, Ober is only decentralized in the sense that it
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`allows for decentralized control of power settings. But it still maintains a
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`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`centralized power management structure. This functionality would remain in the
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`proposed combination of Ober and Nakazato.
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`40.
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`Patent Owner’s expert, Dr. Przybylski confirmed this understanding
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`during his deposition. In particular, when asked whether Ober’s power
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`management scheme was “solely decentralized,” Dr. Przybylski replied “[n]o, it’s
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`not solely decentralized.” EX1029, 71:22-72:2. Dr. Przybylski also explained that
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`“the state that the power management state machine is in indicates the power state
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`of the microcontroller as a whole. One of them is run, one of them is idle ….” Id.,
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`77:6-10. Dr. Przybylski also agreed that the power state machine is stored in the
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`power manager, which is centralized: “Yes, it is centralized. It is – it is the power
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`management state for the entire microcontroller.” Id., 77:22-78:2 (emphasis
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`added).
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`41. More importantly, I did not propose modifying any core functionality
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`of Ober. As noted above, the modification to Ober is simply incorporating CPU
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`speed-changing functionality from Nakazato. EX1003, ¶¶87-91. I did not propose
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`removing any functionality. Id, ¶¶110-112. In fact, I proposed how to combine the
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`references using existing mechanisms in Ober, namely register 62. Id. Thus, as a
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`result of this modification, Ober would still maintain its independent control of
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`power settings for subsystems. Therefore, to the extent Ober is decentralized, it
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`would remain so when combined with Nakazato.
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`Declaration of David H. Albonesi
`U.S. Patent No. 6,895,519
`42. Therefore, Ober is not solely a decentralized system. Consequently,
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`Patent Owner’s argument that Ober cannot include other centralized power
`
`management aspects (such as operating the CPU on a low-speed clock) because it
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`is decentralized is simply incorrect.
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`(b) Modifying Ober as proposed would have been well
`within the abilities of a person of ordinary skill in the
`art.
`43. Patent Owner also argues that the c