VHDL
`Coding Styles and
`Methodologies, 2nd Edition
`
`--- an In-Depth Tutorial
`
`
`
`Ben Cohen
`
`AQUILA - Ex. 2011
`AQUILA- Ex. 2011
`
`
`Coding Styles and
`Methodologies, 2nd Edition
`
`--- an In-Depth Tutorial
`
`
`
`Ben Cohen
`
`AQUILA - Ex. 2011
`AQUILA- Ex. 2011
`
`
`
`VHDL Coding Styles and Methodologies
`
`Second Edition
`
`
`
`This Page Intentionally Left Blank
`
`
`
`VHDL Coding Styles and Methodologies
`
`Second Edition
`
`Ben Cohen
`
`KLUWER ACADEMIC PUBLISHERS
`
`NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
`
`
`
`CD-ROM only available in print edition.
`eBook ISBN: 0-306-47681-9
`Print ISBN:
`0-7923-8474-1
`
`©2002 Kluwer Academic Publishers
`New York, Boston, Dordrecht, London, Moscow
`
`Print ©1999 Kluwer Academic Publishers
`Dordrecht
`
`All rights reserved
`
`No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
`mechanical, recording, or otherwise, without written consent from the Publisher
`
`Created in the United States of America
`
`Visit Kluwer Online at:
`and Kluwer's eBookstore at:
`
`http://kluweronline.com
`http://ebooks.kluweronline.com
`
`
`
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`CONTENTS
`
`1.0 VHDL OVERVIEW AND CONCEPTS
`
`WHAT IS VHDL
`1.1
`1.2
`LEVEL OF DESCRIPTIONS
`1.3
`METHODOLOGY AND CODING STYLE REQUIREMENTS
`1.4
`VHDL TYPES
`VHDL OBJECT CLASSES
`1.5
`Constant
`1.5.1
`Signal and Variable
`1.5.2
`File
`1.5.3
`1.6 VHDL DESIGN UNITS
`ENTITY
`1.6.1
`1.6.1.1
`Style
`1.6.1.1.1
`Comment
`Header
`1.6.1.1.2
`Generics
`1.6.1.1.3
`1.6.1.1.4
`Indentation
`Line length
`1.6.1.1.5
`1.6.1.1.6
`Statements per line
`1.6.1.1.7
`Declarations per line
`1.6.1.1.8
`Alignment of declarations
`1.6.1.2
`Entity Ports
`ARCHITECTURE
`1.6.2
`1.6.2.1
`Process
`1.7 COMPILATION, ELABORATION, SIMULATION
`Compilation Example
`1.7.1
`1.7.2
`Simulation Example
`1.7.3
`Synthesis Example
`
`2.0 BASIC LANGUAGE ELEMENTS
`
`2.1 LEXICAL ELEMENTS
`Identifiers
`2.1.1
`Port Identifiers
`2.1.1.1
`2.1.1.2
`Identifier Naming Convension
`2.1.1.3
`Accessing Identifiers Defined in Packages
`2.1.1.4
`Capitalization
`2.2 SYNTAX
`Delimiters
`2.2.1
`Literals
`2.2.2
`2.2.2.1
`Decimal literals
`2.2.2.2
`Based literals
`Character literals
`2.2.2.3
`2.2.2.4
`String literals
`2.2.2.5
`Bit string literals
`Operators and Operator Precedence
`2.2.3
`Logical operators
`2.2.3.1
`Relational Operators
`2.2.3.2
`Shift Operators
`2.2.3.3
`The Concatenation "&" Operator
`2.2.3.4
`
`
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`VHDL Coding Styles and Methodologies
`
`Remainder and Modulus
`2.2.3.5
`2.3 TYPES AND SUBTYPES
`Scalar Type
`2.3.1
`Integer Type and Subtypes
`2.3.1.1
`2.3.1.2
`Enumeration Types
`User Defined Enumeration Types
`2.3.1.2.1
`Predefined Enumeration Types
`2.3.1.2.2
`Boolean Type
`2.3.1.2.3
`2.3.1.3
`Physical types
`2.3.1.4
`Distinct Types and Type Conversion
`2.3.1.5
`Real type
`Composite
`2.3.2
`2.3.2.1
`Arrays
`2.3.2.1.1
`One Dimensional Arrays
`Unconstrained Array Types
`2.3.2.1.2
`Multi-dimensional Array types
`2.3.2.1.3
`2.3.2.1.4
`Anonymous Arrays
`2.3.2.1.5
`Implicit Functions for Array Declarations
`2.3.2.1.6
`Array Slices and Ranges
`2.3.2.2
`Records
`2.3.3
`Access Type
`FILE
`2.4
`ATTRIBUTES
`2.5
`ALIASES
`2.6
`
`3.0 CONTROL STRUCTURES
`
`EXPRESSION CLASSIFICATION
`3.1
`CONTROL STRUCTURES
`3.2
`3.2.1
`The "if" Statement
`3.2.2
`The Case Statement
`3.2.2.1
`Rules for the Case Statement
`3.2.3
`Latch Inference
`3.2.4
`Register Inference
`3.2.5
`Loop Statement
`3.2.5.1
`The Simple Loop
`3.2.5.2
`The while loop
`The for loop
`3.2.5.3
`3.2.5.3.1
`for loop Rules
`
`4.0 DRIVERS
`
`RESOLUTION FUNCTION
`4.1
`4.2
`DRIVERS
`Definition and Initialization
`4.2.1
`4.2.2
`Creation of Drivers
`Drivers and Resolved Signal Types
`4.2.3
`4.2.3.1
`Driving Data from multiple Processes onto a Non-Resolved Signal
`4.3 PORTS
`
`5.0 VHDL TIMING
`
`SIGNAL ATTRIBUTES
`5.1
`THE "WAIT" STATEMENT
`5.2
`Delta Time
`5.2.1
`wait on sensitivity_list
`5.2.2
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`Table of Contents
`
`wait until condition
`5.2.3
`wait for time_expression
`5.2.4
`SIMULATION ENGINE
`5.3
`5.4
`MODELING WITH DELTA TIME DELAYS
`5.4.1
`Wait for 0 ns Method
`Concurrent Statements Method
`5.4.2
`Use of Variables Method
`5.4.3
`5.4.4
`VITAL Tables
`5.5 INERTIAL / TRANSPORT DELAY
`Simulation Engine Handling of Inertial Delay
`5.5.1
`Simple View
`5.5.1.1
`Updating Projected Waveforms per LRM 8.4.1
`5.5.1.2
`
`6.0 ELEMENTS OF ENTITY/ARCHITECTURE
`
`VHDL ENTITY
`6.1
`VHDL ARCHITECTURE
`6.2
`Process Statement
`6.2.1
`Concurrent Signal Assignment Statements
`6.2.2
`Conditional Signal Assignment
`6.2.2.1
`Selected Signal Assignment
`6.2.2.2
`Component Instantiation Statement
`6.2.3
`Port Association Rules
`6.2.3.1
`Connection
`6.2.3.1.1
`Type Conversion
`6.2.3.1.2
`Concurrent Procedure Call
`6.2.4
`Generate Statement
`6.2.5
`Concurrent Assertion Statement
`6.2.6
`Block Statement
`6.2.7
`Guarded Signal Assignments
`6.2.7.1
`
`7.0 SUBPROGRAMS
`
`SUBPROGRAM DEFINITION
`7.1
`SUBPROGRAM RULES AND GUIDELINES
`7.2
`Unconstrained Arrays in Subprograms
`7.2.1
`Interface class declaration
`7.2.2
`Subprogram Initialization
`7.2.3
`Subprogram Implicit Signal Attributes
`7.2.4
`Passing Subtypes
`7.2.5
`Drivers in Subprograms
`7.2.6
`Signal Characteristics in Procedure Calls
`7.2.7
`Side Effects
`7.2.8
`Separating High Level Tasks From Low Level Protocols
`7.2.8.1
`Positional and Named Notation
`7.2.9
`SUBPROGRAM OVERLOADING
`7.3
`FUNCTIONS
`7.4
`RESOLUTION FUNCTION
`7.5
`OPERATOR OVERLOADING
`7.6
`CONCURRENT PROCEDURE
`7.7
`
`8.0 PACKAGES
`
`8.1 PACKAGE
`Package Declaration
`8.1.1
`
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`VHDL Coding Styles and Methodologies
`
`Package Body
`8.1.2
`Deferred Constant
`8.1.3
`The "use" Clause
`8.1.4
`Signals in Packages
`8.1.5
`Resolution Function in Packages
`8.1.6
`8.1.7
`Subprograms in Packages
`CONVERTING TYPED OBJECTS TO STRINGS
`8.2
`PACKAGE TEXTIO
`8.3
`Printing Objects from VHDL
`8.3.1
`8.4 DESIGN OF A LINEAR FEEDBACK SHIFT REGISTER (LFSR)
`Random Number Generation
`8.4.1
`8.5 COMPILATION ORDER
`Compilation Rules on Changes
`8.5.1
`Automatic Analysis of Dependencies
`8.5.2
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`9.0 USER DEFINED ATTRIBUTES, SPECIFICATIONS, AND CONFIGURATIONS
`
`261
`
`ATTRIBUTE DECLARATIONS
`9.1
`USER-DEFINED ATTRIBUTES
`9.2
`SPECIFICATIONS
`9.3
`Attribute Specifications
`9.3.1
`9.4 CONFIGURATION SPECIFICATION
`Default Binding Indication
`9.4.1
`Explicit Binding Indication in Configuration Specifications
`9.4.2
`9.5 CONFIGURATION DECLARATION
`9.5.1
`Binding with configured components
`CONFIGURATION OF GENERATE STATEMENTS
`9.5.2
`Deferring the Binding of an Instance of a Component
`9.5.3
`
`10.0 DESIGN FOR SYNTHESIS
`
`10.1
`CONSTRUCTS FOR SYNTHESIS
`10.2
`REGISTER INFERENCE
`10.2.1
`Signals Assignments in Clocked Process
`10.2.2
`Variable assignments in clocked process
`Asynchronous Reset or Set of Registers
`10.2.3
`10.2.4
`Synchronous Reset or Set of Registers
`10.3
`COMBINATIONAL LOGIC INFERENCE
`10.3.1
`Latch Inference and Avoidance
`10.3.2
`Variable
`10.4
`STATE MACHINE
`10.5
`RTL STATE MACHINE DESIGN STYLES
`10.5.1
`State Machine Styles
`10.5.2
`Safe FSM with No Lock up
`10.6
`ARITHMETIC OPERATIONS
`
`11.0 FUNCTIONAL MODELS AND TESTBENCHES
`
`11.1
`TESTBENCH MODELING
`11.1.1
`Testbench Overview
`11.1.2
`Testbench Design Methodology
`Validation Plan
`11.1.2.1
`List of errors to be detected
`11.1.2.2
`Architecture block diagram
`11.1.2.3
`
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`
`
`Table of Contents
`
`Testbench design
`11.1.2.4
`11.1.3 Testbench Architectures
`11.1.3.1
`Typical Testbench Architecture
`11.1.4 FM/BFM Modeling Requirements
`11.2
`SCENARIO GENERATION SCHEMES
`11.2.1 Scenario Generation Model: VHDL Code
`11.2.1.1
`Waveform Generator
`11.2.1.2
`Client/Server
`11.2.2 Scenario Generation Model: Text Command File
`11.2.3 Scenario Generation Model: Binary Command File
`11.2.3.1
`Generation of Binary Files
`
`12.0 UART PROJECT
`
`12.1
`UART ARCHITECTURE
`12.1.1 UART Transmitter
`12.1.1.1
`General UART Concepts
`12.1.1.2
`UART Transmitter design
`12.1.2 UART Receiver
`UART TESTBENCH
`12.2
`UART Package
`12.2.1
`Transmit Protocol
`12.2.2
`Receive Protocol Component
`12.2.3
`Transmission Line Component
`12.2.4
`Monitor or Verifier Component
`12.2.5
`Testbench Entity and Architecture
`12.2.6
`Configuration
`12.2.7
`
`13.0 VITAL
`
`VITAL
`13.1
`13.1.1 Overview
`13.2
`VITAL FEATURES
`VITAL MODEL
`13.3
`13.3.1
`Pin-to-Pin Delay Modeling Style
`Distributed Delay Modeling Style
`13.3.2
`
`APPENDIX A
`
`VHDL'93 AND VHDL'81 SYNTAX SUMMARY
`
`APPENDIX B
`
`PACKAGE STANDARD
`
`APPENDIX C
`
`PACKAGE TEXTIO
`
`APPENDIX D
`
`STD_LOGIC_TEXTIO
`
`APPENDIX E
`
`PACKAGE STD_LOGIC_1164
`
`APPENDIX F
`
`NUMERIC_STD
`
`APPENDIX G
`
`STD_LOGIC_UNSIGNED
`
`APPENDIX H
`
`STD_LOGIC_SIGNED
`
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`VHDL Coding Guide and Methodologies
`
`10.4 STATE MACHINE
`
`A state machine is a sequential logic where its outputs are a function of not only its
`inputs but also the present condition or state of the circuit. The state of a circuit is
`stored in state registers. Two VHDL styles are used to define a sequential logic:
`Implicit finite state machine descriptions that contain no explicit states
`1.
`register. Those registers are implied by the control flow. This type of design is
`only synthesizable with behavior compiler tools, but not RTL synthesis tools.
`
`2.
`
`Explicit finite state machine descriptions that use an explicit state register to
`hold an encoded representation of the current state. For each state machine, a
`state register is defined in a clocked process. Combinational logic can be
`expressed either external to this clocked process, or can be implied from within
`the clocked process. This style of coding is synthesizable with RTL
`synthesizers.
`
`Figure 10.4 is an example of two identical representations of a state machine, an implicit
`state machine in architecture Implicit_a, and an explicit state machine in architecture
`Explicit_a. Note that the implicit state machine model uses a procedural flow of control
`to determine the sequences of states. This flow is controlled by the introduction of
`multiple wait until clock'event statements. However, the explicit state machine restricts
`the use of a single wait until clock'event statement.
`
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`VHDL Coding Guide and Methodologies
`
`10.5.2 Safe FSM with No Lock up
`
`It is possible in VHDL to write a state machine with unused implemented states. For
`example, if a state machine (FSM) has five states with an enumeration type of five
`enumerations (e.g., S0, S1, S2, S3, S4), then binary encoded machine would be
`implemented with three bits, most likely encoded as follows:
`S0="000"; S1="001"; S2="010"; S3="011"; S4="100".
`Three bits define eight states. What happens if the state register enters one of those
`undefined state (e.g., "101" or a "110" or "111")? The action to be taken in one of those
`undefined states is tool dependent and is unpredictable. For binary encoded machines,
`some synthesizers will eliminate "unreachable" states to achieve "quality of results".
`
`For mission critical designs, is not acceptable to be locked into an
`
`unpredictable state if the FSM enters an unused hardware state. To overcome this
`problem, it is important to follow the following recommendations:
`Define the number of enumeration for states of the FSM to be a power of two. For
`example, an FSM with five states would have eight enumerations.
`In the case statement of the FSM, use the when others statement to define a recovery
`for the unexpected states. For the five states example, after defining the cases for
`
`
`
`Design for Synthesis
`
`305
`
`the five used states, use the when others case choice to define the course of action
`(and next recovery state) for the error condition.
`One-hot encoded FSMs are more difficult to control than sequential encoding in the
`event of a hardware error in one of the bits of the state register. In one-hot encoding,
`only one of the bits of the state register is at a logical ONE, all other bits are at logical
`ZERO. A sixteen-state machine would use sixteen registers. To reliably detect an error
`in the state register, it is necessary to perform a sum of all the bits of the state register,
`and compare that sum against the value of ONE. If the sum is unequal to ONE, then an
`error condition exists. The cost of the adder in terms of delays may not overcome the
`speed advantage of the one-hot encoding scheme.
`Thus, for non-mission critical
`designs, one-hot encoding scheme is acceptable. For mission critical designs use a
`binary encoding scheme.
`
`10.6 ARITHMETIC OPERATIONS
`
`The arithmetic operations are specified in several packages. Most synthesizer vendors
`have adopted the Synopsys packages including:
`Std_Logic_Arith
`Std_Logic_Signed
`Std_Logic_Unsigned
`Many vendors are also adopting the IEEE standard packages including:
`Numeric_Bit.
`Numeric_Std
`These packages define the Signed and Unsigned types, and a set of overloaded operators
`that operate on Signed , Unsigned, Std_Logic_Vector, and Integer types. Figure 10.6-1
`is demonstrates the use of the Std_Logic_Unsigned and Std_Logic_Arith packages in a
`model that performs addition, subtraction, and multiplication. Figure 10.6-2 is an RTL
`view of the model.
`
`
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