ETB11™
`Revision: r0p1
`
`Technical Reference Manual
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`ARM DDI 0275D
`
`AQUILA - Ex. 2009
`
`

`

`ETB11
`Technical Reference Manual
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`Release Information
`
`Change history
`
`Date
`
`Issue
`
`Change
`
`December 2002
`
`February 2003
`
`May 2003
`
`August 2003
`
`A
`
`B
`
`C
`
`D
`
`First release
`
`ETB revision has changed to r0p1
`
`Description of ETMv1/ETMv2 supported removed.
`
`Preface and Index updated and corrected, Resets correctly described 2.10.2,
`and 3.2.5 RAM Data Register corrected.
`
`Proprietary Notice
`
`Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and
`other countries, except as otherwise stated below in this proprietary notice. Other brands and names
`mentioned herein may be the trademarks of their respective owners.
`
`Neither the whole nor any part of the information contained in, or the product described in, this document
`may be adapted or reproduced in any material form except with the prior written permission of the copyright
`holder.
`
`The product described in this document is subject to continuous developments and improvements. All
`particulars of the product and its use contained in this document are given by ARM in good faith. However,
`all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
`fitness for purpose, are excluded.
`
`This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
`for any loss or damage arising from the use of any information in this document, or any error or omission in
`such information, or any incorrect use of the product.
`
`Confidentiality Status
`
`This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
`license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
`ARM delivered this document to.
`
`Product Status
`
`The information in this document is final, that is for a developed product.
`
`Web Address
`
`http://www.arm.com
`
`ii
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Contents
`ETB11 Technical Reference Manual
`
`Chapter 1
`
`Chapter 2
`
`Preface
`About this document ...................................................................................... x
`Feedback ..................................................................................................... xiv
`
`Introduction
`1.1
`About the Embedded Trace Buffer ............................................................. 1-2
`1.2
`ETM versions and variants .......................................................................... 1-5
`1.3
`Silicon revision ............................................................................................ 1-6
`
`Functional Description
`2.1
`Functional information ................................................................................. 2-2
`2.2
`Operation .................................................................................................... 2-4
`2.3
`Control logic ................................................................................................ 2-6
`2.4
`Data Formatter ............................................................................................ 2-8
`2.5
`Trigger delay counter .................................................................................. 2-9
`2.6
`Address generation ................................................................................... 2-10
`2.7
`BIST interface ........................................................................................... 2-11
`2.8
`TAP controller ........................................................................................... 2-12
`2.9
`Trace RAM interface ................................................................................. 2-15
`2.10
`Clocks, and resets .................................................................................... 2-17
`2.11
`AHB transfers ............................................................................................ 2-19
`
`ARM DDI 0275D
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`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`iii
`
`

`

`Contents
`
`Chapter 3
`
`Chapter 4
`
`Appendix A
`
`Appendix B
`
`Programmer’s Model
`3.1
`About the programmer’s model .................................................................. 3-2
`3.2
`Register descriptions .................................................................................. 3-4
`3.3
`Software access to the ETB11 using the AHB interface .......................... 3-11
`
`Timing Requirements
`4.1
`AHB interface ............................................................................................. 4-2
`4.2
`CLK domain ................................................................................................ 4-4
`4.3
`IEEE1149.1 interface .................................................................................. 4-6
`
`Signal Descriptions
`A.1
`Signal properties and requirements ............................................................ A-2
`A.2
`Signal descriptions ..................................................................................... A-3
`
`Integrating the ETB11
`B.1
`ASIC connections ...................................................................................... B-2
`B.2
`Connecting to ETM11RV ............................................................................ B-3
`B.3
`Connecting the ETB11 in a 64-bit AHB system .......................................... B-4
`
`Glossary
`
`iv
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`List of Tables
`ETB11 Technical Reference Manual
`
`Table 1-1
`Table 2-1
`Table 2-2
`Table 3-1
`Table 3-2
`Table 3-3
`Table 3-4
`Table 3-5
`Table 3-6
`Table 3-7
`Table 3-8
`Table 3-9
`Table 3-10
`Table 3-11
`Table 4-1
`Table 4-2
`Table 4-3
`Table A-1
`Table B-1
`Table B-2
`
`Change history .............................................................................................................. ii
`ETM major architecture versions .............................................................................. 1-5
`Supported public instructions .................................................................................. 2-13
`Trace RAM interface signals ................................................................................... 2-15
`Register map ............................................................................................................. 3-2
`Identification register description ............................................................................... 3-4
`RAM Depth Register bit allocations .......................................................................... 3-5
`RAM Width Register bit allocations ........................................................................... 3-5
`Status Register bit allocations ................................................................................... 3-6
`RAM Data Register bit allocations ............................................................................ 3-7
`RAM Read Pointer Register bit allocations ............................................................... 3-7
`RAM Write Pointer Register bit allocations ............................................................... 3-8
`Trigger Counter Register bit allocations .................................................................... 3-9
`Control Register bit allocations ............................................................................... 3-10
`Registers that require software access ................................................................... 3-11
`AHB interface timing requirements ........................................................................... 4-2
`CLK domain timing requirements .............................................................................. 4-4
`IEEE1149.1 interface timing requirements ................................................................ 4-6
`Signal descriptions .................................................................................................... A-3
`ETB11 connection guide ........................................................................................... B-2
`ETB11 to generic trace port interface connections ................................................... B-3
`
`ARM DDI 0275D
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`Copyright © 2002, 2003 ARM Limited. All rights reserved.
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`v
`
`

`

`List of Tables
`
`vi
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`List of Figures
`ETB11 Technical Reference Manual
`
`Figure 1-1
`Figure 2-1
`Figure 2-2
`Figure 2-3
`Figure 2-4
`Figure 2-5
`Figure 2-6
`Figure 2-7
`Figure 2-8
`Figure 2-9
`Figure 2-10
`Figure 2-11
`Figure 2-12
`Figure 4-1
`Figure 4-2
`Figure 4-3
`
`Key to timing diagram conventions ............................................................................. xii
`System-on-Chip debug implementation .................................................................... 1-2
`ETB11 module block diagram ................................................................................... 2-3
`Trace capture operation ............................................................................................ 2-6
`Trace read operation ................................................................................................. 2-7
`BIST interface block diagram .................................................................................. 2-11
`Read access from Trace RAM timing diagram ........................................................ 2-16
`Write access to Trace RAM timing diagram ............................................................ 2-16
`Example synchronizer ............................................................................................. 2-17
`Synchronization logic between HCLK and CLK domains ....................................... 2-20
`Software read cycle with asynchronous CLK and HCLK ........................................ 2-21
`Software read cycle with synchronous CLK and HCLK .......................................... 2-22
`Software write cycle with asynchronous CLK and HCLK ........................................ 2-24
`Software write cycle with synchronous CLK and HCLK .......................................... 2-25
`AHB interface signals ................................................................................................ 4-2
`CLK domain signals .................................................................................................. 4-4
`IEEE1149.1 interface signals .................................................................................... 4-6
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`vii
`
`

`

`List of Figures
`
`viii
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Preface
`
`This preface introduces the ARM11 Embedded Trace Buffer (ETB11™) Technical
`Reference Manual. It contains the following sections:
`(cid:129)
`About this document on page x
`(cid:129)
`Feedback on page xiv.
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ix
`
`

`

`Preface
`
`About this document
`
`This document is the technical reference manual for the ARM11 Embedded Trace Buffer
`(ETB11) r0p1.
`
`Product revision status
`
`Intended audience
`
`Using this manual
`
`The rnpn identifier indicates the revision status of the product described in this manual,
`where:
`
`rn
`
`pn
`
`Identifies the major revision of the product.
`
`Identifies the minor revision or modification status of the product.
`
`This document has been written for experienced hardware and software engineers who
`want to design or obtain trace information from chips that use ARM cores with the ETM
`facility.
`
`This document is organized into the following chapters:
`
`Chapter 1 Introduction
`Read this chapter for an overview of the ETB11.
`
`Chapter 2 Functional Description
`Read this chapter for a description of the major functional blocks,
`configurability, read and write timing information, clocks, and resets.
`
`Chapter 3 Programmer’s Model
`Read this chapter for a description of the registers and programming
`information.
`
`Chapter 4 Timing Requirements
`Read this chapter for a description of the ETB11 AC timing
`requirements.
`
`Appendix A Signal Descriptions
`This appendix lists the ETB11 signals.
`
`x
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Conventions
`
`Appendix B Integrating the ETB11
`This appendix describes how to integrate the ETB11 if you are not using
`the ETK11 Integration Kit.
`
`Preface
`
`This section describes the conventions that this manual uses:
`(cid:129)
`Typographical
`(cid:129)
`Timing diagrams on page xii
`(cid:129)
`Signal naming on page xii
`(cid:129)
`Numbering on page xiii.
`
`Typographical
`
`This manual uses the following typographical conventions:
`
`italic
`
`bold
`
`monospace
`
`monospace
`
`Highlights important notes, introduces special terminology,
`denotes internal cross-references, and citations.
`
`Highlights interface elements, such as menu names. Denotes
`ARM processor signal names. Also used for terms in descriptive
`lists, where appropriate.
`
`Denotes text that you can enter at the keyboard, such as
`commands, file and program names, and source code.
`
`Denotes a permitted abbreviation for a command or option. You
`can enter the underlined text instead of the full command or option
`name.
`
`monospace italic
`
`Denotes arguments to monospace text where the argument is to be
`replaced by a specific value.
`
`monospace bold
`
`denotes language keywords when used outside example code.
`
` < and >
`
`Angle brackets enclose replaceable terms for assembler syntax
`where they appear in code or code fragments. They appear in
`normal font in running text. For example:
`(cid:129)
`MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
`(cid:129)
`The Opcode_2 value selects which register is accessed.
`
`ARM DDI 0275D
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`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`xi
`
`

`

`Preface
`
`Timing diagrams
`
`This manual contains one or more timing diagrams. The figure named Key to timing
`diagram conventions explains the components used in these diagrams. When variations
`occur they have clear labels. You must not assume any timing information that is not
`explicit in the diagrams.
`
`Clock
`
`HIGH to LOW
`
`Transient
`
`HIGH/LOW to HIGH
`
`Bus stable
`
`Bus to high impedance
`
`Bus change
`
`High impedance to stable bus
`
`Key to timing diagram conventions
`
`Signal naming
`
`The level of an asserted signal depends on whether the signal is active-HIGH or
`active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW
`signals:
`
`Prefix A
`
`Denotes Advanced eXtensible Interface (AXI) global and address
`channel signals.
`
`Prefix B
`
`Denotes AXI write response channel signals.
`
`Prefix C
`
`Denotes AXI low-power interface signals.
`
`Prefix H
`
`Denotes Advanced High-performance Bus (AHB) signals.
`
`Prefix n
`
`Denotes Active-LOW signals except in the case of AHB or Advanced
`Peripheral Bus APB reset signals. These are named HRESETn and
`PRESETn respectively.
`
`Prefix P
`
`Denotes an APB signal.
`
`Prefix R
`
`Denotes AXI read channel signals.
`
`Prefix W
`
`Denotes AXI write channel signals.
`
`xii
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Further reading
`
`Preface
`
`Numbering
`
`<size in bits>’<base><number>
`This is a Verilog method of abbreviating constant numbers. For example:
`(cid:129)
`‘h7B4 is an unsized hexadecimal value.
`(cid:129)
`‘o7654 is an unsized octal value.
`(cid:129)
`8’d9 is an eight-bit wide decimal value of 9.
`(cid:129)
`8’h3F is an eight-bit wide hexadecimal value of 0x3F. This is
`equivalent to b00111111.
`8’b1111 is an eight-bit wide binary value of b00001111.
`
`(cid:129)
`
`This section lists publications by ARM Limited.
`
`ARM periodically provides updates and corrections to its documentation. See
`http://www.arm.com for current errata sheets, addenda, and the ARM Frequently Asked
`Questions.
`
`ARM publications
`
`This document contains information that is specific to the ETB11. Refer to the
`following documents for other relevant information:
`ETB11™ Implementation Guide (ARM DII 0067)
`(cid:129)
`(cid:129)
`Embedded Trace Buffer (Rev 0) Technical Reference Manual (ARM DDI 0242B)
`(cid:129)
`Embedded Trace Macrocell Specification (ARM IHI 0014)
`(cid:129)
`ETM11RV™ Technical Reference Manual (ARM DDI 0233)
`(cid:129)
`ETM11RV Implementation Guide (ARM DII 0061)
`(cid:129)
`ETM11RV User Guide (ARM DUI 0223)
`(cid:129)
`ARM1136JF-S and ARM1136J-S Technical Reference Manual (ARM DDI 0211)
`(cid:129)
`ARM1136JF-S and ARM1136J-S Implementation Guide (ARM DII 0022)
`(cid:129)
`ARM1136JF-S and ARM1136J-S Test Chip Implementation Guide (ARM DXI
`0144)
`ARM Architecture Reference Manual (ARM DDI 0100)
`ARM AMBA® Specification (ARM IHI 0001)
`Multi-ICE System Design Considerations (ARM DAI 0072)
`Multi-ICE® User Guide (ARM DUI 0048)
`Multi-layer AHB Overview (ARM DVI 0045).
`
`(cid:129)
`(cid:129)
`(cid:129)
`(cid:129)
`(cid:129)
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`xiii
`
`

`

`Preface
`
`Feedback
`
`ARM Limited welcomes feedback both on the ETB11 r0p1, and on the documentation.
`
`Feedback on the ETB11
`
`If you have any comments or suggestions about this product, contact your supplier
`giving:
`(cid:129)
`the product name
`(cid:129)
`a concise explanation of your comments.
`
`Feedback on this document
`
`If you have any comments on about this document, send email to errata@arm.com giving:
`(cid:129)
`the document title
`(cid:129)
`the document number
`(cid:129)
`the page number(s) to which your comments refer
`(cid:129)
`a concise explanation of your comments.
`
`General suggestions for additions and improvements are also welcome.
`
`xiv
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Chapter 1
`Introduction
`
`This chapter introduces the Embedded Trace Buffer (ETB11) and its features. It
`contains the following sections:
`(cid:129)
`About the Embedded Trace Buffer on page 1-2
`(cid:129)
`ETM versions and variants on page 1-5
`(cid:129)
`Silicon revision on page 1-6.
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`1-1
`
`

`

`Introduction
`
`1.1
`
`About the Embedded Trace Buffer
`
`As process speeds increase it is increasingly difficult to obtain trace information off a
`chip from an Embedded Trace Macrocell (ETM). This causes difficulties in maintaining
`acceptable signal quality or the signals have to be demultiplexed on to what can become
`a very large number of trace port pins.
`
`The solution is to provide a buffer area on-chip where the trace information is stored,
`and read from the chip later, at a slower rate.
`
`The ETB11 stores data produced by the ETM11RV. The buffered data can then be
`accessed by the debugging tools using a JTAG (IEEE 1149.1) interface, as shown in
`Figure 1-1.
`
`Ethernet
`
`PC-based
`debugging
`tool
`
`JTAG
`interface unit
`
`Trace port
`analyzer
`
`JTAG
`
`ARM processor
`
`EmbeddedICE
`
`ETM11RV
`
`ETB11
`
`Trace
`RAM
`
`AHB bus
`
`On-chip
`ROM
`
`On-chip
`RAM
`
`Peripherals
`
`System-on-Chip
`
`Figure 1-1 System-on-Chip debug implementation
`
`1-2
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Introduction
`
`Providing an on-chip buffer enables the trace data generated by the ETM11RV (at the
`system clock rate) to be read by the debugger at a reduced clock rate. This removes the
`requirement for high-speed pads for the trace data.
`
`This buffered data can also be accessed through an AHB slave-based AHB interface
`included as part of the ETB11. This enables software running on the processor to read
`the trace data generated by the ETM11RV.
`
`The major blocks shown in Figure 1-1 on page 1-2 are:
`
`ETM11RV The ETM11RV monitors the ARM core buses and passes compressed
`information in real time to the ETB11 where it is stored for later retrieval.
`The data is then passed through the JTAG trace port to an interface unit.
`This is an external hardware device that passes the information from the
`trace port to a debugging tool, for example, a PC. The debug tool:
`(cid:129)
`retrieves data from the interface unit
`(cid:129)
`reconstructs a historical view of processor activity including data
`accesses
`configures the macrocell through the JTAG interface unit and port.
`(cid:129)
`User-definable filters enable you to limit the amount of information
`captured in search of a bug, reducing upload time from the trace port
`analyzer.
`
`EmbeddedICE
`EmbeddedICE is a JTAG-based debugging environment for ARM
`microprocessors. EmbeddedICE provides the interface between the
`ARM source-level symbolic debugger, ARMxd, and an ARM
`microprocessor embedded within any ASIC. The ARMxd debugger is
`available for PC compatible and Sun workstation platforms.
`EmbeddedICE provides:
`(cid:129)
`real-time address and data-dependent breakpoints
`(cid:129)
`single stepping
`(cid:129)
`full access and control of the ARM CPU
`(cid:129)
`access to the ASIC system.
`EmbeddedICE also enables the embedded microprocessor to access the
`host system peripherals, for instance screen display, keyboard input and
`disk drive storage.
`
`ARM DDI 0275D
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`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`1-3
`
`

`

`Introduction
`
`JTAG interface unit
`Boundary scan is a methodology enabling complete controllability and
`observability of the boundary pins of a JTAG-compatible device by
`software control. This capability enables in-circuit testing without
`requiring specially designed in-circuit test equipment.
`
`1-4
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`1.2
`
`ETM versions and variants
`
`Introduction
`
`The ETB11 is an enhanced version of the ETB that is designed to support the higher
`operating speeds of ETM11RV.
`
`Although ETB11 supports older ETM protocols, it is intended for use with ETM11RV
`only. For this reason this document only describes details related to storing trace from
`ETM11RV. For details on using an ETB with other ETM products see the Embedded
`Trace Buffer Technical Reference Manual.
`
`The history of the ETM is listed in Table 1-1.
`
`Table 1-1 ETM major architecture versions
`
`Name
`
`ETM7
`
`ETM9
`
`ETM10
`
`Major
`architecture
`version
`
`ETMv1
`
`ETMv1
`
`ETMv2
`
`ETM XScale
`
`ETMv2
`
`ETM10RV
`
`ETM11RV
`
`ETMv3
`
`ETMv3
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`1-5
`
`

`

`Introduction
`
`1.3
`
`Silicon revision
`
`This manual is for ETB11 r0p1. ETB11 r0p1 includes corrections for errata in ETB11
`r0p0. Further information can be found in the ETB11 errata list.
`
`1-6
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Chapter 2
`Functional Description
`
`This chapter describes how the ETB11 operates. It contains the following sections:
`(cid:129)
`Functional information on page 2-2
`(cid:129)
`Operation on page 2-4
`(cid:129)
`Control logic on page 2-6
`(cid:129)
`Data Formatter on page 2-8
`(cid:129)
`Trigger delay counter on page 2-9
`(cid:129)
`Address generation on page 2-10
`(cid:129)
`BIST interface on page 2-11
`(cid:129)
`TAP controller on page 2-12
`(cid:129)
`Trace RAM interface on page 2-15
`(cid:129)
`Clocks, and resets on page 2-17
`(cid:129)
`AHB transfers on page 2-19.
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`2-1
`
`

`

`Functional Description
`
`2.1
`
`Functional information
`
`This section provides basic functional information:
`(cid:129)
`Interfaces
`(cid:129)
`Global configurability.
`
`2.1.1
`
`Interfaces
`
`The on-chip ETB11 module has three primary interfaces:
`
`(cid:129)
`
`(cid:129)
`
`(cid:129)
`
`the trace port from the ETM11RV
`
`a five-pin IEEE 1149.1 (JTAG) interface
`
`an AHB slave interface to give software access to the ETB11 registers.
`
`Additionally, the ETB11 accesses a trace RAM that must be implemented in the target
`technology. It is not possible to provide a single generic RAM interface block because
`of the large number of different RAMs that can be integrated. Therefore, the RAM
`interface is specified but the RAM block must be supplied by the system integrator. The
`RAM interface is described in Trace RAM interface on page 2-15.
`
`Connection of the AHB interface is optional. If you do not require software access to
`the ETB registers or trace RAM, the AHB interface can be left unconnected. If this is
`done, all accesses to the ETB must be performed using the JTAG interface.
`
`A block diagram of the ETB11 module is shown in Figure 2-1 on page 2-3.
`
`2.1.2
`
`Global configurability
`
`The size of the trace RAM is configurable. See the ETB11 Implementation Guide for
`more information. Throughout this document ETB_ADDR_WIDTH refers to the
`address of the trace RAM. For example, if the trace RAM is 4KB, organized as
`1024x32-bit words, ETB_ADDR_WIDTH is 10. ETB11 must always use 32-bit trace
`RAM with ETM11RV. Throughout this document, ETB_DATA_WIDTH is 32.
`
`2-2
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Functional Description
`
`nRESET
`CLK
`
`PORTSIZE[2:0]
`
`Trace buffer
`
`TRACEOUTPUT[(RBW-1):0]
`TRACEVALID
`
`TRIGGER
`PROTOCOL[1:0]
`
`Data
`Formatter
`
`WriteData[(RBW-1):0]
`
`DataValid
`
`D
`
`Din
`
`Dout[(RBW-1):0] Dout
`
`Q
`
`ETB11
`Trace
`RAM
`
`WEN
`
`CEN
`
`OEN
`
`A
`
`Trace RAM interface
`
`Triggered
`
`AcqComp/
`control reg
`
`CData
`
`Reg
`Sync
`
`nR/W
`
`RAMAccess
`
`WR
`
`CS
`
`FULL
`
`ACQCOMP
`
`Control
`register
`
`Addr[(RAW-1):0]
`
`A
`
`DataOut
`
`HCLK/CLK
`synchronization
`
`Register
`control
`
`Read/write
`control signals
`
`AHB interface signals
`
`AHB interface
`
`TraceCaptEn
`
`ReadAddrInc
`
`ReadAddrUp
`
`TAP controller
`
`Configuration
`
`Status
`
`DBGTCKEN DBGTCK
`
`nDBGTRST
`
`DBGTMS
`
`DBGTDI
`
`DBGTDO
`
`nDBGTDOEN
`
`RBW=ETB_DATA_WIDTH
`RAW=ETB_ADDR_WIDTH
`
`Figure 2-1 ETB11 module block diagram
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`2-3
`
`

`

`Functional Description
`
`2.2
`
`Operation
`
`The on-chip ETB11 operates as follows:
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`
`
`The ETM architecture version is supplied to the Data Formatter using the
`PROTOCOL[1:0] signal. This must be set to b10.
`
`Configuration registers are set up through the TAP controller or through the AHB
`interface.
`
`Trace capture is enabled using the control register.
`
`Trace data is continuously written into the trace RAM while the ETB11 is enabled
`and the trigger counter value is nonzero. Once the ETM11RV indicates a trigger
`by asserting TRIGGER, the trigger counter decrements once per word of trace
`stored.
`When the trigger counter reaches zero the acquisition complete flag, AcqComp,
`is activated and trace capture stops. The value loaded into the trigger counter
`therefore sets the number of data words stored in the trace RAM after a trigger
`event.
`
`The debugging tools through the TAP controller can read trace data stored in the
`trace RAM through the TAP controller or through the AHB interface.
`(cid:129)
`To read data through the TAP controller you must:
`1.
`Disable trace capture. If trace capture is enabled when the RAM Data
`Register is accessed, the RAM value read is incorrect.
`2. Write the location that data is read from into the RAM Read Pointer
`Register.
`Read the RAM Data Register to return the data at the address stored
`in the RAM Read Pointer Register. The read address pointer
`increments after each RAM Data Register read and the next data
`value is automatically read from the RAM and stored in the RAM
`Data Register.
`Note
`You must precede the read access by a write to the RAM Read Pointer
`Register to ensure that the first RAM Read Register access returns
`valid data.
`
`3.
`
`(cid:129)
`
`The trace data can also be read using the AHB interface. The trace RAM is
`aliased into the system memory space. This means that reading a value from
`the trace RAM requires an LDR type instruction from the trace RAM address
`space. The AHB interface can also write to the ETB11 memory when trace
`capture is disabled.
`
`2-4
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Functional Description
`
`6.
`
`There are three internal status signals:
`AcqComp
`(cid:129)
`Triggered
`(cid:129)
`Full.
`(cid:129)
`These can be read at any time while trace capture is in progress. The status signals
`are cleared when TraceCaptEn is cleared.
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`2-5
`
`

`

`Functional Description
`
`2.3
`
`Control logic
`
`Control logic monitors the TraceCaptEn signal, the status flags, and the DataValid
`signal from the Data Formatter. The logic enables a RAM write access cycle when there
`is valid data and trace capture is active. Trace capture is active while the TraceCaptEn
`signal is asserted and TrgDelayCounter is nonzero.
`
`TraceCaptEn directly selects RAM write or read mode and the RAM address source.
`When TraceCaptEn is asserted all RAM access cycles are writes using the write
`pointer as the address. When TraceCaptEn is deasserted, RAM accesses are controlled
`by the AHB interface when SoftwareCntl (control register bit 4) is HIGH and SWEN
`is HIGH. Otherwise, all access cycles are reads using the RAM Read Pointer Register
`as the address. Timing diagrams showing the operation of the control logic are given in
`Figure 2-2 and Figure 2-3 on page 2-7.
`
`Figure 2-2 Trace capture operation
`
`2-6
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`Functional Description
`
`R
`
`R+1
`
`UR
`
`UR+1
`
`D
`
`D+1
`
`UD
`
`UD+1
`
`CLK
`
`TraceCaptEn
`
`RAMAddr
`
`ReadData
`
`RAMAccess
`
`ReadAddInc
`
`RegAccess
`
`ControlState
`
`Read
`
`Read
`
`Write
`
`Figure 2-3 Trace read operation
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`2-7
`
`

`

`Functional Description
`
`2.4
`
`Data Formatter
`
`The Data Formatter is used to pack the trace data from ETMv1 ETMs. It is not used by
`ETM11RV. Trace data is written to the trace RAM one word at a time when
`TRACEVALID is asserted by the ETM11RV. You must set the port size to 32 bits and
`port mode to dynamic in the ETM11RV otherwise Unpredictable behavior might occur
`while using the ETB11. See the ETM Specification for details.
`
`2-8
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`2.5
`
`Trigger delay counter
`
`Functional Description
`
`The trigger delay counter, TrgDelayCounter, controls how many data words are
`written into the trace RAM after a trigger event. When a trigger event is detected, the
`Triggered flag is asserted. This enables the trigger delay counter which decrements
`every time a data word is written into the trace RAM. When TrgDelayCounter reaches
`zero the acquisition complete flag, AcqComp, is asserted. This prevents further writes
`to the trace RAM. The AcqComp flag is cleared when trace capture is disabled
`(TraceCaptEn=0). The state of the triggered flag can be read from the Status Register.
`The Triggered flag is cleared when trace capture is disabled.
`
`AcqComp is output as a signal from the macrocell for possible use by ASIC logic.
`
`ARM DDI 0275D
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`2-9
`
`

`

`Functional Description
`
`2.6
`
`Address generation
`
`There are two RAM address pointer registers:
`(cid:129)
`the RAM Write Pointer Register is selected during trace capture
`(cid:129)
`the RAM Read Pointer Register is used as the RAM address source:
`— when trace capture is disabled
`— if software access to registers is disabled.
`
`TraceCaptEn selects which pointer is used.
`
`2.6.1 Write address generation
`
`The RAM Write Pointer Register sets the trace RAM start address. It must be
`programmed before trace capture is enabled. The RAM Write Pointer Register
`increments when the DataValid flag is asserted by the Data Formatter. Reading the
`register returns the current RAM Write Pointer Register value. The RAM Write Pointer
`Register can be read back at any time. However if the TAP controller clock, DBGTCK,
`is asynchronous to CLK, the value might be indeterminate if read while trace capture
`is enabled. Therefore, the pointer must be accessed when TraceCaptEn is deasserted.
`The RAM Write Pointer Register is not affected by AHB writes to the RAM.
`
`2.6.2
`
`Read address generation
`
`When trace capture and software access to registers are disabled, the RAM Read Pointer
`Register generates the RAM address. Updating the RAM Read Pointer Register
`automatically triggers a RAM access to ensure the RAM data output is up-to-date.
`Either writing to the RAM Read Pointer Register or reading the RAM Data Register
`updates the RAM Read Pointer Register. The RAM Read Pointer Register increments
`each time the RAM Data Register is read. The RAM Read Pointer Register can be
`accessed at any time. Reading the RAM Read Pointer Register returns its current value,
`the RAM read address. The RAM Read Pointer Register is not affected by AHB reads
`from the RAM.
`
`2-10
`
`Copyright © 2002, 2003 ARM Limited. All rights reserved.
`
`ARM DDI 0275D
`
`

`

`2.7
`
`BIST interface
`
`Functional Description
`
`ATPG testing can only test out the interface between the ETB11 RAM and the ETB11.
`It is unable to find f