ARM920T
`(Rev 1)
`
`Technical Reference Manual
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`ARM DDI 0151C
`
`AQUILA - Ex. 2008
`
`

`

`
`
`ARM920T
`Technical Reference Manual
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`Release Information
`
`Change history
`
`Date
`
`Issue
`
`Change
`
`31st January 2000
`
`5th September 2000
`
`18th April 2001
`
`A
`
`B
`
`C
`
`First release
`
`Second release
`
`Third release
`
`Proprietary Notice
`
`Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except
`as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
`trademarks of their respective owners.
`
`Neither the whole nor any part of the information contained in, or the product described in, this document
`may be adapted or reproduced in any material form except with the prior written permission of the copyright
`holder.
`
`The product described in this document is subject to continuous developments and improvements. All
`particulars of the product and its use contained in this document are given by ARM in good faith. However,
`all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
`fitness for purpose, are excluded.
`
`This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
`for any loss or damage arising from the use of any information in this document, or any error or omission in
`such information, or any incorrect use of the product.
`
`Figure 9-5 on page 9-12 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port
`and Boundary-Scan Architecture Copyright 2000, by IEEE. The IEEE disclaims any responsibility or liability
`resulting from the placement and use in the described manner
`
`Confidentiality Status
`
`This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
`license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
`ARM delivered this document to.
`
`Product Status
`
`The information in this document is final, that is for a developed product.
`
`Web Address
`
`http://www.arm.com
`
`ii
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`ARM DDI 0151C
`
`

`

`Contents
`ARM920T Technical Reference Manual
`
`Chapter 1
`
`Chapter 2
`
`Chapter 3
`
`Preface
`About this document .................................................................................... xvi
`Further reading ............................................................................................ xix
`Feedback ...................................................................................................... xx
`
`Introduction
`1.1
`About the ARM920T ................................................................................... 1-2
`1.2
`Processor functional block diagram ............................................................ 1-3
`
`Programmer’s Model
`2.1
`About the programmer’s model ................................................................... 2-2
`2.2
`About the ARM9TDMI programmer’s model ............................................... 2-3
`2.3
`CP15 register map summary ...................................................................... 2-5
`
`Memory Management Unit
`3.1
`About the MMU ........................................................................................... 3-2
`3.2
`MMU program accessible registers ............................................................. 3-4
`3.3
`Address translation ..................................................................................... 3-6
`3.4
`MMU faults and CPU aborts ..................................................................... 3-21
`3.5
`Fault address and fault status registers .................................................... 3-22
`3.6
`Domain access control .............................................................................. 3-23
`3.7
`Fault checking sequence .......................................................................... 3-25
`
`ARM DDI 0151C
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`iii
`
`

`

`Contents
`
`Chapter 4
`
`Chapter 5
`
`Chapter 6
`
`Chapter 7
`
`Chapter 8
`
`Chapter 9
`
`3.8
`3.9
`
`External aborts ......................................................................................... 3-28
`Interaction of the MMU and caches .......................................................... 3-29
`
`Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM
`4.1
`About the caches and write buffer .............................................................. 4-2
`4.2
`ICache ........................................................................................................ 4-4
`4.3
`DCache and write buffer ............................................................................. 4-9
`4.4
`Cache coherence ..................................................................................... 4-16
`4.5
`Cache cleaning when lockdown is in use ................................................. 4-19
`4.6
`Implementation notes ............................................................................... 4-20
`4.7
`Physical address TAG RAM ..................................................................... 4-21
`4.8
`Drain write buffer ...................................................................................... 4-22
`4.9
`Wait for interrupt ....................................................................................... 4-23
`
`Clock Modes
`5.1
`About ARM920T clocking ........................................................................... 5-2
`5.2
`FastBus mode ............................................................................................ 5-3
`5.3
`Synchronous mode ..................................................................................... 5-4
`5.4
`Asynchronous mode ................................................................................... 5-6
`
`Bus Interface Unit
`6.1
`About the ARM920T bus interface ............................................................. 6-2
`6.2
`Unidirectional AMBA ASB interface ............................................................ 6-3
`6.3
`Fully-compliant AMBA ASB interface ......................................................... 6-5
`6.4
`AMBA AHB interface ................................................................................ 6-20
`6.5
`Level 2 cache support and performance analysis .................................... 6-22
`
`Coprocessor Interface
`7.1
`About the ARM920T coprocessor interface ................................................ 7-2
`7.2
`LDC/STC .................................................................................................... 7-5
`7.3
`MCR/MRC .................................................................................................. 7-9
`7.4
`Interlocked MCR ....................................................................................... 7-11
`7.5
`CDP .......................................................................................................... 7-13
`7.6
`Privileged instructions ............................................................................... 7-15
`7.7
`Busy-waiting and interrupts ...................................................................... 7-17
`
`Trace Interface Port
`8.1
`About the ETM interface ............................................................................. 8-2
`
`Debug Support
`9.1
`About debug ............................................................................................... 9-2
`9.2
`Debug systems ........................................................................................... 9-3
`9.3
`Debug interface signals .............................................................................. 9-5
`9.4
`Scan chains and JTAG interface .............................................................. 9-11
`9.5
`The JTAG state machine .......................................................................... 9-12
`9.6
`Test data registers .................................................................................... 9-19
`
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`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`ARM DDI 0151C
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`

`

`Contents
`
`9.7
`9.8
`9.9
`9.10
`9.11
`9.12
`9.13
`9.14
`9.15
`9.16
`
`ARM920T core clocks ............................................................................... 9-41
`Clock switching during debug ................................................................... 9-42
`Clock switching during test ........................................................................ 9-43
`Determining the core state and system state ............................................ 9-44
`Exit from debug state ................................................................................ 9-47
`The behavior of the program counter during debug .................................. 9-50
`EmbeddedICE macrocell .......................................................................... 9-53
`Vector catching ......................................................................................... 9-60
`Single-stepping ......................................................................................... 9-61
`Debug communications channel ............................................................... 9-62
`
`TrackingICE
`10.1
`About TrackingICE .................................................................................... 10-2
`10.2
`Timing requirements ................................................................................. 10-3
`10.3
`TrackingICE outputs ................................................................................. 10-4
`
`AMBA Test Interface
`11.1
`About the AMBA test interface .................................................................. 11-2
`11.2
`Entering and exiting AMBA Test ............................................................... 11-3
`11.3
`Functional test ........................................................................................... 11-4
`11.4
`Burst operations ...................................................................................... 11-11
`11.5
`PA TAG RAM test ................................................................................... 11-12
`11.6
`Cache test ............................................................................................... 11-15
`11.7
`MMU test ................................................................................................. 11-19
`
`Instruction Cycle Summary and Interlocks
`12.1
`About the instruction cycle summary ........................................................ 12-2
`12.2
`Instruction cycle times ............................................................................... 12-3
`12.3
`Interlocks ................................................................................................... 12-6
`
`AC Characteristics
`13.1
`ARM920T timing diagrams ........................................................................ 13-2
`13.2
`ARM920T timing parameters .................................................................. 13-14
`13.3
`Timing definitions for the ARM920T Trace Interface Port ....................... 13-24
`
`Signal Descriptions
`A.1
`AMBA signals .............................................................................................. A-2
`A.2
`Coprocessor interface signals ..................................................................... A-5
`A.3
`JTAG and TAP controller signals ................................................................ A-7
`A.4
`Debug signals ........................................................................................... A-10
`A.5
`Miscellaneous signals ............................................................................... A-12
`A.6
`ARM920T Trace Interface Port signals ..................................................... A-13
`
`Chapter 10
`
`Chapter 11
`
`Chapter 12
`
`Chapter 13
`
`Appendix A
`
`Appendix B
`
`CP15 Test Registers
`B.1
`About the test registers ............................................................................... B-2
`B.2
`Test state register ....................................................................................... B-3
`
`ARM DDI 0151C
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`v
`
`

`

`Contents
`
`B.3
`B.4
`B.5
`
`Cache test registers and operations ........................................................... B-8
`MMU test registers and operations ........................................................... B-17
`StrongARM backwards compatibility operations ...................................... B-28
`
`Glossary
`
`vi
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`ARM DDI 0151C
`
`

`

`List of Tables
`ARM920T Technical Reference Manual
`
`Table 2-1
`Table 2-2
`Table 2-3
`Table 2-4
`Table 2-5
`Table 2-6
`Table 2-7
`Table 2-8
`Table 2-9
`Table 2-10
`Table 2-11
`Table 2-12
`Table 2-13
`Table 2-14
`Table 2-15
`Table 2-16
`Table 2-17
`Table 2-18
`Table 2-19
`Table 3-1
`Table 3-2
`Table 3-3
`
`Change history .............................................................................................................. ii
`ARM9TDMI implementation options ......................................................................... 2-3
`CP15 register map .................................................................................................... 2-5
`Address types in ARM920T ...................................................................................... 2-6
`CP15 abbreviations ................................................................................................... 2-6
`Register 0, ID code ................................................................................................... 2-8
`Cache type register format ........................................................................................ 2-9
`Cache size encoding (M=0) .................................................................................... 2-10
`Cache associativity encoding (M=0) ....................................................................... 2-11
`Line length encoding ............................................................................................... 2-11
`Control register 1 bit functions ................................................................................ 2-12
`Clocking modes ....................................................................................................... 2-13
`Register 2, translation table base ............................................................................ 2-14
`Register 3, domain access control .......................................................................... 2-14
`Fault status register ................................................................................................. 2-16
`Function descriptions register 7 .............................................................................. 2-17
`Cache operations register 7 .................................................................................... 2-18
`TLB operations register 8 ........................................................................................ 2-19
`Accessing the cache lockdown register 9 ............................................................... 2-22
`Accessing the TLB lockdown register 10 ................................................................ 2-22
`CP15 register functions ............................................................................................. 3-4
`Level one descriptor bits ........................................................................................... 3-9
`Interpreting level one descriptor bits [1:0] ............................................................... 3-10
`
`ARM DDI 0151C
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`vii
`
`

`

`List of Tables
`
`Table 3-4
`Table 3-5
`Table 3-6
`Table 3-7
`Table 3-8
`Table 3-9
`Table 3-10
`Table 3-11
`Table 4-1
`Table 5-1
`Table 6-1
`Table 6-2
`Table 6-3
`Table 6-4
`Table 6-5
`Table 6-6
`Table 6-7
`Table 6-8
`Table 7-1
`Table 9-1
`Table 9-2
`Table 9-3
`Table 9-4
`Table 9-5
`Table 9-6
`Table 9-7
`Table 9-8
`Table 9-9
`Table 9-10
`Table 9-11
`Table 9-12
`Table 9-13
`Table 9-14
`Table 9-15
`Table 9-16
`Table 9-17
`Table 9-18
`Table 9-19
`Table 10-1
`Table 11-1
`Table 11-2
`Table 11-3
`Table 11-4
`Table 11-5
`Table 11-6
`Table 11-7
`Table 11-8
`
`Section descriptor bits ............................................................................................ 3-11
`Coarse page table descriptor bits ........................................................................... 3-12
`Fine page table descriptor bits ................................................................................ 3-13
`Level two descriptor bits ......................................................................................... 3-15
`Interpreting page table entry bits [1:0] .................................................................... 3-16
`Priority encoding of fault status ............................................................................... 3-22
`Interpreting access control bits in domain access control register ......................... 3-23
`Interpreting access permission (AP) bits ................................................................ 3-23
`DCache and write buffer configuration ................................................................... 4-11
`Clock selection for external memory accesses ......................................................... 5-4
`Relationship between bidirectional and unidirectional ASB interface ....................... 6-3
`ARM920T input/output timing ................................................................................... 6-4
`AMBA ASB transfer types ......................................................................................... 6-6
`Burst transfers .......................................................................................................... 6-7
`Use of WRITEOUT signal ......................................................................................... 6-7
`Noncached LDR and fetch ...................................................................................... 6-11
`Data eviction of 4 or 8 words .................................................................................. 6-16
`ARM920T supported bus access types .................................................................. 6-22
`Handshake encoding ................................................................................................ 7-8
`Public instructions ................................................................................................... 9-14
`ID code register ...................................................................................................... 9-20
`Scan chain number allocation ................................................................................. 9-23
`Scan chain 0 bit order ............................................................................................. 9-24
`Scan chain 1 bit function ......................................................................................... 9-27
`Scan chain 2 bit function ......................................................................................... 9-28
`Scan chain 15 format and access modes ............................................................... 9-31
`Scan chain 15 physical access mode bit format ..................................................... 9-32
`Physical access mapping to CP15 registers ........................................................... 9-32
`Scan chain 15 interpreted access mode bit format ................................................. 9-33
`Interpreted access mapping to CP15 registers ....................................................... 9-34
`Interpreted access mapping to the MMU ................................................................ 9-35
`Interpreted access mapping to the caches ............................................................. 9-35
`Scan chain 4 format ................................................................................................ 9-38
`ARM9TDMI EmbeddedICE macrocell register map ............................................... 9-53
`Watchpoint control register, data comparison bit functions .................................... 9-56
`Watchpoint control register for instruction comparison bit functions ....................... 9-57
`Debug status register bit functions ......................................................................... 9-58
`Debug comms control register bit functions ............................................................ 9-62
`ARM920T in TrackingICE mode ............................................................................. 10-4
`AMBA test modes ................................................................................................... 11-3
`AMBA functional test locations ............................................................................... 11-4
`Construction of A920Inputs location ....................................................................... 11-5
`Construction of A920Status1 location ..................................................................... 11-6
`Construction of A920Status2 location ..................................................................... 11-7
`Burst locations ...................................................................................................... 11-11
`PA TAG RAM locations ........................................................................................ 11-12
`Construction of data pattern write data ................................................................. 11-12
`
`viii
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`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`ARM DDI 0151C
`
`

`

`List of Tables
`
`Cache test locations .............................................................................................. 11-15
`CAM write data ...................................................................................................... 11-15
`CAM match write data ........................................................................................... 11-16
`CAM match read data ........................................................................................... 11-16
`Invalidate by VA write data .................................................................................... 11-16
`Lockdown victim and base data ............................................................................ 11-17
`MMU test locations ................................................................................................ 11-19
`Invalidate by VA data ............................................................................................ 11-19
`Match write data .................................................................................................... 11-20
`CAM data .............................................................................................................. 11-20
`CAM data Size_C encoding .................................................................................. 11-20
`RAM1 data ............................................................................................................ 11-21
`RAM1 data access permission bits ....................................................................... 11-21
`RAM2 data ............................................................................................................ 11-21
`RAM2 data Size_R2 encoding .............................................................................. 11-22
`Symbols used in tables ........................................................................................... 12-3
`Instruction cycle bus times ...................................................................................... 12-3
`Data bus instruction times ....................................................................................... 12-4
`ARM920T timing parameters ................................................................................ 13-14
`ARM920T Trace Interface Port timing definitions ................................................. 13-24
`AMBA signals ............................................................................................................ A-2
`Coprocessor interface signals ................................................................................... A-5
`JTAG and TAP controller signals .............................................................................. A-7
`Debug signals ......................................................................................................... A-10
`Miscellaneous signals ............................................................................................. A-12
`Trace signals ........................................................................................................... A-13
`Test state register ..................................................................................................... B-3
`Clocking mode selection ........................................................................................... B-5
`Register 7 operations ................................................................................................ B-8
`Register 9 operations ................................................................................................ B-8
`Register 15 operations .............................................................................................. B-9
`CP15 MCR and MRC instructions ............................................................................. B-9
`Register 7, 9, and 15 operations ............................................................................. B-10
`Write cache victim and lockdown operations .......................................................... B-14
`TTB register operations ........................................................................................... B-17
`DAC register operations .......................................................................................... B-18
`FSR register operations .......................................................................................... B-18
`FAR register operations .......................................................................................... B-19
`Register 8 operations .............................................................................................. B-19
`Register 10 operations ............................................................................................ B-19
`CAM, RAM1, and RAM2 register 15 operations ..................................................... B-19
`Register 2, 3, 5, 6, 8, 10, and 15 operations ........................................................... B-20
`CAM memory region size ........................................................................................ B-23
`Access permission bit setting .................................................................................. B-23
`Miss and fault encoding .......................................................................................... B-24
`RAM2 memory region size ...................................................................................... B-25
`Write TLB lockdown operations .............................................................................. B-25
`
`Table 11-9
`Table 11-10
`Table 11-11
`Table 11-12
`Table 11-13
`Table 11-14
`Table 11-15
`Table 11-16
`Table 11-17
`Table 11-18
`Table 11-19
`Table 11-20
`Table 11-21
`Table 11-22
`Table 11-23
`Table 12-1
`Table 12-2
`Table 12-3
`Table 13-1
`Table 13-2
`Table A-1
`Table A-2
`Table A-3
`Table A-4
`Table A-5
`Table A-6
`Table B-1
`Table B-2
`Table B-3
`Table B-4
`Table B-5
`Table B-6
`Table B-7
`Table B-8
`Table B-9
`Table B-10
`Table B-11
`Table B-12
`Table B-13
`Table B-14
`Table B-15
`Table B-16
`Table B-17
`Table B-18
`Table B-19
`Table B-20
`Table B-21
`
`ARM DDI 0151C
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`ix
`
`

`

`List of Tables
`
`x
`
`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`ARM DDI 0151C
`
`

`

`List of Figures
`ARM920T Technical Reference Manual
`
`Figure 1-1
`Figure 2-1
`Figure 2-2
`Figure 2-3
`Figure 2-4
`Figure 2-5
`Figure 2-6
`Figure 2-7
`Figure 2-8
`Figure 2-9
`Figure 2-10
`Figure 3-1
`Figure 3-2
`Figure 3-3
`Figure 3-4
`Figure 3-5
`Figure 3-6
`Figure 3-7
`Figure 3-8
`Figure 3-9
`Figure 3-10
`Figure 3-11
`
`Key to timing diagram conventions .......................................................................... xviii
`ARM920T functional block diagram .......................................................................... 1-3
`CP15 MRC and MCR bit pattern ............................................................................... 2-7
`Cache type register format ........................................................................................ 2-8
`Dsize and Isize field format ....................................................................................... 2-9
`Register 7 MVA format ............................................................................................ 2-18
`Register 7 index format ........................................................................................... 2-19
`Register 8 MVA format ............................................................................................ 2-20
`Register 9 ................................................................................................................ 2-21
`Register 10 .............................................................................................................. 2-23
`Register 13 .............................................................................................................. 2-24
`Address mapping using CP15 Register 13 ............................................................. 2-25
`Translation table base register .................................................................................. 3-6
`Translating page tables ............................................................................................. 3-7
`Accessing translation table level one descriptors ..................................................... 3-8
`Level one descriptor .................................................................................................. 3-9
`Section descriptor ................................................................................................... 3-10
`Coarse page table descriptor .................................................................................. 3-11
`Fine page table descriptor ....................................................................................... 3-12
`Section translation ................................................................................................... 3-14
`Level two descriptor ................................................................................................ 3-15
`Large page translation from a coarse page table .................................................... 3-17
`Small page translation from a coarse page table .................................................... 3-18
`
`ARM DDI 0151C
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`Copyright © 2000, 2001 ARM Limited. All rights reserved.
`
`xi
`
`

`

`List of Figures
`
`Figure 3-12
`Figure 3-13
`Figure 3-14
`Figure 4-1
`Figure 5-1
`Figure 5-2
`Figure 5-3
`Figure 5-4
`Figure 5-5
`Figure 6-1
`Figure 6-2
`Figure 6-3
`Figure 6-4
`Figure 6-5
`Figure 6-6
`Figure 6-7
`Figure 6-8
`Figure 6-9
`Figure 6-10
`Figure 7-1
`Figure 7-2
`Figure 7-3
`Figure 7-4
`Figure 7-5
`Figure 7-6
`Figure 7-7
`Figure 9-1
`Figure 9-2
`Figure 9-3
`Figure 9-4
`Figure 9-5
`Figure 9-6
`Figure 9-7
`Figure 9-8
`Figure 9-9
`Figure 9-10
`Figure 9-11
`Figure 9-12
`Figure 9-13
`Figure 9-14
`Figure 9-15
`Figure 9-16
`Figure 9-17
`Figure 10-1
`Figure 11-1
`Figure 11-2
`Figure 12-1
`
`Tiny page translation from a fine page table ........................................................... 3-19
`Domain access control register format ................................................................... 3-23
`Sequence for checking faults .................................................................................. 3-25
`Addressing the 16KB ICache .................................................................................... 4-5
`ARM920T clocking .................................................................................................... 5-2
`Synchronous mode FCLK to BCLK zero phase delay .............................................. 5-5
`Synchronous mode FCLK to BCLK one phase delay ............................................... 5-5
`Asynchronous mode FCLK to BCLK zero cycle delay .............................................. 5-6
`Asynchronous mode FCLK to BCLK one cycle delay ............................................... 5-7
`Output buffer for bidirectional signals .............................