`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`________________________________
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________________________
`
`
`ADVANCED MICRO DEVICES, INC.
`
`Petitioner
`
`
`v.
`
`
`AQUILA INNOVATIONS INC.
`
`Patent Owner
`
`________________________________
`
`
`
`Case No. IPR2019-01526
`Patent No. 6,895,519 B2
`________________________________
`
`
`
`DECLARATION OF DR. STEVEN A. PRZYBYLSKI
`
`
`
`
`
`AQUILA – Ex. 2005
`
`

`

`
`
`I.
`
`II.
`
`III.
`
`IV.
`
`V.
`
`VI.
`
`TABLE OF CONTENTS
`
`INTRODUCTION ...............................................................................................................3
`
`SUMMARY OF OPINIONS ...............................................................................................4
`
`QUALIFICATIONS ............................................................................................................4
`
`APPLICABLE LEGAL STANDARDS ..............................................................................7
`
`A.
`
`B.
`
`C.
`
`Claim Interpretation .............................................................................. 7
`
`Burden of Proof ..................................................................................... 8
`
`Obviousness ........................................................................................... 8
`
`LEVEL OF ORDINARY SKILL IN THE ART ...............................................................10
`
`THE ’519 PATENT ...........................................................................................................11
`
`VII. CLAIM CONSTRUCTIONS ISSUES ..............................................................................17
`
`A.
`
`B.
`
`The Preamble Is Limiting. ................................................................... 18
`
`The “Plurality Of Ordinary Operation Modes” Operate At
`Different Clock Frequencies Supplied To The CPU. ......................... 18
`
`VIII. REFERENCES ..................................................................................................................19
`
`A. OBER .................................................................................................. 19
`
`B.
`
`NAKAZATO ....................................................................................... 30
`
`IX.
`
`OBVIOUSNESS OF CLAIMS 1, 7, 10 and 11 OVER OBER IN VIEW OF
`NAKAZATO .....................................................................................................................33
`
`A. Ober does not disclose a plurality of ordinary operation modes ........ 33
`
`B.
`
`Ober does not carry out frequency transitions among said
`ordinary operation modes .................................................................... 39
`
`C.
`
`The combination of Nakazato and Ober is not obvious ...................... 48
`
`D. All of claims 2-11 depend directly or indirectly on Claim 1 .............. 51
`
`X.
`
`CONCLUSION ..................................................................................................................51
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`I.
`
`INTRODUCTION
`
`1.
`
`I, Steven A. Przybylski, Ph.D., have been retained by Freitas &
`
`Weinberg LLP on behalf of Aquila Innovations, Inc. as an independent expert in
`
`the field of computer memory technology in this inter partes review no. IPR2019-
`
`01526 of U.S. Patent No. 6,895,519 (which I will refer to in this declaration as “the
`
`’519 patent”).
`
`2.
`
`I understand that the ’519 patent is owned by Aquila Innovations Inc.,
`
`which I understand has sued Advanced Micro Devices, Inc. (“AMD”) for
`
`infringement of the ’519 patent and that AMD filed the IPR petition.
`
`3.
`
`I am being compensated at my standard hourly rate for my work on
`
`this matter, including providing this declaration. My compensation is not
`
`dependent on the outcome of this IPR, the infringement litigation, or any other
`
`proceeding. The compensation I receive in this case does not in any way affect the
`
`substance of my testimony in this declaration.
`
`4.
`
`I have no financial interest in the ’519 patent, Aquila Innovations Inc.,
`
`or any entity affiliated with Polaris Innovations Limited. I do not stand to benefit
`
`or be harmed financially in any way by the outcome of this IPR or the infringement
`
`litigation.
`
`5.
`
`I understand that the Patent Trial and Appeal Board (PTAB) has
`
`ordered trial on all the Challenges AMD has asserted: That claims 1, 7, 10 , and 11
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`-3-
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`

`

`
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`of the ’519 patent are obvious over Ober (U.S. Patent No. 6,665,802, Exhibit 1004)
`
`in view of Nakazato (U.S. Patent No. 6,681,336, Exhibit 1008); that claims 2
`
`through 6 are obvious over Ober in view of Nakazato, Cooper (U.S. Patent No.
`
`6,823,516, Exhibit 1007, and Windows ACPI (Exhibit 1013); and that claims 8 and
`
`9 are obvious over Ober in view of Nakazato and Doblar (U.S. Patent No.
`
`6,516,422, Exhibit 1008).
`
`6.
`
`In preparing this declaration, I have considered the ’519 patent and its
`
`prosecution history, the IPR petition filed by AMD (Paper No. 1), the declaration
`
`of Dr. David Albonesi (Exhibit 1003) filed with the IPR petition, the prior art and
`
`references identified in the petition, my knowledge and expertise in the art, and any
`
`additional materials cited herein.
`
`II.
`
`SUMMARY OF OPINIONS
`
`7.
`
`Based on my review and analysis of the materials in this matter, as
`
`well as my experience and education, in my opinion the Petition fails to show that
`
`any claims of the ’519 patent should be found unpatentable.
`
`III. QUALIFICATIONS
`
`8. My current curriculum vitae (“CV”) is being provided as a separate
`
`exhibit.
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`
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`9.
`
`I earned a Bachelor of Applied Science from the University of
`
`Toronto in 1980. I was enrolled in the Engineering Science program, completing a
`
`course of study combining the Electrical Engineer and Computer Science options.
`
`10.
`
`I earned a Masters of Science in Electrical Engineering degree and a
`
`Ph.D. in Electrical Engineering in 1982 and 1988 respectively, both from Stanford
`
`University.
`
`11.
`
`I also earned a Masters of Business Administration from the Haas
`
`School of Business at the University of California at Berkeley in 2000.
`
`12.
`
`I have extensive experience with memory semiconductor integrated
`
`circuits and the memory systems constructed of them. At Stanford, my dissertation
`
`was on the optimization of single- and multi-level cache hierarchies to maximize
`
`system-level performance. Also at Stanford, I was a member of the core team that
`
`architected, designed, built and tested the seminal MIPS processor. I was
`
`responsible for the design of the instruction decode and control units as well as
`
`architecting the virtual memory support. I assembled and debugged the entire
`
`microprocessor design and oversaw its fabrication and testing. In 1984 and 1985, I
`
`took a leave of absence from Stanford to become a member of the founding team
`
`of MIPS Computer Systems, a startup in California that designed, built, and sold
`
`processors and computer systems. In 1989, after finishing my doctorate and brief
`
`post-doctorate at Stanford, I returned to MIPS Computer Systems. Throughout my
`
`-5-
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`
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`two periods of employment at MIPS Computer Systems, I had a number of titles
`
`and worked on a variety of projects. Noteworthy were stints as processor architect,
`
`systems architect, hardware-software team liaison, and Chief Scientist of the High-
`
`End Systems group. During the second period, I also served as a Consulting
`
`Assistant Professor in the Department of Electrical Engineering at Stanford. I
`
`designed and taught an advanced graduate level course on cache and memory
`
`system design.
`
`13.
`
`In 1991, I left MIPS to become an independent consultant. In that
`
`capacity I have provided technical, strategic, marketing, and intellectual property
`
`services to a large number of clients both domestically and internationally. From
`
`between 1994 and approximately 2000, I was a leading independent analyst
`
`following, writing, and teaching about both the technical and business aspects of
`
`the DRAM industry. Overall, I have written three books and over 25 articles in the
`
`areas of memory, processors, and computer systems. In particular, I wrote and
`
`revised an 850-page book entitled “New DRAM Technologies: A Comprehensive
`
`Analysis of the New Architectures.” I have presented many lectures, classes and
`
`seminars on semiconductor memories and their memory systems, processors and
`
`computer systems. I have presented full and half-day seminars on discrete and
`
`embedded DRAMs to over 2,500 engineers, marketers, managers, and financial
`
`analysts.
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`-6-
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`
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`14.
`
`I am a member of both the Institute of Electrical and Electronics
`
`Engineers (IEEE) and the Association of Computing Machinery (ACM). In
`
`addition, in 1997 I became a registered patent agent. I am listed as the inventor on
`
`11 domestic patents and their foreign counterparts. The subject matters include
`
`memory devices, memory subsystems, networks, error detection and correction
`
`codes, processors and cache memories.
`
`IV. APPLICABLE LEGAL STANDARDS
`
`15.
`
`I will not offer opinions on principles of law because I am not an
`
`attorney. Nonetheless, I understand the following principles of patentability, and I
`
`have used these principles as a framework in arriving at my opinions stated in this
`
`declaration.
`
`A. Claim Interpretation
`
`16.
`
`I understand that a patentability analysis is performed in two steps.
`
`First, the patent claims are interpreted to ascertain their scope. Second, the
`
`interpreted claims are compared to the prior art references.
`
`17.
`
`It is my understanding that claims in an inter partes review
`
`proceeding “shall be construed using the same claim construction standard that
`
`would be used to construe the claim in a civil action under 35 U.S.C. 282(b),
`
`including construing the claim in accordance with the ordinary and customary
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`-7-
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`

`
`
`meaning of such claim as understood by one of ordinary skill in the art and the
`
`prosecution history pertaining to the patent.” 37 C.F.R. § 42.100.
`
`18.
`
`I also understand that this interpretation is from the vantage of one of
`
`ordinary skill in the art at the time of the patent's effective filing date.
`
`B.
`
`19.
`
`Burden of Proof
`
`I understand that the claims in an issued patent are not presumed to be
`
`valid during an IPR, and that the petitioner has the burden to show that a patent
`
`claim is not patentable by the preponderance of the evidence.
`
`C. Obviousness
`
`20.
`
`I understand that for a patented invention to be obvious under section
`
`103 of the patent law, the challenger must identify prior art references that alone or
`
`in combination would have rendered the claimed invention obvious to one of
`
`ordinary skill in the art at the time of the invention.
`
`21.
`
`I understand that for a claim to be found obvious, every claim
`
`limitation must be found present in the combination of the prior art references.
`
`22.
`
`I understand that the factors that should be assessed in the
`
`obviousness analysis include at least: (1) the scope and content of the prior art; (2)
`
`the differences between the prior art and the claim at issue; (3) the level of ordinary
`
`skill in the art; and (4) objective evidence as indicia of nonobviousness.
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`23.
`
`I further understand that the obviousness inquiry must guard against
`
`slipping into use of hindsight and resist the temptation to read into the prior art the
`
`teachings of the invention in the patent at issue. Isolated elements from the prior art
`
`should not be picked and chosen and then combined using the invention as a
`
`blueprint if such a combination would not have been obvious at the time of the
`
`invention. In other words, it is impermissible to use the patent as a template (or
`
`reason) for combining prior art references because that would be applying
`
`hindsight. The ordinary skilled artisan would have to have a reason to combine the
`
`references to create the claimed invention independent of the patent.
`
`24.
`
`It is my understanding that a reason must be shown that would have
`
`prompted a person of ordinary skill in the art to have combined known elements in
`
`the fashion claimed by the patents at issue. Combinations on obviousness grounds
`
`cannot be sustained by mere conclusory statements; instead, there must be some
`
`articulated reasoning with some rational underpinning to support the legal
`
`conclusion of obviousness.
`
`25.
`
`I understand that prior art references as a whole need to be considered,
`
`including aspects that teach away from a claimed invention or that may rebut
`
`showing of obviousness.
`
`26.
`
`I understand that if a combination of two or more prior art references
`
`are used to render a claimed invention obvious, there must be a reasonable
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`
`
`expectation of success in making or practicing the claimed invention based on their
`
`combination. I also understand that the combination cannot modify a prior art
`
`reference such that it would render a reference unsatisfactory for its intended
`
`purpose or change the principle of operation of a reference.
`
`27.
`
`I understand that in making a determination on obviousness, one must
`
`also consider secondary considerations or objective evidence, if present, that may
`
`indicate nonobviousness. I understand that these secondary considerations help
`
`illuminate the subjective determination involved in the hypothesis used to draw the
`
`legal conclusion of obviousness based upon the first three obviousness inquiries.
`
`28.
`
`I have not considered objective evidence of nonobviousness in this
`
`case, but I recognize that there may be such evidence, which would further support
`
`my opinion that the claims of the ’519 patent are not obvious.
`
`V. LEVEL OF ORDINARY SKILL IN THE ART
`
`29.
`
`I have considered what was reasonably known by one of ordinary skill
`
`in the art as of the effective filing date of the ’519 patent, which I understand to be
`
`February 2002. My opinions in this declaration about what a person of ordinary
`
`skill in the art knows or thinks are meant to be as of this date, even if I do not
`
`explicitly say so.
`
`30.
`
`I have firsthand knowledge of the state of the art at that time. During
`
`the period 1994 - 2002, I was a leading independent industry analyst following the
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`
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`DRAM industry, commenting on the technology and business aspects of the
`
`substantial changes taking place at the time. In the context of that role, I was very
`
`familiar with the use of inversion encoding and of error correction codes in
`
`memory subsystems and in communications applications generally.
`
`31. Before the priority date of the patent at issue, I had received a Ph.D.,
`
`taught memory system design to graduate students, designed memory systems and
`
`related parts of high-performance computers, and written extensively on these and
`
`related subject.
`
`32.
`
`In this declaration, I am applying the definition of the level of
`
`experience of a person of ordinary skill in the art that has been put forward by Dr.
`
`Albonesi in his declaration (¶ 35). I do not necessarily agree with the definition
`
`offered there, but I do not presently believe that the exact level of experience of a
`
`person of ordinary skill impacts my opinions offered herein. However, I reserve
`
`the right to offer a different definition at a later point in this case, if necessary.
`
`VI. THE ’519 PATENT
`
`33. The ’519 patent is about power management in an integrated circuit,
`
`also known as an “LSI,” comprising a variety of different subunits, at least one of
`
`which is processor including a CPU core.1
`
`1 In the art, the terms “processor”, “central processing unit”, “CPU”, and “core” are
`
`
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`-11-
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`
`
`
`Ex. 1001 Figures 1 and 2. The ’519 patent also discloses a specific set of
`
`mechanisms by which the power level/clock frequency of various components of
`
`used somewhat interchangeable. In the ’519, the usage though is clear, and I will
`
`conform my use of those terms to the way they are used in the specification except
`
`when referring to specific numbered entities in one of the cited references.
`
`Specifically, the processor 511 is a top-level structure that includes a core CPU
`
`512 for executing instructions and at least the first level caches 513 and 514. The
`
`processor is connected to the rest of the System LSI through a CPU bridge 520.
`
`According to this rubric then, a system LSI could have multiple processors and
`
`each processor could have multiple cores if they shared a cache structure.
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`-12-
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`
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`the System LSI can be controlled, through an application program that interacts
`
`with the hardware registers through a clock control library. Ex. 1001 at Figure 6,
`
`Abstract, 3:35-55, 14:20-22, 14:35-39. Most of the critical elements are evident in
`
`the illustrative and independent claim 1:
`
`1. A system LSI having a plurality of ordinary operation modes and a
`
`plurality of special modes in response to clock frequencies supplied to
`
`a central processing unit, comprising:
`
`a first memory that stores a clock control library for controlling a
`
`clock frequency transition between said ordinary operation modes;
`
`a system control circuit which has a register, wherein said system
`
`control circuit carries out the clock frequency transition between said
`
`ordinary operation modes and said special modes in response to a
`
`change of a value in said
`
`register, and also carries out the clock frequency transition among
`
`said ordinary operation modes in response to said clock control
`
`library;
`
`a clock generation circuit that receives a plurality of standard clocks,
`
`wherein said clock generation circuit generates a clock supplied to
`
`said central processing unit according to control by said system
`
`control circuit; and
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`-13-
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`
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`a second memory that stores an application program, wherein calling
`
`of said clock control library and changing of said register value are
`
`programmably controlled by said application program to enable user
`
`selectable clock frequency transitions,
`
`wherein said special modes comprise a first special mode in which
`
`clock supply to principal constituents of said central processing unit is
`
`halted, a second special mode in which clock supply to an entirety of
`
`said central processing unit is halted, and a third special mode in
`
`which supply of power to the entirety of said central processing unit is
`
`halted.
`
`34. Functional units within the System LSI of particular note are the
`
`system control circuit 534, the clock generation circuit 558, and the power down
`
`control circuit 556, and the internal and external buses 521. Ex. 1001 at 6:17-46.
`
`35. The principle disclosed and claimed mechanism for moderating the
`
`power of the system LSI is by reducing the frequency of the CPU or by suspending
`
`execution of instructions altogether. Ex. 1001 at Abstract, 1:20-26, 1:63-2:9. The
`
`CPU 512 in the processor 510 has a number of different modes of operation.
`
`Special modes are ones in which the CPU is stopped and does not execute
`
`instructions. These are a halt mode (in which clock is stopped “to the principal
`
`constituents of the CPU 510”), and a stop mode in all clocks through the CPU 510
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`-14-
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`

`
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`are stopped. The CPU is placed into one of these two modes by software writing
`
`into a special clock halt register 564. Ex. 1001 at 7:28-37, 9:19-26. In this
`
`embodiment, there are 5 ordinary operating modes ST0 through ST4, characterized
`
`by the principal clock operating at different frequencies. Ex. 1001 at Figure 5, 9:7-
`
`17, 9:46-10:17. There are also 3 special modes (Halt, Stop and Sleep) all
`
`characterized by the suspension of execution of instructions. Ex. 1001 at 10:30-
`
`11:5. A POSITA reviewing the ’519 patent would understand that central to the
`
`distinction between ordinary operation modes and the special modes is the
`
`execution of instructions in the former and the absence of execution in the latter.
`
`Ex. 1001 at Figure 5, Figure 10, 4:7-11, 9:12-17, 9:46-10:17, 10:30-11:5, 13:49-53.
`
`36. Another essential aspect of the disclosure of the ’519 is that the
`
`different ordinary operation modes operate at different frequencies that are
`
`supplied to the processor, and that a transition from one ordinary operating mode
`
`to another is effected by making a clock frequency transition of the principal
`
`processor clock from one frequency to another. Ex. 1001 at Figure 5, 7:60-8:29,
`
`9:46-10:9, 14:15-25,
`
`37. The specification refers to the function in the library that effects the
`
`change from one ordinary mode in which the processor is operating at one
`
`frequency to another ordinary mode in which the processor is operating at a
`
`different frequency as a clkgear function:
`
`-15-
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`
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`Furthermore, when expressing the relation between the current
`clock state and the clock state after transition by using a function
`(clkgear) in the form of the clock control library, it becomes
`possible to dynamically and speedily control a plurality of clocks
`in the ordinary operation mode, as if it were a gear-change
`operation.
`Ex. 1001 at 4:12-17. See also Ex. 1001 at 4:38-44, 8:60-9:6, 9:64-10:4, 11:33-38.
`
`38. The ordinary modes are also selected by writing values into a register.
`
`Ex. 1001 at 8:57-65. The frequency of operation of the core CPU in each of the
`
`ordinary operation modes corresponds to the frequency of a one of a plurality of
`
`clock signals MCLK0, MCLK1, MCLK2 provided to the clock generation circuit
`
`558 which generates the FCLK clock signal to the CPU. Ex. 1001 at Figure 4,
`
`3:65-4:11.
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`-16-
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`

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`
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`Ex. 1001 at Figure 4.
`
`VII. CLAIM CONSTRUCTIONS ISSUES
`
`
`
`39.
`
`I understand that Petitioners have argued that in the present matter the
`
`following terms need to be construed: “system LSI”, “a clock control library for
`
`controlling a clock frequency transition between said ordinary operation modes”,
`
`and “principal constituents of said central processing unit”. Paper No. 1 at 13-15.
`
`Patent Owners have suggested that these terms do not need to be construed in order
`
`to resolve this dispute.
`
`40.
`
`I agree. I believe that a POSITA, reading the specification and claims
`
`of the ’519 and affording each of these terms their plain and ordinary meaning in
`
`-17-
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`

`
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`light of the patent would understand the scope of the claims according to the
`
`intentions of the inventors.
`
`A. The Preamble Is Limiting.
`41. A related issue is whether the preamble of claim 1 should be limiting.
`
`The preamble of claim one includes the phrases “a system LSI”, “a plurality of
`
`ordinary operation modes”, “a plurality of special modes”. These are necessary to
`
`“breathe life into the claim”, and therefore I believe that the preamble of claim 1
`
`should be considered limiting.
`
`B.
`
`The “Plurality Of Ordinary Operation Modes” Operate At
`Different Clock Frequencies Supplied To The CPU.
`42. One of the elements of the preamble is the plurality of ordinary
`
`operation modes. Dr. Albonesi acknowledges that “the claimed ordinary operation
`
`modes operate at different frequencies.” Ex. 1003 ¶ 102. However, it is clear that
`
`merely providing a clock that can toggle at a variety of frequencies is not adequate
`
`to show a plurality of ordinary operation modes. Indeed, “ordinary operation” is a
`
`necessary prerequisite--the execution of programs at each of the provided plurality
`
`of different frequencies. Therefore, a person of ordinary skill in the art at the time
`
`of the invention would have understood “a plurality of ordinary operation modes”
`
`to require that the CPU execute instructions at a plurality of different frequencies.
`
`-18-
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`
`VIII. REFERENCES
`
`A. OBER
`
`43. Ober is central to the challenges offered by the Petitioner, playing a
`
`central role in each of them. Ober is titled “Power Management And Control For A
`
`Microcontroller.” It describes a power management system for a specific
`
`microcontroller that includes a Core 22 (also referred to as CPU core 22, and just
`
`CPU), a variety of I/O peripherals (e.g. 30, 32, 34, 36, 38, 40), and internal flexible
`
`peripheral bus FPI bus 24. The integrated circuit also includes a management
`
`subsystem 26 that generates and controls clocks and various control signals to the
`
`Core 22 and the peripherals. Ex. 1004 at Figure 1, 5:28-53.
`
`
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`-19-
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`
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`Ex. 1004 at Figure 1.
`
`44. The central teaching of Ober is that centralized power management in
`
`a microcontroller is problematic. In a microcontroller with a plurality of
`
`peripherals on the same integrated circuit as the processor, controlling the power
`
`centrally means that all of the peripherals are subject to the same power control
`
`policy, even if that policy might not work well for a specific peripheral at a
`
`specific time. Ex. 1004 at 1:22-2:39.
`
`45. The power management mechanism disclosed in Ober is therefore
`
`limited in its focus to solving this problem. Specifically, Ober provides
`
`decentralized control of the power settings of the peripherals, but only limited
`
`control of the power and speed of the processor and the microcontroller as a whole.
`
`In particular, the microcontroller includes a management subsystem 26, shown in
`
`Figure 2, which determines the overall power management policy. It includes a
`
`clock subsystem 64 for generating a master clock (called “System Clock” or just
`
`“Clock”) that is sent to all principal units within the microcontroller 20 and a
`
`Management Clock internal to the management subsystem 26. Ex. 1004 at 5:21-
`
`6:18.
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`-20-
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`
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`
`
`Ex. 1004 at Figure 2.
`
`46. The power management subsystem 26 also includes a power manager
`
`28 which controls the power modes of the microcontroller by means of a Power
`
`Management State Machine (PMSM). The power management subsystem 26 also
`
`includes a programmable special function register (SFR) 62 that allows software
`
`running on the CPU core 22 to control the power manager 28 and the clock
`
`subsystem 64. Ex. 1004 at 5:59-5:64, 7:41-46. The SFR register is intended for use
`
`during boot up. Ex. 1004 at 7:43-44.
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`-21-
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`
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`47. The power manager 28 defines a handful of power modes that the
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`microcontroller can be in, and a finite state machine that controls the transitions
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`between those modes. The modes are RUN MODE (during which the Core 22 is
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`executing code and all the peripherals can be active), IDLE MODE (during which
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`the Core 22 halted, but the peripherals are potentially active), SLEEP MODE
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`(during which the Core 22 can be powered down) and DEEP SLEEP MODE (a
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`deeper form of SLEEP). Ex. 1004 at Table 9, 12:41-16:67. The Power
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`Management State Machine defines states in which the microcontroller is in each
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`of these principal modes as well as transitional states that the power manager is in
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`moving from one mode to another. Ex. 1004 at Figure 6, 17:1-19:36.
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`48. SLEEP mode is actually divided into three submodes – sleep with
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`clock distributed, sleep with no clock distributed, and deep sleep, in which power
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`may be disabled. Ex. 1004 at 15:40-43. In all of the SLEEP modes the CPU is
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`IDLE i.e. not executing programs. Ex. 1004 at 8:41-43. In “SLEEP MODE (Clocks
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`Distributed),” “the phase lock loop (PLL) or oscillator (OSC) clock is distributed
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`to the subsystems which have been preconfigured to operate in the SLEEP mode.”
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`Id. at 14:61-64. The individual peripheral subsystems may be on or off, as
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`configured in their respective SFR 116. See Ex. 1004 at Table 4 (Sleep Mode
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`Enable, Sleep Divide Clock bits in peripheral special function register 116). The
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`system clock provided to active peripheral devices in SLEEP mode may be divided
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`-22-
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`

`

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`by any power of 2 up to 128, as configured in the SlpClk bits of the power
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`management SFR 62. This means that the power level to the peripherals may vary.
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`Ex. 1004 at Tables 5, 7. The CPU remains in an IDLE state during SLEEP mode,
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`that is the CPU core has flushed its pipeline, and does not receive a clock supply.
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`Id. at 8:39-45.
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`49.
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`In SLEEP MODE (Clocks Not Distributed), the CPU is IDLE and
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`may also be unpowered. This mode is triggered when “the CPU core 22 sets the
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`power management state machine software configuration register SFR 62 Request
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`Sleep REQSLP bit to SLEEP and the clock source bits and no distribution of clock
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`as indicated in Table 5.” Ex. 1004 at 16:29-33. The power management subsystem
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`halts the clocks to all of the peripheral subsystems.
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`50. The CPU is clock is explicitly shut off within the Core 22 by the
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`assertion of the Sleep or Idle signals from the Management Subsystem 26 and
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`during IDLE and SLEEP modes. Ex. 1004 at Table 8, Table 9, 15:14-18, 15:46-47,
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`16:12-13. It is only during RUN MODE that the CPU Core 22 executes programs.
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`Consequently, it is only during RUN MODE that any of the special SFR registers
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`can be written.
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`51. The clock subsystem 64, shown in Figure 3, generates the System
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`Clock (Clock) and the local Management Clock. The System Clock is principally
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`derived from a single crystal oscillator by way of a PLL that multiplies the crystal's
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`-23-
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`

`

`
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`frequency, and a clock circuit 108 that divides the frequency down again to
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`generate the frequency that is required by the CPU Core 22. Ex. 1004 at 8:53-64,
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`Table 2. The specification of Ober only refers to “the clock speed of the CPU” in
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`the singular, indicating that CPU core has a single operating frequency: Ober does
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`not contemplate the CPU core 22 operating at more than one frequency. Ex. 1004
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`at 8:59, Table 7. Also, in discussions relating to the control of the operating state of
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`the CPU core 22 by the management subsystem 26 and the power management
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`state machine (PMSM), there is no discussion of reducing the CPU core's operating
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`frequency to reduce the operating power of the core. Ex. 1004 at 8:35-49; 15:14-
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`16, 17:1-26. Additional evidence of this is in the section “Power Management
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`Modes” beginning at Ex. 1004 at 12:41, where the RUN state is not listed as one of
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`the states in which power management takes place. Also, Tables 7 and 8 make
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`clear that during the RUN mode, the only possible source for the System Clock is
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`the Divided PLL Output, the output of block 108. Ex. 1004 at Tables 7 and 8. The
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`control registers offer no avenue for controlling the PLL multiplier at all nor any
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`facility for controlling the Clock circuit 108 divisor during RUN MODE (see
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`below). Ex. 1004 at Figure 5, Table 5. Per the description of the PMSM, low speed
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`clocks are disabled in the RUN state. Ex. 1004 at 12:10-67, 17:1-27. Since the
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`RUN MODE is the only mode in which program execution can occur in the Core
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`22 and there is only a single frequency of operation in that mode, it is the only
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`-24-
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`

`

`
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`ordinary operational mode. Further, since the frequency of System Clock is not
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`controllable by the SFR 62 during RUN MODE (again, see below), the only power
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`level during the only ordinary operation mode is full power, based on “the clock
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`speed of the CPU core 22.” Ex. 1004 at Tables 7, 8 and 9, 8:56-61.
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`
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`Ex. 1004 at Figure 3.
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`52. The clock subsystem 64 also generates a Management Clock, output
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`from the Management Clock block 110. The Management Clock is internal to the
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`management subsystem 26. It can be derived from a number of different sources,
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`including the System Clock or the low frequency Real Time Clock. Table 7 shows
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`that the even though the Management Clock can be derived from a greater number
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`-25-
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`

`

`
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`sources, during the RUN state both these clocks are taken from the Divided PLL
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`Output. Ex. 1004 at 8:53-9:18.
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`53. The SFR register 62 in the management subsystem 26 is described in
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`relation to Figure 5 and Table 5. This register is used by software to control the
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`power manager 28 and the clock subsystem 64. It is distinct from the plurality of
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`peripheral interface power control registers 116 illustrated in Figure 4 and Table 4,
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`discussed in greater depth below. Ex. 1004 at 10:10-11:33, 9:22-10:5.
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`
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`Ex. 1001 at Figure 5.
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`54. Table 5 describes each of the fields in the SFR Register 62. Ex. 1001
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`at 10:18-11:30. Most significant of these fields are the ReqSlp (Request Sleep),
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`ClkSrc (Clock Source During Sleep) and SlpClk (Sleep Clock). The ReqSlp
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`(Request Sleep) field initiates transition from the RUN power management state to
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`one of the low power states: setting this field to Idle Request