Trials@uspto.gov
`571-272-7822
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` Paper 37
` Date: March 10, 2021
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`
`v.
`
`AQUILA INNOVATIONS, INC.,
`Patent Owner.
`____________
`
`Case IPR2019-01526
`Patent 6,895,519 B2
`____________
`
`
`Before SALLY C. MEDLEY, DENISE M. POTHIER, and
`AMBER L. HAGY, Administrative Patent Judges.
`
`POTHIER, Administrative Patent Judge.
`
`
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`Denying Patent Owner’s Motion to Exclude
`37 C.F.R. § 42.64
`
`
`
`
`571-272-7822
`
`
` Paper 37
` Date: March 10, 2021
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`ADVANCED MICRO DEVICES, INC.,
`Petitioner,
`
`v.
`
`AQUILA INNOVATIONS, INC.,
`Patent Owner.
`____________
`
`Case IPR2019-01526
`Patent 6,895,519 B2
`____________
`
`
`Before SALLY C. MEDLEY, DENISE M. POTHIER, and
`AMBER L. HAGY, Administrative Patent Judges.
`
`POTHIER, Administrative Patent Judge.
`
`
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`Denying Patent Owner’s Motion to Exclude
`37 C.F.R. § 42.64
`
`
`
`
`
`IPR2019-01526
`Patent 6,895,519 B2
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`I. INTRODUCTION
`Advanced Micro Devices, Inc. (“Petitioner”)1 requested an inter
`partes review of all claims (claims 1–11) in U.S. Patent No. 6,895,519 B2
`(Ex. 1001, “the ’519 patent”). Paper 2 (“Petition” or “Pet.”), 16. Aquila
`Innovations Inc. (“Patent Owner”)2 filed a Preliminary Response. Paper 10
`(“Prelim. Resp.”). With authorization, Petitioner filed a Reply (Paper 11,
`“Prelim. Reply”), and Patent Owner filed a Sur-reply (Paper 12, “Prelim.
`Sur-reply”). Pursuant to 35 U.S.C. § 314, we granted the request and
`instituted inter partes review as to all challenged claims on all grounds
`presented in the Petition. Paper 13 (“Dec. Inst.”). Patent Owner filed a
`Response (Paper 19, “Resp.”), Petitioner filed a Reply (Paper 24, “Reply”),
`and Patent Owner filed a Sur-reply (Paper 26, “Sur-reply”).
`Patent Owner objected to evidence submitted by Petitioner in its
`Petition (Paper 16). Patent Owner filed a Motion to Exclude (Paper 31,
`“Mot. Exclude”), Petitioner filed an Opposition to the Motion to Exclude
`(Paper 32, “Pet. Opp. Mot. Exclude”), and Patent Owner filed a Reply to
`support the Motion to Exclude (Paper 33, “PO Reply Mot. Exclude”).
`A hearing was held on December 11, 2020, and a transcript of the
`hearing is included in the record. Paper 36 (“Tr.”).
`
`
`
`
`1 Petitioner identifies itself and ATI Technologies ULC as the real parties-in-
`interest. Pet. 4.
`2 Patent Owner identifies itself, Wi-LAN Technologies Inc., Wi-LAN Inc.,
`and Quarterhill Inc. as the real parties in interest. Paper 6, 2.
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`We have jurisdiction under 35 U.S.C. § 6(b). For the reasons
`discussed below, we conclude that Petitioner has shown by a preponderance
`of the evidence that claims 1–11 of the ’519 patent are unpatentable. This
`Final Written Decision is issued pursuant to 35 U.S.C. § 318(a).
`A. Related Proceedings
`The parties indicate the ’519 patent is at issue in a pending lawsuit,
`Aquila Innovations Inc. v. Advanced Micro Devices, Case No. 1:18-cv-
`00554-LY (W.D. Tex. filed July 2, 2018). Pet. 74; Paper 6, 2.
`B. The ’519 Patent
`The ’519 patent was filed on September 23, 2002, and claims priority
`to a Japanese application filed on February 25, 2002. Ex. 1001, codes (22),
`(30). The ’519 patent relates to a system large scale integration (LSI). Id. at
`1:7–10. The ’519 patent describes an improved system LSI that overcomes
`various problems in the prior art system LSIs. Id. at 3:21–34. The ’519
`patent discloses “[a] system LSI dynamically and speedily controls clocks of
`various frequencies as used in a wide range of operation modes from high-
`speed to low-speed operation modes, enabling user selection of a system of
`power consumption type most suitable.” Id. at code (57); see also id. at
`3:23–34.
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`Figure 2 below shows an LSI:
`
`
`Figure 2, reproduced above, shows a system LSI (e.g., 550) using a CPU.
`Id. at 5:60–61, Fig. 2. LSI 550 includes CPU 510, ROM 551 for storing a
`clock control library and an application program, system control circuit 534,
`and clock generation circuit 558. Id. at 5:60–61, 6:50–57, 7:9–12, 7:60–67,
`Figs. 2–4. According to the ’519 patent, the LSI’s system control circuit 534
`and clock generation circuit 558 reduce consumed power without losing the
`core CPU’s versatility. Id. at 11:50–54, Figs. 1–5.
`The ’519 patent’s clock control library (e.g., 32 in Figure 6) manages
`power using an application program (e.g., 31 in Figure 6). Id. at 11:61–65,
`Fig. 6. A main library (e.g., 33 in Figure 6) selects one of the libraries (e.g.,
`34 in Figure 6) corresponding with the application program’s state and
`permits transitions between clock operating modes. Id. at 12:2–5, 12:27–30,
`Figs. 6, 8(a). Below, Figure 5 illustrates an example of clock operation
`mode (i.e., eight operation modes STNn (n:integer of 0 through 7)) and the
`state transitions.
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`Figure 5, above, shows clock operation modes and state transitions.
` Id. at 5:66–67, 9:4–8, Fig. 5. Figure 5’s arrows show transitions among
`various states (modes). Id. at 11:18–22, Fig. 5.
`A “clock gear” concept permits transitions between the ordinary
`operation modes (e.g., STN0–STN4). Id. at 9:4–6, 11:33–39, Fig. 5. For
`example, the ’519 patent describes the state transition number becomes (5)
`in Figure 5 when switching the current clock mode from the low-speed
`operation mode (STN3) to the high-speed operation mode. Id. at 13:9–19,
`Fig. 5. Figure 5 further shows five “ordinary operation modes” (e.g., STN0–
`4) and three “special modes” (e.g., STN5–STN7). Id. at 9:46–47, Fig. 5.
`Figure 5’s ordinary operation modes include: (1) an initial operation mode
`(STN0, 25 MHz), (2) a highest-speed operation mode (STN1, 62.5 MHz),
`(3) a high-speed operation mode (STN2, 50 MHz), (4) a low-speed operation
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`mode (STN3, 31.25 MHz), and (5) a lowest-speed operation mode (STN4,
`32.768 MHz). Id. at 9:12–17, 9:38–41, 9:49–10:17, Fig. 5.
`The ’519 patent also describes a prior art microcontroller power
`management that includes four clock operation modes: high-speed operation
`mode (operating at 1/2 of the oscillation frequency), low-speed operation
`mode (operating at 1/4, 1/8, 1/16, and 1/32 of the oscillation frequency
`respectively), wait mode, and halt mode. Id. at 1:63–2:6, 2:61–67, Fig. 10.
`C. Illustrative Claim
`Petitioner challenges all the claims of the ’519 patent. Of the
`contested claims, claim 1 is the only independent claim, and claims 2
`through 11 ultimately depend from claim 1. Below, independent claim 1
`illustrates the claimed subject matter:
`1. A system LSI having a plurality of ordinary operation
`modes and a plurality of special modes in response to clock
`frequencies supplied to a central processing unit, comprising:
`a first memory that stores a clock control library for
`controlling a clock frequency transition between said ordinary
`operation modes [“limitation 1.1”];
`a system control circuit which has a register, wherein
`said system control circuit carries out the clock frequency
`transition between said ordinary operation modes and said
`special modes in response to a change of a value in said
`register, and also carries out the clock frequency transition
`among said ordinary operation modes in response to said clock
`control library [“limitation 1.2”];
`a clock generation circuit that receives a plurality of
`standard clocks, wherein said clock generation circuit generates
`a clock supplied to said central processing unit according to
`control by said system control circuit [“limitation 1.3”]; and
`a second memory that stores an application program,
`wherein calling of said clock control library and changing of
`said register value are programmably controlled by said
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`application program to enable user selectable clock frequency
`transitions [“limitation 1.4”],
`wherein said special modes comprise a first special mode
`in which clock supply to principal constituents of said central
`processing unit is halted, a second special mode in which clock
`supply to an entirety of said central processing unit is halted,
`and a third special mode in which supply of power to the
`entirety of said central processing unit is halted [“limitation
`1.5”].
`
`
`Ex. 1001, 14:15–47.
`D. Instituted Grounds of Unpatentability
`We instituted inter partes review of all challenged claims based on all
`grounds of unpatentability asserted in the Petition, which are as follows:
`Claims Challenged
`35 U.S.C. §
`References
`1, 7, 10, 11
`103(a)3
`Ober,4 Nakazato5
`Ober, Nakazato, Cooper,6
`2–6
`103(a)
`Windows ACPI7
`8, 9
`103(a)
`Ober, Nakazato, Doblar8
`Dec. Inst. 2, 69; Pet. 3–4.
`
`
`3 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. § 103. Changes to § 103 apply to
`applications filed on or after March 16, 2013. Because the ’519 patent has
`an effective filing date before March 16, 2013, we refer to the pre-AIA
`version of § 103.
`4 US 6,665,802 B1, issued Dec. 16, 2003 and filed Feb. 29, 2000 (Ex. 1004).
`5 US 6,681,336 B1, issued Jan. 20, 2004 and filed June 16, 2000 (Ex. 1008).
`6 US 6,823,516 B1, issued Nov. 23, 2004 and filed Aug. 10, 1999
`(Ex. 1007).
`7 Microsoft Corporation (1998), Microsoft Hardware White Paper, Draft
`ACPI Driver Interface Design Notes and Reference (Version 0.91),
`Redmond, WA (Ex. 1005).
`8 US 6,516,422 B1, issued Feb. 4, 2003 and filed May 27, 1999 (Ex. 1006).
`
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`II. DISCUSSION
`A. Principles of Law
`To prevail in its challenges to Patent Owner’s claims, Petitioner must
`demonstrate by a preponderance of the evidence that the claims are
`unpatentable. 35 U.S.C. § 316(e) (2012); 37 C.F.R. § 42.1(d) (2018). A
`patent claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which said subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`question of obviousness is resolved on the basis of underlying factual
`determinations including: (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of ordinary skill in the art; and (4) when in evidence, objective evidence of
`nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`“In an [inter partes review], the petitioner has the burden from the
`onset to show with particularity why the patent it challenges is
`unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
`Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
`petitions to identify “with particularity . . . the evidence that supports the
`grounds for the challenge to each claim”)). This burden of persuasion never
`shifts to Patent Owner. See Dynamic Drinkware, LLC v. Nat’l Graphics,
`Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015) (discussing the burden of proof in
`inter partes review).
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`B. Level of Ordinary Skill in the Art
`Petitioner describes the level of ordinary skill as follows:
` [a] person of ordinary skill in the art . . . would have a B.S.
`degree in Electrical Engineering, Computer Engineering, or an
`equivalent field as well as at least 3 to 5 years of academic or
`industry experience in computer systems architecture or
`computer chip design, or comparable industry experience.
`
`Pet. 16. The testimony of David H. Albonesi, Ph.D (Ex. 1003, “Albonesi
`Declaration”) presents a similar level of ordinary skill. Ex. 1003 ¶ 35.
`Patent Owner does not set forth an ordinary artisan’s skill level.
`See generally Resp. The testimony of Steven A. Przybylski, Ph.D.
`(Ex. 2005, “Przybylski Declaration”) states that he “do[es] not necessarily
`agree with the definition offered” but is “applying the definition of the level
`of experience of a person of ordinary skill in the art that has been put
`forward by Dr. Albonesi in his declaration (¶ 35).” Ex. 2005 ¶ 32.
`Having reviewed the arguments and evidence in the full record, we
`adopt Petitioner’s definition above, as we did initially in the Institution
`Decision, as is consistent with the ’519 patent and the asserted prior art.
`C. Claim Construction
`In this inter partes review, claims are construed using the same claim
`construction standard that would be used to construe the claims in a civil
`action under 35 U.S.C. § 282(b). See 37 C.F.R. § 42.100(b) (2019). The
`claim construction standard includes construing claims in accordance with
`the ordinary and customary meaning of such claims as understood by one of
`ordinary skill in the art and the prosecution history pertaining to the patent.
`See id.; Phillips v. AWH Corp., 415 F.3d 1303, 1312–14 (Fed. Cir. 2005).
`
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`1. The Preamble
`Petitioner proposes that we construe the term “system LSI” in the
`preamble of claim 1 to mean “a ‘single integrated chip, which has a CPU
`memory, and I/O capability.’” Pet. 14. Petitioner states that the ’519 patent
`confirms the system LSI includes memory, a CPU, and I/O capabilities. Id.
`(citing Ex. 1001, 5:58–61, 12:34–37, Fig. 2). Relying on Dr. Albonesi’s
`testimony, Petitioner further states an ordinarily skilled artisan would have
`had the same understanding. Id. (citing Ex. 1003 ¶ 77). Later, Petitioner
`states “to the extent the preamble is determined as limiting” (Pet. 25),
`implying that claim 1’s preamble may not be limiting. See id.
`Patent Owner asserts that the preamble, “[a] system LSI having a
`plurality of ordinary operation modes and a plurality of special modes in
`response to clock frequencies supplied to a central processing unit”
`(Ex. 1001, 14:15–19), is limiting because the preamble is “an essential
`element of the invention.” Resp. 21–22 (citing Bicon, Inc. v. Straumann
`Co., 441 F.3d 945, 952 (Fed. Cir. 2006)). Patent Owner additionally states
`that the preamble provides antecedent bases for the recitations “ordinary
`operation modes,” “special modes,” and “central processing unit” found in
`claim 1’s body, and thus the preamble “is a necessary component of the
`claimed invention.” Id. at 22 (citing Bicon, 441 F.3d at 952). Patent Owner
`further contends that “[a] person of ordinary skill in the art would
`understand ‘a plurality of ordinary operation modes’ to require that the CPU
`execute instructions at different frequencies.” Id. at 24; see also id. at 22–25
`(citing Ex. 1001, 4:12–18, 8:56–65, 11:34–38, 12:37–45, 13:54–60, Fig. 5;
`Ex. 2005 ¶ 35), 27.
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`Petitioner responds that we need not decide whether the preamble is
`limiting because its recitations are not relevant to the obviousness challenge;
`rather, Petitioner contends the parties’ dispute relates to whether Ober and
`Nakazato disclose changing a CPU’s clock frequency or operating at
`different frequencies. Reply 2–3. Patent Owner does not further address the
`construction of claim 1’s preamble in the Sur-reply. See generally Sur-
`reply.
`Upon considering Petitioner’s and Patent Owner’s arguments and
`evidence, we find that the preamble is limiting. Recitations to the “ordinary
`operation modes” and “central processing unit,” as noted by Patent Owner
`(Resp. 22), are found in both claim 1’s preamble (Ex. 1001, 14:15–17) and
`claim’s 1 body (id. at 14:21–22, 14:25, 14:28, 14:32–33). Claim 1’s
`“ordinary operation modes” and “central processing unit” recitations in its
`body thus rely upon and derive antecedent basis from claim 1’s preamble,
`and these recitations in the preamble are essential elements that give
`meaning to claim 1’s invention. See Bicon, 441 F.3d at 952.
`We further find claim 1’s preamble requires “clock frequencies” be
`“supplied to a central processing unit” because the preamble recites “a
`plurality of ordinary operation modes . . . in response to clock frequencies
`supplied to a central processing unit.” Ex. 1001, 14:17–18. However, we do
`not find claim 1’s preamble requires the central processing unit (CPU)
`executes instructions or that the “clock frequencies” differ. Ex. 1001,
`14:15–19. No recitation that the CPU execute instructions is found in the
`preamble.
`Nor do we agree with Patent Owner that this limitation requires the
`“clock frequencies” to differ. See Resp. 23–25. As support for that
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`proposition, Patent Owner points to, inter alia, the testimony of Petitioner’s
`declarant, Dr. Albonesi, to the effect that claim 1’s “ordinary operation
`modes” have two requirements and “the claimed ordinary operation modes
`operate at different frequencies.” See, e.g., id. at 23 (citing Ex. 1003 ¶ 102).
`We find, however, that Dr. Albonesi’s statement that the “ordinary operation
`modes” operate at different frequencies refers to the recitation the “‘clock
`frequency transition[s]’ occur between said ordinary operation modes” in the
`“first memory” limitation of claim 1, not the preamble’s recitation that the
`“clock frequencies [are] supplied to a central processing unit.” Ex. 1003
`¶ 102. We thus disagree with Patent Owner that Petitioner’s evidence
`supports construing the “plurality of ordinary operation modes . . . supplied
`to a central processing unit” in claim 1’s preamble such that the CPU
`executes instructions at various frequencies as argued. We will address
`Patent Owner’s assertions related to varying a clock signal’s frequency
`further below when discussing the “first memory” limitation.
`Also, the passages in the ’519 patent cited by Patent Owner do not
`define or explain the phrase “plurality of ordinary operation modes” as
`having a customary meaning, such that its construction should be limited to
`a CPU that executes instructions at different frequencies, as asserted by
`Patent Owner. See, e.g., Ex. 1001, 4:12–18, 8:56–65, 11:34–38, 12:37–45,
`13:54–60, cited in Resp. 23–25. Notably, the ’519 patent uses the term
`“instructions” twice but not when discussing a CPU executing instructions at
`different frequencies. See id. at 6:23–26, 7:38–42. The Specification
`addresses “control[l]ing a plurality of clocks in the ordinary operation
`mode” (id. at 4:16, 13:59; see id. at 8:60–61) and “control[ling] the clock
`with a lot of frequencies covering the wide range of the operation modes
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`from the high-speed operation mode to the low-speed operation mode based
`on the concept of the clock gear” (id. at 11:35–39; see id. at code (57)). For
`example, the ’519 patent provides details how this may be achieved,
`including using “a function (clkgear)” (id. at 4:14, 9:4–6) or “Clock Gear” to
`transition to the clock state and designating values in memory when
`changing gears (id. at 12:37–45). But claim 1, including its preamble, does
`not recite these details, including a CPU executing instructions at different
`frequencies.
`Dr. Przybylski attempts to distinguish ordinary operation modes from
`special modes based on disclosure in the Specification, contending “[a]
`POSITA[9] reviewing the ’519 patent would understand that central to the
`distinction between ordinary operation modes and the special modes is the
`execution of instructions in the former and the absence of execution in the
`latter.” Ex. 2005 ¶ 35 (citing Ex. 1001, 1:20–26, 1:63–2:9, 4:7–11, 7:28–37,
`9:12–17, 9:46–10:17, 10:30–11:5, 13:14–53, 19:7–17, 19:19–26, 19:46–
`10:17, 10:30–11:5, Figs. 5, 10). We disagree that the ’519 patent makes
`such a distinction. The ’519 patent describes some examples of “operation
`modes” where the CPU does not execute instructions, such as the “wait
`mode” where “the clock of the CPU is halted.” Ex. 1001, 2:3; see Ex. 2005
`¶ 35 (citing Ex. 1001, 1:63–2:9). Both Petitioner (Tr. 34:2–6) and Patent
`Owner (id. at 50:9–20) acknowledged during oral hearing that “wait mode,”
`such as the one addressed in Ober’s column 10, is an ordinary operation
`mode. See also Ex. 1001, 10:10–17 (describing a wait mode as one where
`“the clock supply to the system is not completely halted”). In contrast, claim
`
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`9 A person of ordinary skill in the art.
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`1 of the ’519 recites “a first special mode in which a clock supply to
`principal constituents of said central processing unit is halted” (id. at 14:41–
`43; see also Ex. 1003 ¶ 84, cited in Pet. 14), such that an ordinarily skilled
`artisan would infer that instructions can still be executed by other
`constituents of the CPU in special modes. We thus do not give substantial
`weight to Dr. Przybylski’s testimony in this regard.
`Lastly, in the Decision to Institute, we interpreted “system LSI” in the
`preamble to require “the elements of the claims reside on a chip.” Dec. Inst.
`9. Neither party has indicated that our interpretation was improper and we
`do not find any reason or evidence that now compels any deviation from this
`interpretation.
`Therefore, we determine the preamble is limiting but does not require
`the CPU to execute instructions at different frequencies. We further
`determine the recited “system LSI” in the preamble requires the elements of
`the claims to reside on a chip.
`2. “[A] clock frequency transition between said ordinary operation modes”
`Petitioner states “ordinary operation modes” as recited in claim 1 has
`two requirements, including that the “‘clock frequency transition[s]’ occur
`between said ordinary operation modes.” Pet. 24 (citing Ex. 1001, 14:20–
`22; Ex. 1003 ¶ 102). Dr. Albonesi similarly testifies “claim 1 requires: (1)
`that clock frequency transitions occur between ordinary operation modes . . .
`EX1001, 14:20-22. To state it another way, the claimed ordinary operation
`modes operate at different frequencies.” Ex. 1003 ¶ 102. Patent Owner
`states that “claim 1 requires clock frequency transitions between the
`ordinary operation modes. Petitioner also correctly notes that the ordinary
`operation modes ‘operate’ at different frequencies.” Resp. 23; id. at 22–23.
`
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`We agree with both parties that the recitation “clock frequency
`transition between said plurality of ordinary operation modes” in the “first
`memory” recitation requires the ordinary operation modes to operate at
`different frequencies. The “first memory” recitation in claim 1 recites “a
`clock frequency transition,” which implies the clock frequency undergoes a
`change (e.g., differs) between ordinary operation modes and thus operates at
`different frequencies between the ordinary operation modes. See Ex. 1003
`¶ 102; see also Ex. 2005 ¶ 36. However, we find that the recitation “said
`ordinary operation modes,” for reasons stated above when addressing the
`preamble (§ II(C)(1)), does not require the CPU to execute instructions at
`different frequencies.
`3. “[A] clock control library”
`Petitioner argues the phrase “a clock control library” should be given
`“Patent Owner’s construction of this term from the district court proceeding,
`which is ‘software that controls the change in the frequency of the clock
`signals in the ordinary operation modes.’” Pet. 15 (citing Ex. 1011, 7).
`Patent Owner does not, in this proceeding, offer a construction of this
`phrase. See generally Resp. For purposes of this Final Written Decision, we
`determine that we need not provide an express construction for the phrase
`“clock control library.” That is, as our reviewing court has held, “only those
`terms need be construed that are in controversy, and only to the extent
`necessary to resolve the controversy.” See Vivid Techs., Inc. v. Am. Sci. &
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999); see also Nidec Motor Corp.
`v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir.
`2017) (citing Vivid Technologies in the context of an inter partes review).
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`In sum, we agree the recited “clock frequency transition between said
`plurality of ordinary operation modes” in the “first memory” recitation
`requires the ordinary operation modes to operate at different frequencies.
`We need not determine whether the proper construction of the phrase “clock
`control library” requires software that controls the frequency change of
`clock signals in ordinary operation modes.
`4. Remaining Terms
`Petitioner also provides constructions for the phrase “principal
`constituents of said central processing unit” found in claim 1. Pet. 15.
`Patent Owner does not construe this phrase. See generally Resp. For
`purposes of this Final Written Decision, we determine that we need not
`provide an express construction for this or any other claim terms. See Nidec
`Motor Corp., 868 F.3d at 1017.
`D. Obviousness of Claims 1, 7, 10, and 11
`Over Ober and Nakazato (Ground 1)
`1. Ober (Ex. 1004)
`Ober is a United States patent issued on December 16, 2003, and filed
`on February 29, 2000. Ex. 1004, codes (22), (45). According to Petitioner,
`Ober is prior art under 35 U.S.C. § 102(e). Pet. 12. Patent Owner does not
`dispute Ober’s prior-art status. Ober describes a power management system
`for a microcontroller or System on Chip (SoC) having different subsystems.
`Ex. 1004, code (57), 3:45–47. Ober’s Figure 1 below shows a power
`management architecture for a microcontroller or SoC.
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`Figure 1 above shows a power management architecture for a SoC. Id. at
`3:22–26, Fig. 1. Figure 1 shows a microcontroller that includes CPU core
`22, flexible peripheral interconnect (FPI) bus 24, power management
`subsystem 26, major subsystems 30–40, FPI peripheral interface 42–52, and
`memory banks 54 and 56. Id. at 5:28–53, Fig. 1. CPU core 22 is coupled to
`a system bus (e.g., 24) “to enable the operating system or application
`program to read and write the SFR[10] register in the power management
`state machines as well as the SFRs in each of the FPI peripheral interfaces
`for each of the subsystems.” Id. at 5:31–37, Fig. 1.
`Ober’s power management subsystem 26, illustrated in more detail in
`Figure 2, includes a machine for controlling a central processing unit’s
`(CPU) power mode. Id. at code (57), 3:28–30, 5:38–40, 17:1–5, Figs. 2, 6.
`Ober states the power management subsystem may provide “four power
`modes or states: RUN; IDLE; SLEEP; and DEEP SLEEP.” Id. at 4:16–19;
`id. at 7:65–67, 15:14–16:67, Fig. 6. Table 8 shows the system’s
`configuration during RUN, IDLE, and SLEEP modes (id. at 12:41–13:42),
`
`
`10 Special Function Register.
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`and Table 9 summarizes the power modes, including RUN, IDLE, SLEEP
`(distributed clock) and (no distributed clock), and DEEP SLEEP (id. at
`13:45–15:10).
`Power management subsystem 26 includes power manager 28 with a
`power management state machine, programmable SFR register 62, and clock
`subsystem 64 for generating a system clock signal. Id. at 5:58–64, Fig. 2.
`Ober’s SFR register 62 allows the power management system to be
`configured for specific applications and is illustrated in Figure 5. Id. at
`10:10–13, Figs. 2, 5. The bits’ definitions for SFR register 62 are shown in
`Table 5 and include SlpClk (Sleep clock), which may be divided by 2, 4, or
`128 “during Sleep.” Id. at 10:13–11:12, Fig. 5. Each subsystem 30–40 also
`has a separate SFR register (e.g., 116 in Figure 4), which allows the
`operating system (OS) to control the subsystems during different power
`modes. Id. at 9:20–25, 9:49–51, Fig. 1. The bits’ definition for registers 116
`are shown in Table 4. Id. at 9:27–47, Fig. 4. “A sleep divide clock
`(SDCLK) bit and a divided clock (DIVCLK) bit either disables or provides
`divided clock signal to the subsystem during a SLEEP mode and also may
`provide a divided clock signal to the subsystem during a normal mode.” Id.
`at 9:65–10:2.
`Ober’s clock subsystem 64 may be configured by SFR register 62. Id.
`at 9:4–7. Clock subsystem 64 generates system and management clock
`signals. Id. at 8:52–55, Fig. 3. Main crystal 84 connects to system oscillator
`104 to generate an oscillation frequency. Id. at 8:58–61, Figs. 2–3. Phase
`lock loop (PLL) 106 locks in the oscillation frequency, while clock circuit
`108 divides the oscillation frequency to provide the system clock frequency.
`Id. at 8:61–64, Fig. 3. The system clock signal may be generated by main
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`oscillator 84/PLL or shut down. Id. at 9:6–8. Management clock 110 can be
`derived from three sources, including real time clock (RTC) oscillator 114
`connected to the 32 kHz crystal 86, system clock oscillator 104, or system
`clock signal. Id. at 8:66–9:3.
`
`2. Nakazato (Ex. 1008)
`Nakazato is a United States patent issued on January 20, 2004, and
`filed on June 16, 2000. Ex. 1004, codes (22), (45). According to Petitioner,
`Nakazato is prior art under 35 U.S.C. § 102(e). Pet. 12. Patent Owner does
`not dispute Nakazato’s prior-art status. Nakazato’s Figure 1, reproduced
`below, discloses a computer system.
`
`
`Nakazato’s Figure 1, above, shows a computer system. Ex. 1008, 3:5–7,
`Fig. 1. The above computer system includes CPU 11, main memory 13,
`drive circuit 22, and CPU speed control circuit 152. The OS and various
`programs are loaded in main memory 13. Id. at 4:11–20, Fig. 1.
`
`CPU speed control circuit 152 controls the CPU’s processing speed.
`Id. at 5:44–52, Fig. 1. CPU’s processing speed can be controlled at different
`levels using a CPU throttling function and a GEYSERVILLE function. Id.
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`at 4:20–24. For switching CPU speed, the throttling controller uses the CPU
`throttling function, and the frequency/voltage controller uses the
`GEYSERVILLE function. Id. at 5:45–6:18. With either function, the CPU
`speed can be switched by writing necessary data in the internal register of
`CPU speed control circuit 152. Id. at 6:19–21.
`
`A power-saving driver/program, running on the OS, executes CPU
`speed control circuit 152 and its variable setting of the CPU’s processing
`speed. Id. at 7:2–6. The power-saving driver controls CPU speed control
`circuit 152 through BIOS or directly without BIOS. Id. at 7:13–15.
`
`The user designates the CPU speed level using the power-saving
`driver. Id. at 4:25–26, 7:16–19. A dedicated program, such as a program-
`saving utility, presents the user with a window, such as shown in Figure 2
`below.
`
`
`Nakazato’s Figure 2, above, shows a CPU speed-setting window. Id. at 3:8–
`9, 7:19–24, Fig. 2. The selected CPU processing speed is recorded in a
`predetermined area (e.g., a registry area) of HDD 161, and the power-saving
`driver can refer to this area. Id. at 7:24–27, 9:34–39.
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`Nakazato describes examples of the CPU processing speed changing.
`
`For example, Nakazato states: (1) the CPU processing speed changes from
`the highest speed to a low speed when the user designates a low speed,
`(2) the CPU processing speed is maintained as the highest speed when the
`user designates a highest speed, and (3) the processing speed changes
`depending on the presence/absence of the AC adapter when the user sets a
`low speed for battery operation and a high speed for an operation by an
`external AC power supply. Id. at 7:64–8:4.
`3. Discussion
`In Ground 1, Petitioner contends claims 1, 7, 10, and 11 are
`unpatentable under 35 U.S.C. § 103(a) as obvious over Ober and Nakazato.
`Pet. 16–51. We are persuaded Petitioner has established, by a
`preponderance of the evidence that claims 1, 7, 10, and 11 are unpatentable
`on this ground.
`
`(a) Claim 1
`(i) Preamble
`Claim 1 recites “[a] system LSI having a plurality of ordinary
`operation modes and a plurality of special modes in response to clock
`frequencies supplied to a central processing unit.” Ex. 1001, 14:15–17. As
`stated in the Claim Construction section, we do not construe this limitation
`to require the ordinary operation modes to operate at different frequencies or
`that the CPU executes instructions at different frequencies. Thus, arguments
`made by Patent Owne
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