`
`Microchip
`Fabficafion
`
`A Practical Guide to Semiconductor Processing
`
`Peter Van Zant
`
`Fourth Edition
`
`New York San Francisco Washington. D.C. Auckland Bogota
`Caracas Lisbon London Madrid Mexico City Milan
`Montreal New Delhi San Juan Singapore
`Sydney Tokyo Toronto
`
`McGraw-Hill
`
`AMD EX1049
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`AMD V. Aquila
`IPR2019-01525
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`AMD EX1049
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`

`Library of Congress Cataloging-in—Puhlication Data
`
`Van Zant, Peter.
`Microchip fabrication : a practical guide to semiconductor processing ! Peter Van
`Zant.—4th ed.
`
`p.
`
`cm.
`
`includes bibliographical references and index.
`ISBN 0-07-135636—3
`
`1. Semiconductors—Design and construction.
`TK7871.85.V36 2000
`621.3815'2—dc21
`
`I. Title.
`
`00-02317
`
`McGraw-Hill
`
`22
`
`A Division ofTbe MchIwHiH Companies
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`written permission of the publisher.
`
`1234567890 DOCIDOC 09876543210
`
`ISBN 0-07-135636-3
`
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`“
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`

`

`Many thanks to Mary DeWitt, my ever patient and supportive
`wife, and my sons, Patrick, Jefi‘rey, and Stephen. They have all
`brought great joy to my life and all have managed to live through
`the demands of my microelectronics career: Thank you.
`
`HIM MU. Hangs:
`
`pg
`.2?
`'s.-‘-:-
`
`stars.
`A..-
`'1,
`_
`"‘
`if“ 11
`.. fifin‘1'_":':
`1
`'3; '- -
`..-': 2-1“:
`1""
`
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`
`e l
`
`a.
`
`
`
`

`

`This material may be protected by Copyright law (Title 17 U.S. Code)
`
`

`

`3% Chapter Thirteen
`
`Introduction
`
`The most common and familiar use of metal films in semiconductor
`
`technology is for surface wiring. The materials, methods, and pro-
`cesses of “wiring” the component parts together is generally referred
`to as metallization or the metallization process. Metallization includes
`all of the steps in the metallization sequence described in Chapter 5.
`
`Conductors-Single Level Metal
`
`In the MSI era metallization was relatively straight forward (Fig.
`13.1), requiring only a single level metal process. Small holes, called
`contact holes or contacts, are etched through the surface layers, to the
`device]circuit component parts. Following contact masking, a thin
`layer (10,000 to 15,000 A) of the conducting metal (mostly aluminum
`or aluminum alloys) was deposited by vacuum evaporation, sputter-
`ing, or CVD techniques over the entire wafer. The unwanted portions
`of this layer are removed by a conventional photomasking and etch
`procedure or by lift-off. This step leaves the surface covered with thin
`lines of the metal that are called leads, metal lines, or interconnects.
`Generally a heat-treatment step, called alloying, is performed after
`metal patterning to ensure good electrical contact between the metal
`and the wafer surface.
`
`Regardless of the structure, a metal system must meet the following
`criteria:
`
`
`
`1.
`Water with
`Doped Raglan:
`
`2.
`Patterning:
`Contact
`Mask
`
`
`
`
`
`3-
`“Wm!“ “Mum“
`Layer
`
`Figure 13.1 Metallization sequence.
`
`4
`
`Pdtlernlng: Metal
`Mask
`
`

`

`Metallizatlon
`
`397
`
`I Good electrical current-carrying capability (current density)
`[-9. Good adhesion to the top surface of the wafer (usually Si02)
`I; I Ease of patterning
`- I Good electrical contact with the wafer material
`
`I High purity
`.- .I Corrosion resistance
`
`' I Long-term stability
`I Capable of deposition in uniform void- and hillock-free films
`'1 .
`.
`.
`.5 I Umform grain structure
`
`Conductors-Multilevel Metal Schemes
`Increasing chip density has placed more components on the wafer sur-
`75' face, which in turn has decreased the area available for surface wiring.
`The answer to this dilemma has been multilevel metallization
`l: _' schemes with two to four individual metal layers (Fig. 13.2). By 2012,
`'- it is expected that chips will carry up to nine wiring levels.1 (A typical
`.-
`two-metal stack is shown in Fig. 13.3.) The stack starts with a barrier
`_-7
`layer formed by silicidation of the silicon surface to produce a lowered
`
`Advanced Multilevel Logic Device
`HDPCVD sm “xx
`Passivallon
`HDPCVD oxide /
`(use. PSG)
`
`PECVD oxide
`
`HDPCVD oxide
`
`PECVD oxide
`
`HDPCVD USGIFSG
`
`HDPCVD ass Hr“ PW
`
`Figure 13.2 Multi-metal level structure. (Courtesy ofSemiconductor International,
`July, 1997)
`
` -
`
`f _
`j‘.‘
`
`_'
`
`"
`
`

`

`398
`
`Chapter Thirteen
`
`
`
`Figure 13.3 Two metal structure. (Courtesy of Semiconductor Services, January 1998)
`
`electrical resistance between the surface and the next layer. Barrier
`layers also prevent alloying of aluminum and silicon if aluminum is
`the conducting material. Next comes a layer of some dielectric mate-
`rial, called an intermetallic dielectric layer (IDL or IMD) that provides
`the electrical isolation between metal layers. This dielectric may be a
`deposited oxide, silicon nitride, or a polyimide film. This layer receives
`a masking step that etches new contact holes, called vies or plugs,
`holes down to the first-level metal. Conducting plugs are created by
`depositing conducting material into the hole. Next the first-level metal
`layer is deposited and patterned. The IMD/plug/metal deposition!pat-
`terning sequence is repeated for the subsequent layers. A multilevel
`metal system is more costly, of lower yield, and requires greater at-
`tention to planarization of the wafer surface and intermediate layers
`to create good current-carrying leads.
`
`Conductors
`
`Aluminum
`
`This section will address the three primary materials used for the
`primary metal interconnection layers. Prior to the development of
`VLSI-level circuits, the primary metallization material was pure alu-
`minum. The choice of aluminum and its limitations are instructive to
`the understanding of metallization systems in general. From an elec-
`trical conduction standpoint, aluminum is less conductive than copper
`
`

`

`Metalllzaflon
`
`399
`
`
`
`
`
`and .gold. Some early metallization schemes used gold. But its high
`.oontact resistance with silicon required a platinum inter layer and a
`top layer of molybdenum to over come gold’s softness. Copper, if used
`as a direct replacement for aluminum, has a high contact resistance
`lflith silicon and raises havoc with device performance if it gets into
`”the device areas. Aluminum emerged as the preferred metal because
`'it'avoids the problems just mentioned. It has a low-enough resistivity
`,--(2.7 all cm),2 and good current-carrying density. It has superior ad-
`‘hBBiOIl to silicon dioxide, is available in high purity, has a naturally
`low contact resistance with silicon, and is relatively easy to pattern
`with conventional photoresist processes. Aluminum sources are pur-
`chased at 5 to 6 “nines” of purity (99.999 to 99.9999%).
`
`
`
`'. Aluminum-silicon alloys
`
`Shallow junctions in the wafer surface presented one of the first prob—
`' lems with the use of pure aluminum leads. The problem came with
`the need to bake aluminum-silicon interfaces to stabilize the electrical
`
`contact. This type of contact is called ohmic because the voltage-
`current characteristics behave according to Ohm’s law. Unfortunately,
`' aluminum and silicon dissolve into each other and at 577°C, there
`‘ exists a eutectic formation point. A eutectic formation occurs when two
`materials heated in contact with each other melt at temperatures
`much lower than their individual melting temperatures. Eutectic for-
`mations occur over a temperature range, and the aluminum-silicon
`eutectic starts to form at about 450°C, the temperature necessary for
`good electrical contact. The problem is that the alloy formation can
`melt down into the silicon wafer. If the surface has shallow junctions,
`the alloy region can extend completely through the junction, shorting
`it out (Fig. 13.4).
`Two solutions to this problem are employed. One is a barrier metal
`layer (see section on barrier metals) that separates the aluminum and
`silicon and prevents the eutectic alloy from forming. The second is an
`alloy of aluminum with 1 to 2% silicon. During the contact heating
`step the aluminum alloys more with the silicon in the alloy and less
`with the silicon from the wafer. This process is not 100 percent effec—
`tive and some alloying between the aluminum and wafer always oc-
`curs.
`
`Aluminum-copper alloy
`
`Aluminum suffers a problem called electromigration. The problem oc-
`curs when long skinny leads of aluminum are carrying high currents
`over long distances, as is the situation on VLSI/ULSI circuits. The
`
`

`

`400
`
`Chapter Thirteen
`
`Excessive Alloy
`
`I A
`
`luminum / Silicon
`malted into Wafer
`
`MW
`
`Aluminum will! Si
`
`W-
`
`- Figure 13.4 Eutectic alloying of
`aluminum and silicon contacts.
`
`Barrier Mauls
`
`current sets up an electric field in the lead that decreases from the
`input side to the output. Also, heat generated by the flowing current
`sets up a thermal gradient along the lead. The aluminum in the lead
`becomes mobile and diffuses within itself along the direction of the
`two gradients. The first effect is a thinning of the lead. In the extreme,
`the lead can become completely separated. Unfortunately, this event
`usually takes place after the circuit is in operation in the field causing
`a failure of the chip. Prevention or moderation of electromigration is
`achieved by depositing an alloy of aluminum and 0.5 to 4%3 copper or
`an alloy of aluminum and 0.1 to 0.5% titanium. Aluminum alloys con-
`taining both copper and silicon are often deposited on the wafer to
`resolve both alloying and electromigration problems.
`Drawbacks of aluminum alloys are an increased complexity for the
`deposition equipment and process and different etch rates, as well as
`an increase in film resistivity compared to the pure aluminum. The
`amount of the increase varies with the alloy composition and heat
`treatments, but can be as much as 25 to 30%.‘
`
`Copper
`
`With individual devices getting smaller and circuits operate faster. At
`the hundred megahertz speed, signals must move fast enough through
`the metal system to prevent processing delays. In this setting, circuit
`speed becomes restricted with aluminum. Longer and smaller cross
`sections required for larger chips increases the resistance of the metal
`wiring system. The small contract resistance between aluminum and
`
`

`

`Matallization
`
`401
`
`
`
`I
`
`.
`:--
`
`. ,l-silicon surfaces add up to a restictive level as the number of circuit
`.. " components grow. While aluminum provides a workable resistance, it
`is difficult to deposit in high aspect ratio vias/plugs. To date, barrier
`.‘metal schemes, stacks, and refractory metals have been employed to
`w'reduce aluminum metal system resistance. Additional resistance re-
`__!.'l_ductions needed for 0.25-um (and smaller) devices has renewed inter-
`fleet in copper as a conducting metal. Copper is a better conductor than
`'i'aluminum with a resistance of 1.7 micro—ohm cm compared to a 3.1
`”3." {micro-ohm cm value for aluminum. Copper13 resistant to electromi-
`I.gration, and can be deposited at low temperatures. 5 It also can be used
`as a plug material. Deposition can be by CVD, sputtering, electroless
`plating, and electrolytic plating. Plasma enhanced CVD (PECVD) is
`"T emerging as an early leader. Drawbacks, besides lack of a learning
`curve, include etching problems, vulnerability to scratching, corrosion,
`.' and the requirement of barrier metals to keep the copper out of the
`:silicon. Nevertheless IBM, followed quickly by Motorola, announced
`the availability of production copper based devices in 1998.6
`The slowing of circuit signals comes from the combination of the
`__ "metal resistance (R) and capacitance (C). It is called the RC constant
`of the system. Copper metallization is envisioned for use with new low
`;_ capacitance (lower dielectric strength or low “11”) dielectrics, such as
`4_ cobalt silicide (COSig). Switching to a copper metal system and a low
`'1, k dielectric could lower the RC constant by 400%.7
`'
`In addition to low-k intermetallic dielectrics copper use is requiring
`the industry to develop dual damascene patterning, and employ CMP
`planarization (Chapter 10). Deposition techniques include traditional
`,' CVD and PVD. There is also the development of electroplating, which
`is a process new to the wafer fabrication business. Plating and dual
`.. damascene are described further on in this chapter.
`
`2'
`
`.
`
`.1.
`
`' Dual damascene process
`
`In Chapter 10, a basic damascene process was introduced. The dam—
`ascene concept is simple. A trench is formed in a surface dielectric
`layer and the required metal deposited into it. Usually the trench is
`overfilled, requiring a CMP step to re-planarize the surface. This pro-
`cess offers superior dimensional control because it eliminates the var—
`iation introduced in a typical metal etch process. The dual damascene
`takes the concept one step further. With copper metallization there is
`no need for a separate plug metal. In the dual damascene process, the
`plug via and the metal trench are formed (Fig. 13.5) in sequence. The
`subsequent metal deposition fills both, forming a complete metal layer.
`In the sequence shown, there is a barrier!seed deposition step. Ac-
`tually these are two separate depositions. First a barrier material is
`
`
`
`

`

`

`

`Metallization
`
`403
`
`_
`'sfifTitanium nitride layers can be placed on the wafer by all the dep-
`"tion techniques: evaporation, sputtering, and CVD. It can also be
`
`tin-u ed by the thermal nitridation of a titanium layer at 600°C in an
`“lg-i,- or NH3 atmosphere.9 CVD titanium nitride layers have good step
`
`' erage and can fill submicron contacts. A layer of titanium is re-
`.
`.‘..
`-u under TiN films to provide a high conductivity intermediate
`
`'_th silicon substrates.
`} With copper metallization, the barrier is also critical. Copper inside
`
`.a' is silicon ruins device performance. Barrier metals used are TiN,
`
`ftantalum (Ta), and tantalum nitride (TaN).10
`
`
`{Although the limitations of electromigration and eutectic alloying
`
`*1 've been made manageable by aluminum alloys and barrier metals,
`__
`- issue of contact resistance may prove to be the final limit on alu-
`
`-. fininum metallization. The overall effectiveness of a metal system is
`.'.: governed by the resistivity, length, thickness, and total contact resis-
`
`.'.;ance of all the metal-wafer interconnects. In a simple aluminum sys-
`'l’xtem, there are two contacts: silicon! aluminum interconnect and the
`
`1'.'.aluminum interconnect/bonding wire. In a ULSI circuit with multi-
`level metal layers, barrier layers, plug fills, polysilicon gates and con-
`.‘
`fiuctors, and other intermediate conductive layers, the number of con-
`.
`-, nections becomes very large. The addition of all the individual contact
`-- resistances can dominate the conductivity of the metal system.
`Contact resistance is influenced by the materials, the substrate dop-
`"ing, and the contact dimensions. The smaller the contact size, the
`.. "higher the resistance. Unfortunately, ULSI chips have smaller contact
`': .".-Openings, and large gate array chip surfaces can be as much as 80%
`L! contact area.11 These two factors make the contact resistance the dom-
`-' inant factor in VLSI metal system performance. Aluminum-silicon
`‘ contact resistance, along with the alloying problem, have led to the
`investigation of other metals for VLSI metallization. Polysilicon has a
`lower contact resistance than aluminum and is in use in MOS circuits
`.
`1 (Fig. 13.6).
`'
`' Refractory metals and their silicides offer lower contact resistance.
`.. The refractory metals of interest are titanium (Ti), tungsten (W), tan-
`" ,
`talum (Ta), and molybdenum (Mo). Their silicides form when they are
`' alloyed on a silicon surface (WSig, TaSiz, MoSi2 and TiSig). The re-
`fi'actory metals were first proposed for metallization in the 1950s, but
`they stayed in the background due to a lack of a reliable deposition
`method. That situation has changed with the development of LPCVD
`and sputtering processes.
`
`
`
`_-
`
`

`

`404
`
`Chapter Thirteen
`
` Poly~Si Gate
`
` Figure 13.6 Silicon gate elec-
`
`Metallization
`and Metal Mad:
`
`trode extended for metallization
`lead.
`
`All modern circuit designs, especially MOS circuits, use refractory
`metals or their silicides as intermediate (plugs), barrier, or conducting
`layers. The lower resistivities and lower contact resistances (Fig. 13.7)
`make them attractive for conducting films, but impurities and depo-
`sition uniformity problems make them less attractive for MOS gate
`electrodes. The solution to the problem has been the polycide and sil-
`icicle gate structures, which are combinations of a silicon gate topped
`by a silicide. The details of this structure are explained in Chapter 16.
`A popular use of refractory metals is the filling of via holes in mul-
`tilevel metal structures. The process is called plug filling and the filled
`via is called a plug (Fig. 13.2). The vias are filled by either selective
`tungsten deposition through surface holes onto the first layer metal
`or by CVD techniques.12 Of the available refractory metals, tungsten
`finds a lot of use as aluminum-silicon barriers, MOS gate intercon-
`nects, and for via plugs.
`One of the attractions of cepper metallization is that copper can be
`the plug material, creating a monometal system which minimizes in-
`ter-metal resistances.
`
`Doped polysilicon
`
`The advent of silicon-gate MOS technology made the use of deposited
`polysilicon lines on the chip a natural consideration for conduction
`leads. For use as a conductor, the polysilicon has to be doped to in-
`crease its conductivity. Generally, the preferred dopant is phosphorus
`due to its high solid solubility in silicon. Doping is by either diffusion,
`ion implantation, or in situ doping during an LPCVD process. Each of
`the methods produces a different doping result. The differences relate
`to the doping temperature’s effect on the grain structure. The lower
`the temperature, the greater the amount of dopant trapped in the
`polygrain structure, where it is unavailable for conduction. This is the
`situation with ion implantation. Diffusion doping results in the lowest
`film sheet resistivity. In situ CVD doping has the lowest dopant carrier
`mobility due to grain boundary trapping.
`
`

`

`Matallization
`
`405
`
`
`
`0.1
`
`02
`
`0.4
`
`1
`
`2
`
`4
`
`10
`
`Deslgn Rule{pm}
`
`Figure 13.? Effect of contact re-
`sistance on RC time constant.
`
`
`. Daped polysilicon has the advantage of a good ohmic contact with
`_'.-the wafer silicon and can be oxidized to form an insulating layer.
`
`‘g-Polysilicon oxides are of a lower quality than thermal oxides grown
`
`u1m single-crystal silicon because of the nonuniformity of the oxide
`lfl'I-grown on the rougher polysilicon surface.
`' While polysilicon has a low contact resistance with silicon it still
`
`exhibits too high a resistance the metal material(s) Creating a mul-
`
`'fimetal stack of the polysilicon and a silicide (such as titanium sili-
`ag-cide). These are called polycide structures (see Chapter 16).
`
`
`Iii-Metal Film Uses
`
`ENDS gate and capacitor electrodes
`,Most electrical devices depend on the passage of an electrical current
`
`.'.,dielectric. In most designs, the top electrode is a section of the con-
`
`_"ductor metal system. A discussion of the relationship of capacitor pa-
`
`- :grameters'13 in Chapter 2.
`
`._
`' MOS transistors are a capacitor structure and the top electrode,
`
`,gcalled a gate, is a critical structure in MOS circuits
`
`
`
`
`-' The development of thin-film fuse technology allowed creation of the
`
`"Programmable read-only memory (PROM) circuit. The fuse allows
`
`fl:field programming of data in the memory section of the chip. In this
`'. ',l'ole the fuseis not a protective device, as in most electrical circuits,
`
`. Ibut is included specifically to be “blown” or disabled.
`3',
`In the memory section of the chip, called the array, are a number
`IOf memory cells, each with a fuse between the cell and the main me-
`
`
`
`

`

`406
`
`Chapter Thirteen
`
`tallization system. The array is essentially a blank blackboard (Fig.
`13.8). Information can be coded into the array in digital form (on/off)
`by having some of the cells operating and others not operating. Non-
`operating cells can be created by blowing the fiise, thus removing it
`from the circuit. The same system is used to program logic arrays. The
`fuse is blown by the heat generated by a high—voltage current (blowing
`current) passing through the narrow neck of the fuse, heating the
`material to the melting point and leaving it disabled (Fig. 13.9). Once
`the fuse is blown, the associated memory cell is permanently removed
`(electrically) from the circuit.
`There are two primary fuse configurations. One consists of thin films
`of nichrome, titanium-tungsten, or polysilicon lying under two metal
`leads, which are patterned with thin “necks” that can be blown by a
`current pulse directed through the metal lines. Another fuse scheme
`
`
`
`* Fuse
`
`El Memory Call
`
`Figure 13.8 Schematic of fused
`memory array.
`
`Blown Fuse
`
`Figure 13.9 Thin film fuses.
`
`

`

`Metallization
`
`407'
`
`employs a thin film of polysilicon or oxide in the contact hole. The fuse
`. is blown when a high current is passed through the layer and destroys
`. it by heating.
`
`.
`
`_
`.
`
` promise aluminum’s role as a conductor. A second requirement for
`
`Backside plating
`
`i 1 Gold is sometimes evaporated onto the entire back of the wafer just
`prior to wafer sort. The gold functions as a solder in certain packaging
`{'12 processes (see Chapter 18).
`
`..
`
`' Deposition Methods
`
`.
`
`"
`
`_. Metallization techniques, like other fabrication processes, have un-
`' derg‘one improvements and evolution in response to new circuit re-
`'- quirements and new materials. The mainstay of metal deposition up
`'.
`to the mid 1970s was vacuum evaporation. Aluminum, gold, and the
`fuse metals were all deposited by this technique. The needs of depos—
`iting multimetal systems and alloys, along with the need for better
`step coverage, led to the introduction of sputtering as the standard
`deposition technique for VLSI circuit fabrication. Refractory metal use
`has added the third technique, CVD, to the arsenal of the metalliza—
`tion engineer. Some of the basic issues of the deposition of metals, by
`all techniques, is discussed in the following section on vacuum evap-
`oration.
`
`Vacuum evaporation
`
`Vacuum evaporation is used for the deposition of metals on discrete
`devices and circuits of lower integration levels. It is also used for the
`deposition of gold to the back of a wafer for die adhesion into a pack—
`age. Vacuum evaporation takes place inside an evacuated chamber
`'g. 13.10). The chamber can be a quartz bell jar or a stainless steel
`3 closure. Inside the chamber is a mechanism to evaporate the metal
`Iource, wafer holders, a shutter, thickness and rate monitors, and
`heaters. The chamber is connected to a vacuum pump(s) (see “Vacuum
`Pumps”).
`Since aluminum is the most critical of the materials evaporated, we
`shall focus on its deposition. The vacuum is required for a number of
`reasons. First is a chemical consideration. If any air (oxygen) mole-
`cules were in the chamber when the high-energy aluminum atoms
`_ were coating the wafer, they would form aluminum trioxide (A1203), a
`' dielectric which, if incorporated into the deposited film, would com-
`
`"f
`
`vacuum deposition is uniform coating. The vacuum required for suc-
`
`

`

`408
`
`Chapter Thirteen
`
`High Vacuum
`5 x 10’5torr
`to
`
`1 x 10710"
`
`Heater -
`
`
`
`
`Bell Jar (Quartz or Stainless Stout)
`
`Planetary Water Holder
`
`
`
`Evaporation Source
`
`Mechanical and
`
`
`Pumps
`
`High Vacuum
`
`Figure 13.10 Vacuum evaporator.
`
`
`
`
`cessful evaporation of aluminum is from 5 X 10‘5 to 1 X 10“9 torr of
`pressure. (See Chapter 2 for a discussion on vacuum and pressure.)
`There are systems that operate in the ultra high vacuum (sub 10‘9
`torr) range.13 They offer the advantage of lowered background contam-
`ination in the system hardware which reduces contamination of the
`wafers.
`
`Evaporation sources. Before describing the various methods of causing
`a metal to evaporate, a review of basic evaporation theory is in order.
`Most of us are familiar with the evaporation of a liquid from a beaker.
`This happens because there is sufficient energy (heat) in the liquid to
`cause the molecules to escape into the atmosphere. Over time some of
`them stay in the atmOSphere; we call this evaporation. The same pro-
`cess of evaporation can be made to occur in solid metals. The require-
`ment is to heat the metal to a liquid state so that the atoms or mol-
`ecules evaporate into the surrounding atmosphere. Three methods are
`used to evaporate metals in a vacuum system. They are
`
`I Filaments
`
`I Electron beam
`
`l Flash hot plate
`
`Filament evaporation is the simplest of the three methods. It is used
`for noncritical evaporation’s such as backside gold layers. The mate-
`rial, in wire form, is either wrapped around a coiled tungsten (or other
`metal that is able to withstand high temperatures) wire. A high cur-
`
`

`

` -‘7' metal to a liquid and evaporates into the chamber, coating the wafers.
`
`Metallization
`
`409
`
`-'
`"
`
`Another version uses a flat filament with a dimple to hold pieces of
`the deposition material.
`'
`Filament evaporation is not very controllable due to temperature
`variations along the filament and contaminants in the source mate—
`
`Alloys are difficult to deposit by this method. Each element has a
`difl'erent evaporation rate at a given temperature. When an alloy, such
`'. as nichrome, is evaporated, the nickel and the chromium each evap-
`.~ crate at different rates. The composition of the film on the wafer will
`'
`' be different than the composition in the starting material.
`.
`The need for evaporation control and low contamination led to the
`development of the electron beam evaporation source (Fig. 13.11) for
`.‘j aluminum. The system is called an E-beam gun or just E-gun. This
`evaporation source consists of a water-cooled copper crucible with a
`1 center cavity to hold the aluminum. At the side of the crucible is a
`»
`'; high-temperature filament. A high current is passed through the fil-
`u 'ament, which, in turn, “boils” off electrons. The negative electrons are
`bent 180° by a magnet so that the electron beam strikes the center of
`the charge in the cavity. The high-energy electrons create a pool of
`-' liquid aluminum in the center of the charge. Aluminum evaporates
`from the pool into the chamber and deposits on the wafers in holders
`I at the top of the chamber. The water cooling maintains the outer edges
`of the charge in a solid state, thus preventing contaminants from the
`copper crucible from evaporating. E-gun evaporation is relatively con-
`trolled for an elemental source such as aluminum or gold. It is less
`useful for the deposition of alloys due to the same limitation as with
`filament evaporation sources, that is, the different evaporation rates
`of different elements. This problem is addressed by adding one or more
`additional e-guns (coevaporation) in the chamber. Each gun will hold
`
`"
`
`'
`
`.
`
`
`
`Crucible - Water Cooler
`
`
`
`Filament
`
`Flume 13.11 Electron gun evaporation source.
`
`

`

`410
`
`Chapter Thirteen
`
`a different material and the power can be adjusted to drt evaporation
`rates.
`
`Film thickness is controlled by shutters and by rate and thickness
`monitors. In-chamber monitors, located near or above the wafer hold-
`ers, feed back information to the E-gun power supply which controls
`the evaporation rate.
`The hot plate, or flash system (Fig. 13.12) was developed to resolve
`some of the problems with the evaporation of alloys with E-gun
`sources. This source consists of a hot plate held at a temperature well
`above the melting point of the particular alloy. A thin wire of the alloy
`is fed automatically onto the hot plate’s surface. Upon contact, the tip
`of the wire melts and the material “flashes” into a vapor and coats the
`wafers in the chamber. Since all of the elements are “flashed” simul-
`
`taneously, the composition of the film on the wafer is very close to the
`composition of the wire.
`A major goal of any metal deposition system is good step coverage
`(Fig. 13.13). This is a challenge for vacuum evaporators because the
`source is essentially a point source. The problem comes when material
`from a point source is shadowed by steps on the wafer surface. The
`result can be that one side of the openings in the surface oxide can be
`too thin or have a void. Planetary wafer “domes” rotating in the cham-
`
`\
`
`0 H
`
`[5I:
`
`Aluminum Alloy Wire
`
`Figure 13.12 Flash evaporation
`source.
`
`ot Plate
`
`Good
`
`[5
`
`Thin at Step
`
`[5
`
`Step Shadowed
`
`Figure 13.13 Step coverage.
`
`

`

`
`
`Metallizatlon
`
`41 1
`
`_""i":-.. are used to create uniform thicknesses (Fig. 13.14). Quartz heaters
`
`'-
`'
`the chamber aid step coverage by maintaining evaporant mobility
`
`the atoms arrive at the surface. They “fill in” the steps by a capil-
`
`action.
`
`
`deposition (PVD)
`
`tter deposition (sputtering) is another old process adapted to sem-
`
`.ductor needs. It is a process first formulated in 1852 by Sir Wil-
`
`.. Robert Grove.“ Sputtering is a process that (in general) can de-
`
`'t any material on any substrate. It is widely used to coat costume
`
`.
`elry and put optical coatings on lenses and glasses. Discussion of
`
`I,‘ e benefits of sputtering to the semiconductor industry is best left
`
`..
`til the principles and methods of sputtering are covered. Sputtering,
`
`'-
`‘ evaporation, takes place in a vacuum. However, it is a physical
`
`“(if-t a chemical process (evaporation is a chemical process), and is re-
`
`fined to as physical vapor deposition (PVD).
`
`’l’ Inside the vacuum chamber is a solid slab, called a target, of the
`
`film material (Fig. 13.15). The target is electrically grounded.
`
`i'l”"1\rgon gas is introduced into the chamber and is ionized to a positive
`
`. ..charge. The positively charged argon atoms are attracted to the
`
`
` h-f
`
`._;. y.
`
`'
`Figure
`holder.
`
`13.14 Planetary wafer
`
`
`
`(9/, o
`l
`
`.-
`9"
`
`Figure 13.15 Principle of sput-
`
`tering.
`
`
`
`

`

`412
`
`Chapter Thirteen
`
`grounded target and accelerate toward it. During the acceleration they
`gain momentum, which is force, and strike the target. At the target,
`a phenomenon called momentum transfer takes place. Just as a cue
`ball transfers its energy to the other balls on a pool table, causing
`them to scatter, the argon ions strike the slab of film material, causing
`its atoms to scatter (Fig. 13.16). The argon atoms “knock off” atoms
`and molecules from the target into the chamber. This is the sputtering
`activity. The sputtered atoms or molecules scatter in the chamber with
`some coming to rest on the wafer. A principal feature of a sputtering
`process is that the target material is deposited on the wafer without
`chemical or compositional change.
`There are several advantages of sputtering over vacuum evapora-
`tion. One is the aforementioned conservation of target material com-
`position. A direct benefit of this feature is the deposition of alloys and
`dielectrics. The problem of evaporating alloys was described in the
`preceding section. In sputtering, an aluminum and 2% copper target
`material yields an aluminum and 2% copper film on the wafers.
`Step coverage is also improved with sputtering. Whereas evapora-
`tion proceeds from a point source, sputtering is a planar source. There
`is material being sputtered from every point on the target with ma-
`terial arriving at the wafer holder with a wide range of angles to coat
`the wafer surface. Step coverage is further improved by rotating the
`wafer holder and by heating the wafer.
`Adhesion of the sputtered film to the wafer surface is also improved
`over evaporation processes. The higher energy of the arriving atoms
`makes for a better adhesion, and the plasma environment inside the
`chamber has a “scrubbing” action5 of the wafer surface that enhances
`adhesion. Adhesion and surfac