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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
`Petitioner
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`v.
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`AQUILA INNOVATIONS, INC.
`Patent Owner
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`Case IPR2019-01525
`Patent 6,239,614 B1
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`DECLARATION OF DR. DOUGLAS R. HOLBERG IN SUPPORT OF
`PETITIONER ADVANCED MICRO DEVICES, INC.’S REPLY TO
`PATENT OWNER’S RESPONSE
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`AMD EX1048
`AMD v. Aquila
`IPR2019-01525
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`
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`IPR2019-01525
`U.S. Patent No. 6,239,614
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`TABLE OF CONTENTS
`INTRODUCTION ...............................................................................1
`I.
`CLAIM CONSTRUCTION ..................................................................3
`II.
`III. GROUND 1: CLAIMS 1-3 ARE OBVIOUS OVER URANO IN
`VIEW OF MUTOH021 ........................................................................4
`A. Mutoh021 discloses “a power switch disposed around said
`unit cell array and comprised of a plurality of third MOS
`transistors, each of the third MOS transistors having the
`second threshold voltage” ............................................................ 4
`B. A POSA Would Have Combined Urano and Mutoh021 with
`a Reasonable Expectation of Success ............................................. 5
`IV. GROUND 2: CLAIMS 1-3 ARE OBVIOUS OVER MUTOH IN
`VIEW OF MUTOH021 ...................................................................... 26
`A.
`PO Does Not Dispute that Mutoh and Mutoh021 Would
`Have Been Readily Combined According to Known
`Methods to Yield Predictable Results .......................................... 26
`THE DEPENDENT CLAIMS ARE UNPATENTABLE FOR THE
`REASONS SET FORTH IN THE PETITION. ...................................... 27
`VI. GROUND 3: CLAIMS 4-5 ARE OBVIOUS OVER DOUSEKI IN
`VIEW OF RAMUS ............................................................................ 28
`VII. CONCLUSION ................................................................................. 29
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`
`V.
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`IPR2019-01525
`U.S. Patent No. 6,239,614
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`I, Dr. Douglas R. Holberg, declare as follows:
`
`I.
`
`INTRODUCTION
`
`1.
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`I have been retained on behalf of Advanced Micro Devices, Inc.
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`(“AMD” or “Petitioner”) for the above captioned inter partes review proceeding. I
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`previously submitted a prior declaration (EX1003) in support of the Petition for
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`inter partes review of U.S. Patent No. 6,239,614 (“the ’614 patent”), which I
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`understand was filed on August 28, 2019.
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`2.
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`I understand that Patent Owner Aquila Innovations, Inc. submitted a
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`Patent Owner Response (“POR”). I have been asked to provide my technical
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`review, analysis, insights, and opinions regarding the POR.
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`3. My background and qualifications were provided in paragraphs 7-14
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`of my prior declaration, and my CV was provided as Exhibit 1004. My statements
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`in paragraphs 32-67 of my prior declaration regarding my review of U.S. Patent
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`No. 6,239,614 (“the ’614 patent”) and related materials remain unchanged, as do
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`my understandings of the relevant legal principles stated in paragraphs 15-31.
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`4. My statements in my original declaration regarding my review of the
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`’614 patent and related materials remain unchanged. In reaching my opinions
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`provided below, I reviewed my original declaration and the materials reviewed as
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`part of my original declaration. In addition, I have reviewed and considered the
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`following materials:
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`Paper/Exhibit
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`IPR2019-01525
`U.S. Patent No. 6,239,614
`DESCRIPTION
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`12
`
`18
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`Institution Decision
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`Patent Owner’s Response
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`EX2002
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`Declaration of Dr. Przybylski
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`EX2004
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`Excerpts from Michael Vai, VLSI Design (2001)
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`EX2005
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`Excerpts from Rabaey et al., Digital Integrated Circuits (2003)
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`EX2006
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`Excerpts from Peter Van Zant, Microchip Fabrication (2000)
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`EX1047
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`Deposition Transcript of Dr. Przybylski
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`EX1049
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`EX1050
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`Chapter 13 of Microchip Fabrication by Van Zant from the 4th
`Edition (2000)
`“Sea-of-gates architecture” by Manoel E.de Lima and David
`J.Kinniment, published on Microelectronics Journal Volume 26,
`Issue 5, July 1995
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`
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`5.
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`In my opinion, the ’614 patent claims nothing more than a layout of a
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`well-known integrated circuit—a multi-threshold complementary metal oxide
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`semiconductor (“MTCMOS”)—and the use of widely known decoupling
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`capacitors. The ’614 patent concedes, and I understand that the Patent Owner
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`(“PO) does not dispute, that MTCMOS devices and each of the claimed features,
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`including placing power switches around a unit cell array of MOS transistors and
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`decoupling capacitors, were already known. EX1001, ’614 patent, 1:14-32; see
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`POR generally. And as I explained in my Declaration, it would have been obvious
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`U.S. Patent No. 6,239,614
`to combine these known teachings according to known methods to yield
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`predictable results and there would have been a reasonable expectation of success,
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`because such a combination would have been applying a known technique to a
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`known device and for a same purpose. EX1003, ¶114-128, 163-171, 205-209. I
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`disagree with each of PO’s arguments.
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`6.
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`For Grounds 1 and 2, I understand that PO’s sole argument is that it
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`would not have been obvious to combine the feature of placing power switches
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`around a unit cell array of MOS transistors clearly taught by Mutoh021 in the
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`circuit of Urano (Ground 1) or Mutoh (Ground 2). I understand that for Ground 3,
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`PO presents only one argument. I disagree with PO’s arguments as explained
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`below.
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`7.
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`Thus in my opinion, claims 1-5 of the ’614 patent are unpatentable.
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`II. CLAIM CONSTRUCTION
`I continue to believe that the constructions presented in the Petition
`8.
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`and in my Declaration are correct. EX1003, ¶¶68-107. But regardless of the
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`construction, in my opinion, the challenged claims are invalid as explained here.
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`U.S. Patent No. 6,239,614
`III. GROUND 1: CLAIMS 1-3 ARE OBVIOUS OVER URANO IN VIEW
`OF MUTOH021
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`A. Mutoh021 discloses “a power switch disposed around said unit
`cell array and comprised of a plurality of third MOS transistors,
`each of the third MOS transistors having the second threshold
`voltage”
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`9.
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`As I explained in my first declaration, each of the elements of claims
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`1-3 were known in the art, including “a power switch disposed around said unit
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`cell array and comprised of a plurality of third MOS transistors, each of the third
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`MOS transistors having the second threshold voltage.” EX1003, ¶¶32-55, 108-233.
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`I understand that the PO does not dispute that Mutoh021 discloses this limitation,
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`which is the only limitation not explicitly taught by Urano. POR, 18-19. However,
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`PO argues that a POSA would not have combined Urano and Mutoh021. Id., 19. I
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`disagree.
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`10. As I explained in my first declaration, the disclosed elements of Urano
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`and Mutoh021 would have been readily combined according to known
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`methods to yield predictable results—reduced resistance between components—
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`and there would have been a reasonable expectation of success, because such a
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`combination would have been applying a known technique—positioning power
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`cells around the cell array or around and within the cell array—to a known
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`device—a MTCMOS IC—and for a same purpose—operating under a same low
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`U.S. Patent No. 6,239,614
`voltage and suppressing the magnitude of the leakage current during standby.
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`EX1003, ¶128.
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`B. A POSA Would Have Combined Urano and Mutoh021 with a
`Reasonable Expectation of Success
`I disagree with PO and its declarant’s arguments about the supposed
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`11.
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`lack of benefits or predictability of combining Urano and Mutoh021. As I
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`explained in my first declaration, a POSA would have been motivated to combine
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`Urano and Mutoh021 with a reasonable expectation of success. EX1003, ¶¶114-
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`128.
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`12. First, Urano and Mutoh021 are directed to analogous MTCMOS IC
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`devices based on the same MTCMOS configuration and same cell-based gate array
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`architecture. EX1003, ¶¶114-128.
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`13. The IC device of Urano includes an array of “basic cells” to utilize
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`logic functions, where the basic cells include components of an MTCMOS circuit
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`having high-speed and low-voltage output. EX1008, Urano, [0001], [0029].
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`Further, Urano teaches that a plurality of low-threshold MOSFETs can be provided
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`along with high-threshold MOSFETs to form different types of basic cells used in
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`a cell array. EX1008, [0030], [0038]; EX1003, ¶109.
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`14. Figure 25 of Urano below illustrates a cell array with multiple first
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`basic cells (31) having low-threshold MOSFETs (red), multiple second basic cells
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`(39) having high-threshold MOSFETs (blue), and multiple third basic cells (42)
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`U.S. Patent No. 6,239,614
`used as power switch cells with high-threshold MOSFETs (green). EX1008,
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`[0087], [0085]; EX1003, ¶110.
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`EX1008, FIG. 25 (annotated).
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`
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`15. Mutoh021 also discloses a MTCMOS IC device configured in a gate
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`array style. In particular, a gate array-type integrated circuit compatible with
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`CMOS circuits for low-voltage/high-speed operation composed of a transistor with
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`a high threshold voltage and a transistor with a low threshold voltage. EX1013,
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`Mutoh021, ¶[0001]; EX1003, ¶111. Mutoh021 specifically discloses a layout of
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`the MTCMOS circuit in which the high-threshold voltage power switch transistors
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`are located around the gate array. EX1003, ¶112.
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`16. Figure 1 of Mutoh21, below, illustrates a very similar cell array
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`including first basic cells 2A, 2B, 2C (purple) and second basic cells 3A, 3B, 3C,
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`U.S. Patent No. 6,239,614
`3D (green), which correspond to Urano’s power switch cells, located on the left
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`and right ends and within the cell array configured to form power supply control
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`circuits. EX1003, ¶113.
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`EX1013, FIG. 1 (annotated).
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`17. Urano and Mutoh021 have only minor layout differences (e.g., Urano
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`places the power switches on two sides while Mutoh021 places the power switches
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`on all sides). EX1003, ¶¶117-124.
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`18. Further, Urano does not limit the power switches to only be placed on
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`two sides of the array, but discloses that the power switch cells having high
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`threshold voltage MOS transistors can be positioned at the periphery of a cell
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`array. Urano states that “a power supply cell 43 is structured using this third basic
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`U.S. Patent No. 6,239,614
`cell 42,” “[the] first basic cells 31 and [the] second basic cells 39 are laid out on
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`the chip 30, repeated in units of specific numbers of cells, and third basic cells 42
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`are arranged on the periphery thereof.” EX1008, [0087], [0085]; EX1003, ¶116
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`(emphasis added).
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`19. Mutoh021’s MTCMOS layout design is very similar to Urano, and
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`further includes arrangements of the second basic cells, which correspond to
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`Urano’s power switch cells, around or around and within the cell array. Mutoh021
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`specifically states that “a group of logic circuits is formed in the first basic cell,
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`and a power supply control circuit is formed in the second basic cell to control the
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`supply of power to the group of logic circuits,” and “the second basic cell being
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`arranged adjacent to the cell array composed of the first basic cell, at any end
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`vertically or horizontally, at both ends horizontally, at both ends vertically, at all
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`ends vertically and horizontally, or inside the first basic cell.” EX1013, ¶¶15-16;
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`EX1003, ¶118.
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`20. Moreover, Mutoh021 specifically disclosed a benefit associated with
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`its on all sides arrangement. In the “Means for Solving the Problem” Mutoh021
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`states that the “present invention” included the second basic cells 3 (equivalent to
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`the third basic cells 42 of Urano) placed around all sides of the gate array. EX1013,
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`[0015]. Mutoh021 further states that the second basic cells control the supply of
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`power to the logic circuits. EX1013, [0016]. A POSA would have clearly
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`U.S. Patent No. 6,239,614
`understood that providing more sources for power to the logic circuits (sourced
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`from all sides) would supply more power to the logic circuits. As a result,
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`Mutoh021 stated in the “Effects of the Invention” that the “present invention”
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`having a “cell array composed of second basic cells … arranged adjacent to a cell
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`array”—around all sides—realized the benefit of “a MT-CMOS circuit using high
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`threshold voltage transistors and low threshold voltage transistors… on a single
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`LSI chip without reducing the cell utilization rate.” EX1013, [0035]; EX1003,
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`¶¶118-119.
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`21.
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`In my opinion, and as I explained in my first declaration, a POSA
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`would accordingly have recognized that modifying Urano’s arrangement in view
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`of Mutoh021 would have achieved multiple benefits. EX1003, ¶¶125-127. That is,
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`arranging the power switch cells to all four ends in Urano to encircle the cell array
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`as taught by Mutoh021 would realize circuit design efficiencies, such as reducing
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`wiring complexity, reducing resistance between components (i.e., parasitics),
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`decreasing response time of circuit components, and increased layout pattern
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`density to achieve the low voltage, high-speed operation of Urano. EX1003,
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`¶¶125-127.
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`22. For example, consider the case of a cell in the middle of an array, with
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`power supplied from only two sides of the array. Dips in the power supply due to
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`resistance in the supply may eliminate that cell as a candidate in a high-speed
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`U.S. Patent No. 6,239,614
`circuit where response time is critical. By providing additional power from the top
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`and bottom of the array resistance to the cell is reduced and power-supply glitches
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`are also reduced and the cell can be used. Thus the overall used cell density has
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`increased because a cell can be used that otherwise would not. A further
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`complication exists when high-speed circuits (that would be adversely affected by
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`supply glitches) must be placed near the supply on either side of the array,
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`rendering the interior of the array useless for these high-speed circuits. Ultimately,
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`it is desired that all cells in the array perform the same irrespective of their physical
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`location. To accomplish this, all cells should receive equivalent power from the
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`supplies. A POSA would have understood that, in practice, supplying power from
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`all sides and within the array approaches this goal.
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`23. Saigo presents a three-level metal solution to improve performance by
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`reducing power-supply glitches. EX1016, Saigo, Abstract. In Figure 2 of Saigo, the
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`power is supplied vertically which is equivalent, in a MTCMOS environment, to
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`the power switches being supplied on the top and bottom. Id., 579. In Figure 3,
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`Saigo introduces a metal-3 power supplied horizontally. Id. This is equivalent, in a
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`MTCMOS environment, to adding additional power switches which deliver power
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`from the left and right sides. Thus even Saigo teaches the advantage of power
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`being supplied from all sides as understood by a POSA. EX1003, ¶44.
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`U.S. Patent No. 6,239,614
` These benefits of combining Urano and Mutoh021 would have been
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`24.
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`readily understood by a POSA as confirmed by Sato and Baker, which I discussed
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`in my first declaration. EX1003, ¶¶45, 125. For example, Baker, a textbook from
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`1998, explains that a POSA would have considered parasitic effects when
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`determining the layout of a circuit. EX1025, Baker, xx. Sato, from 1984, teaches a
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`gate array having three layers of metal, with the third layer used for power buses
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`and reduced resistance, and power supply terminals located on all four sides of the
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`chip to reduce the voltage drops in power busses. EX1017, Sato, 140-141; Fig. 4.
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`25.
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`I understand that PO argues that because Urano itself does not
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`recognize a problem with its arrangement of power switches and Mutoh021 does
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`not allegedly disclose any advantage to its arrangement, a POSA would not have
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`modified Urano. POR, 21-22. I disagree. Circuit design is an iterative process that
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`often builds on prior circuit designs, leading to improvements and benefits.
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`EX1003, ¶¶125, 169.
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`26.
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`I understand that PO also contends that Mutoh021 does not disclose
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`any advantage associated with its arrangement to encircle the unit cell array. POR,
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`22-23. I disagree. As I explained above and in my first declaration, Mutoh021 does
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`disclose an advantage to this arrangement and a POSA would have readily
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`understood the benefits of this arrangement in the circuit of Urano as described
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`above. See supra Section III.A.
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`U.S. Patent No. 6,239,614
`I understand that PO admits that “according to Mutoh021,
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`27.
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`Mutoh021’s advantages are achieved by arranging power switch cells ‘adjacent to
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`the cell array’,” but argues that “the ‘at all ends vertically and horizontally’
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`arrangement does not confer any advantages over the ‘at both ends vertically’
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`arrangement.” POR, 23. I disagree with PO at least because the power switch cells
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`arranged at all four sides would serve more power to cells located in the middle of
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`horizontal rows (marked in yellow) of the array compared to the “at both ends
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`vertically” arrangements, as shown in the figure below. In my opinion, a POSA
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`would have known that adding the power switch cells at the top row and bottom
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`row would cut the equivalent resistance to the center of the array in half
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`(approximately).
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`EX1013, FIG. 6 (annotated).
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`U.S. Patent No. 6,239,614
`It is notable that PO’s declarant admitted that the ’614 patent does not
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`28.
`
`describe any alleged benefit achieved by this claimed configuration but that
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`somehow a POSA would have readily understood the benefits of this arrangement
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`based on Figure 1 of the ’614 patent alone, reproduced below. EX1047, 58:19-
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`60:10 (“These are benefits that are not specifically articulated within the ’614, but
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`are -- would be understood by a person of ordinary skill.”).
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`29. As shown below, Figure 1 of the ’614 patent and Figure 1 of
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`Mutoh021 disclose the same level of detail.
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`EX1001, FIG. 1 (annotated)
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`U.S. Patent No. 6,239,614
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`EX1013, FIG. 1 (annotated)
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`Compare EX1001, 3:11-18 (“The semiconductor integrated circuit device
`
`(hereinafter called ‘MTCMOS’) 10 comprises unit cells 2 each comprised of
`
`PMOS and NMOS transistors both having a low threshold voltage, unit cells 3
`
`each comprised of PMOS and NMOS transistors both having a high threshold
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`voltage, a unit cell array 1 in which the unit cells 2 and 3 are laid in array form, a
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`power switch 4 placed around the unit cell array 1, and input/output circuits 5
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`disposed therearound.”) to EX1013, ¶0015 (“…the second basic cell being
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`arranged adjacent to the cell array composed of the first basic cell, at any end
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`vertically or horizontally, at both ends horizontally, at both ends vertically, at all
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`ends vertically and horizontally, or inside the first basic cell.”) (emphasis added).
`
`30.
`
`In my opinion, if a POSA would have understood the benefits of the
`
`arrangement of power switches from Figure 1 of the ’614 patent as PO’s declarant
`
`contends, so too would they have readily understood the benefits of this
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`arrangement as taught by Mutoh021. EX1047, 112:11-18 (“…Yes, there are
`
`benefits to placing the power switch around the unit cell array associated with the
`
`pad ring.”). Thus a POSA would have been motivated to modify Urano in view of
`
`Mutoh021.
`
`31.
`
`I understand that PO also criticizes the combination of Urano and
`
`Mutoh021 by pointing to the model in my first declaration demonstrating the
`
`benefits a POSA would have understood by contending that it applies Ohm’s law
`
`incorrectly. POR, 24. I disagree with PO because they either misrepresent my
`
`position or simply do not understand it. I did not argue for exchanging the position
`
`of the switch and metal resistance by putting the switch close to the load as PO
`
`appears to contend. Rather, the model accurately reflects how providing another
`
`switch adjacent to the load would reduce the voltage drop. EX1003, ¶¶121-122.
`
`32.
`
`I understand that PO further argues that modifying Urano would
`
`negatively impact the cell utilization rate and not result in any design efficiencies.
`
`POR, 24. I disagree and note that PO never explains why this would be the case or
`
`why the ’614 patent would not suffer from this alleged problem. POR, 24.
`
`Regardless, PO mistakenly introduces a false concept of redundant cells. A POSA
`
`would have instead understood that the extra supply cells are not redundant
`
`because they reduce the power supply feed resistance and thus provide a benefit.
`
`Cell utilization would also be unchanged by power switches at the periphery. That
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`U.S. Patent No. 6,239,614
`is, as I explained in my first declaration, adding additional power switch cells
`
`would not impact the circuit in a negative manner. EX1003, ¶¶114-128.
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`33.
`
`I understand that PO presents several additional arguments about the
`
`alleged lack of advantages achieved by combining Urano and Mutoh021. POR, 25-
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`30. I disagree because each of PO’s arguments appear to be based on an
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`assumption that Urano is limited to two metal layers. See POR, 26-28 (“Also,
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`parasitics and circuit response time would not change between Urano and a
`
`hypothetical Urano-Mutoh021 combination because, without additional metal
`
`layers, the power delivery mechanism and network would be the same.”); EX2002,
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`¶¶93, 107, 120, 129; EX1047, 76:2-77:7.
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`34.
`
`In my opinion, a POSA would not have understood Urano’s
`
`MTCMOS to be limited to two metal layers. Nor would a POSA have concluded
`
`that the architecture of the ’614 patent is limited to two metal layers as PO’s
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`declarant agreed. EX1047, 45:17-48:10. I thus disagree with PO’s position that
`
`Urano’s embodiments are limited to only two metal layers while the embodiments
`
`of the ’614 patent are not.
`
`35. Urano does not disclose such a design constraint and a POSA would
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`have understood that the use of more than two layers of metal was well-known at
`
`the time. Indeed, multiple references I discussed in my first declaration disclose
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`three or four metal layers as typical in power line design. EX1003, ¶44. For
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`example, Saigo published in 1983 teaches “triple level metallization,” (EX1016,
`
`Abstract), Sato published in 1984 teaches that “three layer aluminum metallization
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`is used for signal and bias routing and for the power buses,” (EX1017, 140), and
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`Ramus published in 1997 states that “typically three to four metal layers are used”
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`in a gate array IC (EX1011, Ramus, 6:15-19).
`
`36.
`
`I understand that PO’s declarant admits that IC design was not limited
`
`to two metal layers at the time, which I agree with. EX2002, ¶78 (asserting only
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`that two metal layers are only “typically” but not always used). I also note that the
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`single exhibit he cited for his conclusion that Urano is limited to two metal layers
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`does not provide support and actually contradicts it. See EX2002, ¶93 (citing
`
`EX2004 at 17); EX2004 at 15 (acknowledging that “If a fabrication technology
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`provides more than two routing layers [more than two metal layers], a number of
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`them can be reserved exclusively for the interconnections between cells. This
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`allows a large amount of or all inter-cell connections to be routed above the cells to
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`form over-the- cell routing. The pure routing area (channels and feedthroughs),
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`which does not contribute to the circuit density, can thus be minimized.”).
`
`37.
`
`It is informative to note that the ’614 patent does not disclose the
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`number of layers of metal used. Nowhere in the ’614 patent does the word, “metal”
`
`even exist. Nor does the ’614 patent teach the invention of achieving power cells
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`around the cell array using only two metals. EX1047, 60:6-10 (“And does the '614
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`U.S. Patent No. 6,239,614
`patent describe any specific technique used to place the power switch cells around
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`the unit cell array? … A. No.”). Even the PO’s declarant could only account for
`
`one metal in the figures of the ’614 patent. EX1047. 46:17-22, 47: 1-11.
`
`38. Also, PO’s declarant admitted that the ’614 patent is not limited to
`
`two metal layers and the use of more than two metal layers was known at the time
`
`as evidenced by his own exhibits, which I agree with. EX1047, 46:9-48:6, 84:9-16.
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`For example, EX2005 cited by PO’s declarant states that “[w]ith the advent of
`
`extra metallization layers, the routing channels can be eliminated, and routing can
`
`be performed on top of the primitive cells ….”. EX2005, Rabaey, 399-400.
`
`39.
`
`I understand that PO’s declarant argued in his deposition that the three
`
`or more metal layers disclosed by EX2005 are used only for sea of gates design,
`
`which he contends are different from gate arrays. EX1047, 54:12-21. I disagree.
`
`For example, Figure 8-20 on page 400 of EX2005 (reproduced below) clearly
`
`shows that one type of known gate-array architecture is referred to as channelless
`
`(or sea of gates).
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`EX2005, FIG. 8-20.
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`
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`40. As another example, “Sea-of-gates architecture” by Manoel E. de
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`
`
`Lima and David J.Kinniment, published on Microelectronics Journal Volume 26,
`
`Issue 5, July 1995, Pages 431-440, states in its Abstract that “This paper deals with
`
`the development of sea-of-gates technology for the design of VLSI circuits. Sea-
`
`of-gates technology, also considered a second generation gate-array system, is
`
`discussed in detail.” EX1050, de Lima, Abstract. Moreover, the Saigo reference
`
`cited in my declaration is a gate array using three levels of metal. EX1003, ¶44. I
`
`thus disagree with PO’s declarant that the use of more than two metal layers is
`
`somehow limited to only a sea of gates design or that sea of gates would not be
`
`considered a type of gate array.
`
`41. Further, Chapter 13 of EX2006, Microchip Fabrication by Van Zant
`
`from the 4th Edition (2000), which I understand PO did not submit, contains an
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`U.S. Patent No. 6,239,614
`entire chapter discussing more than two layers of metallization. See EX2006, xvi
`
`(“Multilevel Metal Schemes”). EX1049, Van Zant, 397:
`
`Increasing chip density has placed more components on the wafer
`surface, which in turn has decreased the area available for surface
`wiring. The answer to this dilemma has been multilevel metallization
`schemes with two to four individual metal layers (Fig. 13.2). By 2012,
`it is expected that chips will carry up to nine wiring levels.
`In my opinion, these references confirm that no POSA would have
`42.
`
`limited the prior art I discussed in my first declaration to two layers of metal.
`
`43.
`
`I understand that PO also contends that the costs for ICs with more
`
`metal layers are greater than designs with few layers, somehow leading a POSA to
`
`conclude that the prior art is limited to two layers of metal. POR, 24. I disagree. A
`
`POSA would have readily understood that there are tradeoffs in circuit design and
`
`an incremental increase in cost can easily be outweighed by performance benefits.
`
`EX1047, 65:5-70:20.
`
`44. PO’s arguments about the supposed lack of advantages achieved by
`
`combining Urano and Mutoh021 thus only apply to a hypothetical design of Urano
`
`with an arbitrary limitation of two metal layers that in my opinion no POSA would
`
`apply.
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`U.S. Patent No. 6,239,614
`45. Lastly, PO appears to contend that a POSA could not have used
`
`known techniques to modify the power switch arrangement of Urano in view of
`
`Mutoh021. POR, 30-35. I disagree.
`
`46.
`
`I first note that the ’614 patent does not disclose any technique used to
`
`arrange the power switches around the unit cell array or challenges encountered
`
`with such an arrangement. EX1047, 60:6-10 (“And does the '614 patent describe
`
`any specific technique used to place the power switch cells around the unit cell
`
`array? … A. No.”).
`
`47.
`
`I also understand that when asked, PO’s declarant stated that the ’614
`
`could have been implemented with two layers of metal. Id., 48:7-10. And the ’614
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`patent claims placing power switches disposed around and within the array without
`
`a hint of how it is achieved with an unknown numbers of layers of metal. Yet,
`
`PO’s declarant admitted that a POSA would have known how to make the
`
`embodiments of the ’614 patent with its very limited disclosure, even if the circuit
`
`was limited to two metal layers. EX1047, 47:15-48:10. Moreover, PO’s declarant
`
`admitted that a POSA would have known how to make the embodiments of
`
`Mutoh021. Id., 100:15-101:9 (“… So a person of ordinary skill would have enough
`
`disclosure here to design a base level gate array according to this embodiment [of
`
`Mutoh021]”), 102:19-22, 103:10-104:8.
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`48. Regardless, in my opinion, a POSA would have understood the
`
`benefits of Mutoh021’s arrangement and the common challenges related to
`
`distribution of power in a circuit and seek to reduce noise and parasitic resistance
`
`to achieve an efficient design. EX1003, ¶¶41-46, 125-128; EX1047, 65:2-70:20. It
`
`is also my opinion that it would have been well within the knowledge of a POSA
`
`to position Urano’s power switch cells to be around the cell array or around and
`
`within the cell array as explicitly taught by Mutoh021 using well-known standard
`
`software, which was not limited to the second phase of circuit design as PO
`
`appears to contend.
`
`49. And even if the combination of Urano and Mutoh021 was limited to
`
`two metal layers, which it is not, a POSA would have known how to distribute
`
`power around and within the array using a two-metal-layer design to get multiple
`
`benefits. For example, a POSA would have readily known how to use two metal
`
`layers to arrange power lines horizontally and vertically, as I show below:
`
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`50. Using a similar arrangement, a POSA would have also known how to
`
`use two metal layers to achieve distributing the power lines around and within the
`
`cell array, as I show below:
`
`
`51. As shown in the figure above, power switches are placed on the left
`
`and right sides of the array to supply the VDDV power line. In addition, power
`
`switches are provided top and bottom to provide additional VDDV power. The
`
`horizontal power lines are Metal 1 and the vertical power lines are Metal 2. In
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`U.S. Patent No. 6,239,614
`order to preserve Metal 2 signal runs in the routing channel, Metal 1 jumpers span
`
`the channel. Metal 2 continues vertically within the cell itself. Also shown in the
`
`figure above is a power switch which is located in the interior of the array,
`
`intersecting a VDD power line and providing VDDV as an output. A POSA would
`
`have known how to modify Urano based on the teachings of Mutoh021 to place the
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`power switch cells on horizontal and vertical sides and interior of the cell array
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`even using the two-metal-layer design using these techniques.
`
`52.
`
`I understand that PO’s declarant further argues that integrating
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`Mutoh021’s teaching into Urano in a double-ended power switch environment and
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`a two-level metallization environment is not within the abilities of a person of
`
`ordinary skill in the art without great effort and experimentation. EX2002, ¶107. I
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`disagree. For example, a very simple addition to the left and right columns where
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`both VDD and VSS (double-ended) switches supply power would resolve this
`
`issue in two levels of metal. But this is not the only solution and with additional
`
`levels of metal, solutions are even simpler. In my opinion, this would have been
`
`well within the ability of a POSA.
`
`53. As I explained in my first declaration, integrated circuit design using
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`standard computer-aided design (CAD) software for semiconductor IC circuit
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`devices was also well-known by 1999, including the “first phase” of arranging unit
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`cells and the power switch cells. This is confirmed by multiple references I c
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