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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ADVANCED MICRO DEVICES, INC.
`Petitioner
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`v.
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`AQUILA INNOVATIONS, INC.
`Patent Owner
`
`
`
`
`Case IPR2019-1525
`Patent 6,239,614 B1
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`
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`DECLARATION OF DOUGLAS R. HOLBERG PH.D.
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`
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`AMD EX1003
`U.S. Patent No. 6,239,614
`
`

`

`IPR2019-1525
`U.S. Patent No. 6,239,614 B1
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`BACKGROUND ........................................................................................ - 1 -
`
`QUALIFICATIONS AND EXPERTISE ................................................... - 6 -
`
`III. LEGAL UNDERSTANDING .................................................................... - 9 -
`
`A. My Understanding of Claim Construction ....................................... - 9 -
`
`B.
`
`A Person Having Ordinary Skill in the Art .................................... - 12 -
`
`C. My Understanding of Obviousness ................................................ - 13 -
`
`IV. The ’614 Patent ......................................................................................... - 15 -
`
`A.
`
`Technical Background .................................................................... - 15 -
`
`i.
`
`Using MTCMOS gate array in a semiconductor
`integrated circuit for low power consumption and
`reduced leakage current was well-known ............................ - 15 -
`
`ii.
`
`IC layout design was well-known ........................................ - 20 -
`
`iii. Using MOSFETs in IC as decoupling capacitors was
`well-known ........................................................................... - 23 -
`
`B.
`
`C.
`
`D.
`
`The Alleged Problem in the Prior Art ............................................ - 27 -
`
`The Alleged Invention of the ’614 Patent ...................................... - 27 -
`
`Summary of the Prosecution History ............................................. - 32 -
`
`V.
`
`Claim Construction ................................................................................... - 33 -
`
`A.
`
`B.
`
`“unit cells” ...................................................................................... - 35 -
`
`“a unit cell array comprised of said first and second unit
`cells laid in array form” .................................................................. - 43 -
`
`C.
`
`“a power switch” ............................................................................ - 46 -
`
`i
`
`

`

`IPR2019-1525
`U.S. Patent No. 6,239,614 B1
`“a power switch disposed around said unit cell array and
`comprised of a plurality of third MOS transistors” ........................ - 50 -
`
`“a plurality of input/output circuits disposed around said unit
`cell array” ....................................................................................... - 54 -
`
`“parts of said power switch are disposed within said unit cell
`array” .............................................................................................. - 57 -
`
`D.
`
`E.
`
`F.
`
`VI. GROUND 1: CLAIMS 1-3 ARE OBVIOUS OVER URANO IN
`VIEW OF Mutoh021 ................................................................................ - 59 -
`
`A. Overview of Urano ......................................................................... - 59 -
`
`B.
`
`Overview of Mutoh021 .................................................................. - 61 -
`
`C. Motivation to Combine Urano and Mutoh021 ............................... - 63 -
`
`D.
`
`Claim 1 is obvious over Urano in view of Mutoh021. ................... - 72 -
`
`i.
`
`ii.
`
` Urano discloses the preamble of claim 1 ............................ - 72 -
`
` Urano discloses the first unit cells limitation of claim
`1 ............................................................................................ - 73 -
`
`iii. Urano discloses the second unit cells limitation of
`claim 1 .................................................................................. - 76 -
`
`iv. Urano discloses the unit cell array limitation of claim
`1 ............................................................................................ - 78 -
`
`v.
`
`vi.
`
`The combination of Urano and Mutoh021 discloses
`the power switch limitation of claim 1 ................................ - 80 -
`
` The combination of Urano and Mutoh021 discloses
`the input/output limitation of claim 1 .................................. - 84 -
`
`E.
`
`F.
`
`Claim 2 is obvious over Urano in view of Mutoh021. ................... - 86 -
`
`Claim 3 is obvious over Urano in view of Mutoh021. ................... - 87 -
`
`ii
`
`

`

`IPR2019-1525
`U.S. Patent No. 6,239,614 B1
`VII. GROUND 2: CLAIMS 1-3 ARE OBVIOUS OVER MUTOH IN
`VIEW OF MUTOH021 ............................................................................ - 89 -
`
`A. Overview of Mutoh ........................................................................ - 89 -
`
`B. Motivation to Combine Mutoh and Mutoh021 .............................. - 91 -
`
`C.
`
`Claim 1 is obvious over Mutoh in view of Mutoh021. .................. - 96 -
`
`i.
`
`Mutoh discloses the preamble of claim 1 ............................ - 96 -
`
`ii. Mutoh discloses the first unit cells limitation of claim
`1 under the Patent Owner’s alternative claim
`construction .......................................................................... - 97 -
`
`iii. Mutoh discloses the second unit cells limitation of
`claim 1 under the Patent Owner’s alternative claim
`construction ........................................................................ - 100 -
`
`iv. Mutoh discloses the unit cell array limitation of claim
`1 under the Patent Owner’s alternative claim
`construction ........................................................................ - 101 -
`
`v.
`
`vi.
`
`The combination of Mutoh and Mutoh021 discloses
`the power switch limitation of claim 1 under the
`Patent Owner’s alternative claim construction .................. - 103 -
`
`The combination of Mutoh and Mutoh021 discloses
`the input/output limitation of claim 1 under the Patent
`Owner’s alternative claim construction ............................. - 105 -
`
`A.
`
`B.
`
`Claim 2 is obvious over Mutoh in view of Mutoh021. ................ - 108 -
`
`Claim 3 is obvious over Mutoh in view of Mutoh021 under
`the Patent Owner’s alternative claim construction ...................... - 109 -
`
`VIII. GROUND 3: CLAIMS 4-5 ARE OBVIOUS OVER DOUSEKI IN
`VIEW OF RAMUS................................................................................. - 110 -
`
`A. Overview of Douseki.................................................................... - 110 -
`
`iii
`
`

`

`IPR2019-1525
`U.S. Patent No. 6,239,614 B1
`Overview of Ramus ...................................................................... - 112 -
`
`B.
`
`C. Motivation to Combine Douseki and Ramus ............................... - 113 -
`
`D.
`
`Claim 4 is obvious over Douseki in view of Ramus. ................... - 116 -
`
`i.
`
`ii.
`
`Douseki discloses the preamble of claim 4 ........................ - 116 -
`
` Douseki discloses the power supply lines limitation
`of claim 4 ........................................................................... - 116 -
`
`iii. Douseki discloses the virtual power supply lines
`limitation of claim 4 ........................................................... - 118 -
`
`iv.
`
`v.
`
` Douseki discloses the latch circuit limitation of claim
`4 .......................................................................................... - 119 -
`
` Douseki discloses the logic circuit limitation of claim
`4 .......................................................................................... - 120 -
`
`vi.
`
` Douseki discloses the capacitor limitations of claim 4 ..... - 123 -
`
`vii. The combination of Douseki and Ramus discloses the
`wherein limitation of claim 4 ............................................. - 124 -
`
`A.
`
`Claim 5 is obvious over Douseki in view of Ramus. ................... - 127 -
`
`IX. CONCLUSION ....................................................................................... - 131 -
`
`iv
`
`

`

`I, Douglas R. Holberg, declare as follows:
`
`I.
`
`BACKGROUND
`
`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`
`1.
`
`I have been retained by Sterne, Kessler, Goldstein, & Fox, P.L.L.C.,
`
`(“SKGF”) which represents Advanced Micro Devices, Inc. (“AMD”; “Petitioner”)
`
`in connection with the above-captioned inter partes review of U.S. Patent No.
`
`6,239,614 to Morikawa, titled Semiconductor Integrated Circuit Device, EX1001,
`
`“’614 patent.” I understand that the ’614 patent is currently assigned to Aquila
`
`Innovations, Inc. (“Aquila”).
`
`2.
`
`I have reviewed and am familiar with the ’614 patent, which issued to
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`Oki Electric Industry Co. Ltd. on May 29, 2001. I understand that the ’614 patent
`
`includes seven claims, and that claims 1 and 4 are the independent claims. I also
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`understand that the Petition for inter partes review that accompanies this
`
`Declaration seeks to cancel claims 1-5 (“challenged claims”) of the ’614 patent.
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`Thus, my analysis and opinions will focus on claims 1-5 of the ’614 patent. In this
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`Declaration, I will cite to the specification of the ’614 patent using the following
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`format: EX1001, 1:1-10. This example citation points to the ’614 patent
`
`specification at column 1, lines 1-10.
`
`I have reviewed and am familiar with the following documents:
`
`3.
`
`
`
`- 1 -
`
`

`

`Exhibit
`
`1001
`
`1002
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
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`1014
`
`1015
`
`1016
`
`1017
`
`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`DESCRIPTION
`
`U.S. Patent No. 6,239,614 to Morikawa (“’614 patent”)
`
`Prosecution History of U.S. Patent No. 6,239,614 (“’614
`Prosecution History”)
`
`Dr. Holberg’s Curriculum Vitae
`
`Mutoh et al., “1-V Power Supply High-Speed Digital Circuit
`Technology with Multithreshold-Voltage CMOS,” IEEE Journal
`of Solid-State Circuits, Vol. 30, No. 8, 847-854 (1995) (“Mutoh”)
`
`U.S. Patent No. 6,653,693 to Makino (“Makino”)
`
`Japanese Patent Publication No. H10-125878 to Masami Urano
`(“Urano”)
`
`English translation of Urano
`
`Translation Certificate of Urano
`
`U.S. Patent No. 5,486,774 to Douseki et al. (“Douseki”)
`
`U.S. Patent No. 5,631,492 to Ramus et al. (“Ramus”)
`
`Japanese Patent Publication No. H08-18021 to Shin’ichiro Mutoh
`et al. (“Mutoh021”)
`
`English translation of Mutoh021
`
`Translation Certificate of Mutoh021
`
`Declaration of Dr. Holberg in Support of District Court Case No.
`1:18-cv-00554-LY (“Holberg Dec. 2”)
`
`Saigo et al., “A 20 K-Gate CMOS Gate Array,” IEEE Journal of
`Solid State Circuits, Vol. SC-18, No. 5, 578-584 (1983)
`
`Sato et al., “A Subnanosecond 2000 Gate Array with ECL 10OK
`Compatibility,” Vol. ED-31, No. 2, 139-143 (1984)
`
`- 2 -
`
`

`

`Exhibit
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`DESCRIPTION
`
`Massetti et al., “A CMOS-Based Mixed Analog-Logic Standard
`Cell Product Family,” IEEE 1988 Custom Integrated Circuits
`Conference, 24.1.1 (1988)
`
`Horowitz et al., “Chapter 2: Transitors,” The Art of Electronics,
`2d Edition, Cambridge University Press (1989)
`
`U.S. Patent No. 4,001,869 to Brown (“Brown”)
`
`U.S. Patent No. 4,499,387 to Konishi (“Konishi”)
`
`U.S. Patent No. 5,544,102 to Tobita et al. (“Tobita”)
`
`U.S. Patent No. 6,285,052 to Draper (“Draper”)
`
`U.S. Patent No. 6,292,015 to Ooishi et al. (“Ooishi”)
`
`Baker et al., “CMOS Circuit Design, Layout, and Simulation”
`Institute of Electrical and Electronics Engineers, Inc. (1998)
`
`Sato et al., “A Subnanosecond 2000 Gate Array with ECL 100K
`Compatibility,” IEEE Journal of Solid-State Circuits, Vol. SC-19,
`No. 1, 5-9 (1984)
`
`Smith et al., “A CMOS-Based Analog Standard Cell Product
`Family,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 2,
`370-379 (1989)
`
`U.S. Patent No. 6,340,825 to Shibata (“Shibata”)
`
`Scheduling Order, Aquila Innovations, Inc. v. Advanced Micro
`Devices, Inc., Case No. 1:18-cv-00554-LY (W.D. Tex.), issued
`January 18, 2019
`
`Order Granting Unopposed Motion to Extend Claim Construction
`Deadlines, Aquila Innovations, Inc. v. Advanced Micro Devices,
`Inc., Case No. 1:18-cv-00554-LY (W.D. Tex.), issued May 14,
`2019
`
`- 3 -
`
`

`

`Exhibit
`
`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`DESCRIPTION
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`1036
`
`1037
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`1044
`
`1045
`
`1046
`
`Webster’s Third New International Dictionary (2002)
`
`U.S. Patent No. 4,937,649 to Shiba et al. (“Shiba”)
`
`U.S. Patent No. 6,459,331 to Takeuchi et al. (“Takeuchi”)
`
`Weste, Neil H. E. et al., Principles of CMOS VLSI Design (2d ed.
`1993) (“Weste”)
`
`Laplante, P.A., Comprehensive Dictionary of Electrical
`Engineering (CRC Press 1999) (“Laplante”)
`
`Graf, R.F., Modern Dictionary of Electronics (7th ed. 1999)
`(“Graf”)
`
`Merriam-Webster’s Collegiate Dictionary (10th ed. 2001)
`
`Cabe, Adam and Shamik Das, “Performance Simulation and
`Analysis of a CMOS/Nano Hybrid Nanoprocessor System,”
`Nanotechnology, Vol. 20, No. 16, 22 (Apr. 2009) (“Cabe and
`Das”)
`
`U.S. Patent No. 5,781,062 to Mashiko et al. (“Mashiko”)
`
`U.S. Patent No. 5,933,384 to Terada et al. (“Terada”)
`
`U.S. Patent No. 6,034,563 to Mashiko (“Mashiko1996”)
`
`U.S. Patent No. 6,046,627 to Itoh et al. (“Itoh”)
`
`U.S. Patent No. 6,111,427 to Fujii et al. (“Fujii”)
`
`U.S. Patent No. 6,119,250 to Nishimura et al. (“Nishimura”)
`
`U.S. Patent No. 6,140,836 to Fujii et al. (“Fujii1998”)
`
`U.S. Patent No. 6,211,725 to Kang (“Kang”)
`
`- 4 -
`
`

`

`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`The ’614 patent is generally directed to “a semiconductor integrated
`
`4.
`
`circuit device including MOS transistors, which is capable of operating at a low
`
`power supply voltage when taken active and reducing power consumption resultant
`
`from a leakage current during standby.” EX1001, 1:7-12. The ’614 patent also
`
`relates to implementation of a “layout of a semiconductor integrated circuit device
`
`by a gate array system, thereby shortening a manufacturing period thereof as
`
`compared with the conventional standard cell system.” Id., 2:3-7. I am familiar
`
`with the technology described in the ’614 patent both as of its earliest possible
`
`priority date (January 14, 1999) and its actual filing date (April 1, 1999).
`
`5.
`
`I have been asked to consider how a person of ordinary skill in the art
`
`(“POSA”) would have understood the claims subject to inter partes review in light
`
`of the disclosure of the ’614 patent. I have also been asked to consider how a
`
`POSA would have understood the applied Urano, Mutoh, Mutoh021, Douseki, and
`
`Ramus prior art. Further, I have been asked to consider and provide my technical
`
`review, analysis, insights, and opinions regarding whether a POSA would have
`
`understood: the disclosure of Urano in combination with Mutoh021 to render
`
`claims 1-3 obvious; the disclosure of Mutoh in combination with Mutoh021 to
`
`render claims 1-3 obvious; and the disclosure of Douseki in combination with
`
`Ramus to render claims 4-5 obvious.
`
`- 5 -
`
`

`

`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`I am being compensated at my standard hourly rate of $400 dollars
`
`6.
`
`per hour. My compensation is not dependent on the outcome of this inter partes
`
`review and in no way affects the substance of my statements in this declaration.
`
`II. QUALIFICATIONS AND EXPERTISE
`
`7.
`
`In formulating my opinions, I have relied upon my knowledge,
`
`training, and experience in the relevant art. My qualifications are stated more fully
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`in my curriculum vitae, which has been provided as Exhibit 1004. Here, I provide a
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`brief summary of my qualifications.
`
`8.
`
`My education includes a B.S. in Electrical Engineering from Texas
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`A&M University in 1977, followed by a M.S. in Electrical Engineering from the
`
`University of Texas in 1989. I earned a Ph.D. in Electrical Engineering from the
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`University of Texas in 1992.
`
`9.
`
`My qualifications are stated more fully in my curriculum vitae. See
`
`EX1004. As reflected in my curriculum vitae (and as explained in more detail
`
`below), I have experience with the technology described in the ’614 Patent,
`
`including resistors, capacitors, inductors, transistors, transformers, oscillators,
`
`operational amplifiers, comparators, CMOS integrated-circuit technology,
`
`analog/digital mixed-signal circuits, floor-planning and layout of CMOS integrated
`
`circuits, standard cells, custom cells, gate arrays, I/O cells, embedded flash, and
`
`- 6 -
`
`

`

`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`tools used to design, construct, and verify integrated circuits (CAD tools). The
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`following paragraphs provide a brief summary of my qualifications.
`
`10.
`
`I have over 40 years of experience in the electronics field. During
`
`that time, I have worked for several different electronics companies including:
`
`Mostek, Texas Micro Engineering (acquired by Crystal Semiconductor), Crystal
`
`Semiconductor, Cirrus Logic, Cygnal Integrated Products, and Silicon
`
`Laboratories. I joined Silicon Laboratories when they acquired Cygnal, which I co-
`
`founded in 1999. I am a named inventor on 39 U.S. granted patents. I have held a
`
`variety of engineering positions throughout my career, from circuit designer,
`
`design manager, Director of Engineering, Chief Technical Officer, V.P. of
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`Engineering, and V.P. of Technology. In addition to my engineering experience, I
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`also have served as an adjunct faculty member at the University of Texas, where I
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`taught CMOS analog and mixed-signal design for six years, and I have taught a
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`number of short courses in Germany and Ireland.
`
`11.
`
`I earned the BSEE degree from Texas A&M University, the MSE
`
`and Ph.D. degrees from The University of Texas at Austin. A complete listing of
`
`my qualifications including a list of my patents is found in Exhibit 1004.
`
`12. Upon graduation from Texas A&M, I went to work for Mostek
`
`Corporation designing integrated circuits for telecommunications applications. I
`
`designed an integrated DTMF tone generator which was my first patented
`
`- 7 -
`
`

`

`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`invention. I also designed telephone ringer circuits and two-to-four-wire converters
`
`for central-office applications. After leaving Mostek, I joined a startup company,
`
`Texas Micro Engineering, as employee #2, where I designed, among other things,
`
`a dual-channel (atrium-ventricle) pacemaker sense amplifier/filter using discrete-
`
`time switched capacitor technology, co-designed a gate-array that was used to
`
`implement an insulin-pump controller, and a metronome. While enrolled in the
`
`Masters/Ph.D. program at The University of Texas at Austin, I worked on the
`
`application of bipolar technology to DRAM sense-amplifier architectures and
`
`circuit-simulation algorithms. I also designed and laid out the mask set (The
`
`Holberg Mask Set) used by the fabrication class/lab for many years. Upon
`
`graduating with a Ph.D., I went to work for Crystal Semiconductor/Cirrus Logic
`
`where I designed high frequency synthesizers for hard-disk read-channel
`
`applications. I managed a group designing CCD interface circuits for digital
`
`camera applications as well as television encoder chips and CMOS imagers. Upon
`
`leaving Cirrus, I started a company developing mixed-signal microcontrollers. I
`
`was a founder/CTO/VP Engineering, as well as an individual contributor. While at
`
`Cygnal, I designed A/D converters, ∆Vbe temperature sensors, I/O cells/pads (both
`
`design and layout) as well as many additional miscellaneous circuits. My company
`
`was purchased by Silicon Labs where I remained employed as a manager of the
`
`microcontroller group, followed by the position, VP of Technology.
`
`- 8 -
`
`

`

`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`In 2008, I began a consulting career in the area of patents and
`
`13.
`
`intellectual property. I have supported my clients in patent prosecution, licensing,
`
`and litigation in a variety of technologies, including analog/digital mixed signal
`
`circuits, RF circuits, oscillators, PLLs, A/D, D/A converters, switch-mode power
`
`supplies, motor drivers, and a variety of inventions from the circuit-level to system
`
`level. Based on my experience, both professional and educational, I believe I am
`
`more than qualified to give the opinions expressed herein.
`
`14.
`
`I am the co-author of the book “CMOS Analog Circuit Design”
`
`which was published in first edition in 1987. It is now in third edition and
`
`published in English and Chinese—a text widely used throughout the world.
`
`III. LEGAL UNDERSTANDING
`
`15.
`
`I am not an attorney and will not offer opinions on the law. I have
`
`been informed by counsel for AMD, however, of several principles that I have
`
`used in arriving at my stated conclusions in this report.
`
`A. My Understanding of Claim Construction
`
`16.
`
`I have been advised and understand that “claim construction” is the
`
`process of determining a patent claim’s meaning. I also understand that, during an
`
`inter partes review, a claim construction analysis begins with the plain meaning of
`
`the claim term, which is the ordinary and customary meaning given to the term by
`
`- 9 -
`
`

`

`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`those of ordinary skill in the art at the time of the invention. I also understand that
`
`this standard is sometimes referred to as the Phillips standard.
`
`17.
`
`I have been informed and understand that there is a presumption that
`
`claim terms carry their accustomed meaning among persons of ordinary skill in the
`
`art. I have also been informed that the ordinary and customary meaning of a claim
`
`term may be determined by reviewing a variety of sources, including the claims
`
`themselves, the specification (or “written description”) of a patent, its prosecution
`
`history, and dictionaries and treatises.
`
`18.
`
`I have been informed and understand that the language of a patent
`
`claim must be interpreted in light of the patent’s claims, specification, and
`
`prosecution history, as well as other evidence extrinsic to the patent. More
`
`specifically, I understand that claim terms should be given their plain and ordinary
`
`meaning as understood by a person of ordinary skill in the art as of the effective
`
`filing date of the patent application (i.e., the day the application that led to the
`
`patent was filed), unless the claims, specification, or prosecution history indicate
`
`that a special meaning was intended.
`
`19. More specifically, I understand that, for claim construction, one must
`
`focus on the claim terms in the context of the claim as a whole, interpreting the
`
`claim language as it ordinarily would be understood by a person skilled in the art at
`
`the time of the invention. I understand that the context of the surrounding words of
`
`- 10 -
`
`

`

`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`the claim also must be considered in determining the ordinary and customary
`
`meaning of those terms.
`
`20. After the claim language, I understand that the most important
`
`sources to consider are the patent specification, including any publications
`
`incorporated by reference in the specification, and the prosecution history. I
`
`understand that, collectively, these sources (the claim language, specification, and
`
`prosecution history) are called “intrinsic evidence.”
`
`21. With respect to technical references and other information (called
`
`“extrinsic evidence”) that would have been available at the time when the patent’s
`
`application was filed, I understand that the law considers extrinsic evidence to be
`
`less reliable than intrinsic evidence, and that extrinsic evidence should not be used
`
`to change the ordinary meaning of the claim language.
`
`22.
`
`It is my understanding that a patentee may also act as his own
`
`lexicographer and provide definitions in the specification or prosecution history.
`
`For example, an inventor may clearly set forth a definition of the claim term in
`
`either the specification or prosecution history that is different from the term’s
`
`ordinary meaning. I understand that actions taken by the patent owner can affect
`
`the constructions of the claim terms. For instance, there may also be a clear
`
`disavowal of claim coverage in the specification or prosecution history.
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`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`I understand that, if a patentee makes a clear and unambiguous
`
`23.
`
`disavowal of claim scope during prosecution, such a disclaimer informs the claim
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`construction analysis by narrowing the ordinary and customary meaning of the
`
`claim consistent with the scope of the surrender. I further understand that such a
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`disavowal of claim scope must be clear and unambiguous.
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`24. Unless otherwise noted, I have applied the plain meaning of the claim
`
`language for each of the claims discussed.
`
`25. My opinions on validity are based on the information available to me
`
`as of the date of this expert report. In addition, however, I respectfully reserve the
`
`right to supplement this expert report as may be necessary or appropriate based on
`
`the discovery of additional information relevant to the opinions set forth herein,
`
`such as test results produced by Respondents.
`
`B. A Person Having Ordinary Skill in the Art
`
`26.
`
`I have been advised and understand that a POSA is presumed to be
`
`aware of all pertinent art, thinks along conventional wisdom in the art, and is a
`
`person of ordinary creativity, not an automaton. With this understanding, a POSA
`
`at the time of the invention claimed in the ’614 patent, is a person holding a
`
`Bachelor of Science degree in Electrical Engineering or an equivalent field as well
`
`as at least 3-5 years of academic or industry experience in semiconductor
`
`integrated circuit filed, or comparable industry experience.
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`C. My Understanding of Obviousness
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`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`
`27.
`
`I have been advised and understand that a claimed invention is
`
`unpatentable if the differences between the invention and the prior art are such that
`
`the subject matter as a whole would have been obvious at the time the invention
`
`was made to a POSA to which the subject matter pertains. This means that even if
`
`all of the requirements of the claim cannot be found in a single prior art reference
`
`that would anticipate the claim, the claim can still be invalid.
`
`28.
`
`It is my understanding that obviousness is a question of law based on
`
`underlying factual findings: (1) the scope and content of the prior art; (2) the
`
`differences between the claims and the prior art; (3) the level of skill in the art; and
`
`(4) objective considerations of nonobviousness. I understand that for a single
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`reference or a combination of references to render the claimed invention obvious, a
`
`POSA must have been able to arrive at the claims by altering or combining the
`
`applied references.
`
`29.
`
`I also understand that prior art references can be combined under
`
`several different circumstances. For example, it is my understanding that one such
`
`circumstance is when a proposed combination of prior art references results in a
`
`system that represents a predictable variation, which is achieved using prior art
`
`elements according to their established functions.
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`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`I also understand that when considering the obviousness of a patent
`
`30.
`
`claim, one should consider whether a teaching, suggestion, or motivation to
`
`combine the references exists so as to avoid impermissibly applying hindsight
`
`when considering the prior art. I understand this test should not be rigidly applied,
`
`but that the test can be important to avoiding such hindsight.
`
`31.
`
`Further, I understand that certain objective indicia can be important
`
`evidence regarding whether a patent is obvious or nonobvious. Such indicia
`
`include: commercial success of products covered by the patent claims; a long-felt
`
`need for the invention; failed attempts by others to make the invention; copying of
`
`the invention by others in the field; unexpected results achieved by the invention as
`
`compared to the closest prior art; praise of the invention by the infringer or others
`
`in the field; the taking of licenses under the patent by others; expressions of
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`surprise by experts and those skilled in the art at the making of the invention; and
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`the patentee proceeded contrary to the accepted wisdom of the prior art. I am not
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`aware of any objective indicia of nonobvious at this time. But, I reserve the right to
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`review and opine on any evidence of objective indicia of nonobvious that Polaris
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`may present during this proceeding.
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`IV. The ’614 Patent
`
`A. Technical Background
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`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
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`32.
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`The ’614 patent relates to a layout for a semiconductor integrated
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`circuit device including multi-threshold voltage MOS transistors (“MTCMOS”),
`
`which is capable of operating at a lower power supply voltage when active and
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`reduced leakage current during standby. EX1001, Abstract, 1:7-12.
`
`33.
`
`The ’614 patent also relates to the use of MOS decoupling capacitors
`
`to reduce voltage variations and time delays in MTCMOS devices. Id., Abstract,
`
`4:59-6:9. But these techniques, and the benefits thereof, were known well before
`
`the ’614 patent’s earliest possible priority date, which I have been advised is
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`January 14, 1999.
`
`i.
`
`Using MTCMOS gate array in a semiconductor integrated
`circuit for low power consumption and reduced leakage
`current was well-known
`
`34. As an initial matter, using multi-threshold-voltage complementary
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`metal–oxide–semiconductor (MTCMOS) in a semiconductor integrated circuit
`
`operating at a low power supply voltage when active and reduced power
`
`consumption resultant from a leakage current during standby was a well-known
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`concept prior to the ’614 patent. Such fact is admitted in the background section of
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`the ’614 patent:
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`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`As high integration of an LSI or an increase in performance thereof
`progresses, how to reduce the power consumption has recently been
`recognized as an important problem. It can be said that in a CMOS
`type LSI in particular, a reduction in the power supply voltage is a
`method most effective for low power consumption, …the reduction
`in the threshold voltage leads to an increase in leakage current of the
`MOS transistor during standby. An MTCMOS (Multithreshold-
`Voltage CMOS) has been proposed as an LSI for solving such a
`problem. The MTCMOS has been introduced in the paper: 1-V
`Power Supply High-Speed Digital Circuit Technology with
`Multithreshold-Voltage CMOS (IEEE JOURNAL OF SOLID-
`STATE CIRCUIT. VOL. 30. NO. 8, AUGUST 1995) or the like,
`for example.
`EX1001, 1:15-32, emphasis added.
`
`35.
`
`For example, as stated by Mutoh reference, Exhibit 1005, a paper
`
`described above cited by the ’614 patent, a POSA would have understood that the
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`MTCMOS technique “features both low-threshold voltage and high-threshold
`
`voltage MOSFET’s in a single LSI. The low-threshold voltage MOSFET’s
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`enhance speed performance at a low supply voltage of 1 V or less, while the high-
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`threshold voltage MOSFET’s suppress the stand-by leakage current during the
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`sleep period,” EX1005, Abstract, and such MTCMOS can be arranged in “layout
`
`schemes based on a standard cell and chip configurations,” Id., Sec. I, paragraph 4.
`
`Mutoh was published in the IEEE Journal of Solid-State Circuits, Vol. 30 in
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`

`IPR2019-01525
`U.S. Patent No. 6,239,614 B1
`August 1995, more than a year before the priority date of the ’614 patent. IEEE is
`
`a well-known publisher of scientific and technical publications, and a POSA would
`
`have been able to locate Mutoh exercising reasonable diligence.
`
`36.
`
`The ’614 patent also explains the basic components of conventional
`
`prior art MTCMOS devices, including: “at least one logic circuit electrically
`
`connected between a virtual power supply line and a virtual power supply line and
`
`comprised of MOS transistors each having a low threshold voltage and standby
`
`power control MOS transistors each having a high threshold voltage, which are
`
`electrically connected between a power supply line and the virtual power supply
`
`line and between a ground line and a virtual ground line to reduce the leakage
`
`current of each MOS transistor during standby.” EX1001, 1:33-42.
`
`37.
`
`Figure 40 of Urano reproduced below also illustrates an exemplary
`
`prior art MTCMOS gate-array devi