U5005933384A
`
`United States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,933,384
`
`Terada et al.
`[45] Date of Patent: Aug. 3, 1999
`
`
`
`[54] SEMICONDUCTOR INTEGRATED CIRCUIT
`
`[75]
`
`Inventors: Yutaka Terada; T0ru Iwata, both of
`Osaka, Japan
`
`FOREIGN PATENT DOCUMENTS
`
`06029834
`06208790
`
`4/1994
`7/1994
`
`Japan.
`Japan.
`
`[73] Assignee: Matsushita Electric Industrial C0.,
`Ltd., Japan
`
`Primary Examiner—Huan Hoang
`Attorney, Agent, or Firm—McDermott, Will & Emery
`
`[21] Appl. No.: 08/997,558
`
`[22]
`
`Filed:
`
`Dec. 23, 1997
`
`[30]
`
`Foreign Application Priority Data
`
`Dec. 27, 1996
`
`[JP]
`
`Japan .................................... 8—350227
`
`Int. Cl.6 ....................................................... G11C 7/00
`[51]
`[52] US. Cl.
`........................... 365/227; 365/226; 365/229
`[58] Field of Search ..................................... 365/227, 226,
`365/229
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`[57]
`
`ABSTRACT
`
`In serially connected first and third inverters, the high-level-
`side source nodes are connected to a first pseudo-power
`supply line and the low-level-side source nodes are con-
`nected to a third pseudo-power supply line.
`In serially
`connected second and fourth inverters, the high-level-side
`source nodes are connected to a second pseudo-power
`supply line and the low-level-side source nodes are con-
`nected to a fourth pseudo-power supply line. The source
`nodes of transistors which are cut off in the operation mode,
`are disconnected from the power supply when first to fourth
`switch transistors are turned off according to an input signal,
`and these source nodes are short-circuited when either of
`fifth and sixth switch transistors is turned on.
`
`5,410,278
`5,726,946
`
`........................... 365/227 X
`4/1995 Itoh et al.
`3/1998 Yamagata et al.
`...................... 365/226
`
`10 Claims, 9 Drawing Sheets
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`STBI
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`CONTROL
`CIRCUIT
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` V852
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`V881
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`0001
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`AMD EX1040
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`US. Patent No. 6,239,614
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`AMD EX1040
`U.S. Patent No. 6,239,614
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`0001
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`

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`US. Patent
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`Aug.3, 1999
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`Sheet 1 0f9
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`5,933,384
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`Fig.1
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`CONTROL
`CIRCUIT
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`CONTROL
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`CONTROL
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`CIRCUIT
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`US. Patent
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`Aug.3, 1999
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`Sheet 2 0f9
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`5,933,384
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`Fig.3(a)
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`STB2
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`0003
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`0003
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`US. Patent
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`Aug.3, 1999
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`Sheet 3 0f9
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`5,933,384
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`Fig. 4
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`SECOND STATE
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`FIRST STATE
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`SECOND STATE
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`US. Patent
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`5,933,384
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`US. Patent
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`Aug.3, 1999
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`Sheet 5 0f9
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`5,933,384
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`PIigg.(5
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`STBI
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`CONTROL
`CIRCUIT
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`N1
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`P1
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`0006
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`US. Patent
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`Aug.3, 1999
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`Sheet 6 0f9
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`5,933,384
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`Fig. 7
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`SECOND STATE
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`FIRST STATE
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`SECOND STATE
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`A
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`T
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`P1
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`P2
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`US. Patent
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`Aug.3, 1999
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`Sheet 7 0f9
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`5,933,384
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`Fig. 8
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`CONTROL
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`CIRCUIT
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`E2
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`55
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`CIRCUIT HOLDING
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`CONTROL
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`CIRCUIT
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`0008
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`US. Patent
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`Aug.3, 1999
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`Sheet 8 0f9
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`5,933,384
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`Fig. 9
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`VDDlZ
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`VSSll
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`US. Patent
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`Aug.3, 1999
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`Sheet 9 0f9
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`5,933,384
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`Fig.11
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`SECOND STATE
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`FIRST STATE
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`SECOND STATE
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`0010
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`5,933,384
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`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor inte-
`grated circuit having both an operation mode large in power
`consumption and a standby mode small
`in power
`consumption, and more particularly to a semiconductor
`integrated circuit reduced in power consumption when it
`operates at a low voltage.
`With the spread of portable devices and in view of energy
`saving, a reduction in power consumption is recently
`demanded for
`a semiconductor
`integrated circuit
`(hereinafter referred to as LSI). To reduce an LSI in power
`consumption,
`it
`is effective to lower the power supply
`voltage. Further, to assure the reliability of a transistor of
`which miniaturization is progressed, a reduction in power
`supply voltage becomes an essential condition in LSI
`designing. Conventionally, the inside power supply of an
`LSI is mainly set to 3 to 5 V, but an LSI operable at 0.8
`V~1.5 V is now desired for a battery-driven LSI. On the
`other hand, each of the MOS transistors forming an LSI has
`a threshold voltage. When the power supply voltage is
`lowered and approaches the predetermined threshold volt-
`age of each transistor, the drive ability of each transistor is
`lowered to lower the drive current thereof. This lowers the
`
`LSI in performance. In this connection, to provide a prede-
`termined performance even at a low voltage, there are used
`low-threshold transistors higher in drive current. However,
`low-threshold transistors are high in drive current at a low
`voltage and also high in off-leak current in the standby
`mode. This increases the current in the standby mode to
`increase the power consumption, resulting in a failure to
`achieve the original object of a reduction in power con-
`sumption. In this connection,
`there have been proposed
`MTCMOS transistors disclosed by Japanese Patent Laid-
`Open Publication No. 6-29834,
`in which high-threshold
`transistors are disposed between the power supply and a
`circuit formed by low-threshold transistors and in which the
`off-leak current is reduced in the standby mode by turning
`off these high-threshold transistors.
`As another method of reducing the off-leak current, there
`is available a method disclosed by Japanese Patent Laid-
`Open Publication No. 6-208790, with the object of reducing
`the off-leak current in the standby mode.
`However, any of the conventional semiconductor inte-
`grated circuits can reduce only the off-leak current in the
`standby mode and disadvantageously generates a
`feedthrough leak current together with charging and dis-
`charging currents in the operation mode. This is particularly
`remarkable in a circuit in which the operation period of time
`is long or which operates in a region relatively high in
`frequency, because the influence in the operation mode is
`greater.
`
`SUMMARY OF THE INVENTION
`
`The present invention is proposed in view of the forego-
`ing. It is a first object of the present invention to reduce the
`power consumption not only in the standby mode but also in
`the operation mode even though the inside power supply is
`reduced in voltage.
`It is a second object of the present invention to enable a
`high-speed operation to be achieved even though the inside
`power supply is reduced in voltage.
`The present invention has been accomplished with atten-
`tion placed on the following. That is, the main reason why
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`a leak current flows in the operation mode is because the
`power supply potential and the grounding potential are
`applied to the cells such as logic elements or the like. Thus,
`to lower the leak current,
`it
`is essential
`to reduce the
`difference between the power supply potential and the
`grounding potential applied to the cells, to such an extent
`which does not interferes with the transmission of each
`output signal.
`To achieve the first object, the present invention provides
`a method of driving a semiconductor integrated circuit
`having a logic circuit comprising a plurality of elements, and
`this method comprises a power supply voltage changing step
`of changing, according to the state of an input signal in the
`operation mode, the power supply voltage of each element
`which is included in the plurality of elements and which is
`substantially brought into a cutoff state, such that the drive
`ability of the above-mentioned element is reduced.
`According to the semiconductor integrated circuit drive
`method of the present invention, the power supply voltage of
`each element which is included in the plurality of elements
`and which is substantially brought into a cutoff state, is
`changed such that the drive ability of the above-mentioned
`element is reduced. This reduces the feedthrough leak cur-
`rent generated in the logic circuit in the operation mode. This
`reduces the leak current not only in the standby mode but
`also in the operation mode. This results in a reduction in
`power consumption in the operation mode.
`According to the semiconductor integrated circuit drive
`method of the present invention, the power supply voltage
`changing step preferably comprises a step of decreasing the
`power supply voltage or a step of increasing the power
`supply voltage. With such an arrangement,
`the voltage
`decreasing step is effective for reduction in leak current
`when each element driven by the higher-side potential is
`brought into a cutoff state, and the voltage increasing step is
`effective for reduction in leak current when each element
`
`driven by the lower-side potential is brought into a cutoff
`state. This securely reduces the leak current in the operation
`mode. Further, in a logic circuit in which the value of either
`higher-side potential or lower-side potential has a logic, the
`potential of each element substantially in the cutoff state, is
`equal to an intermediate potential between the higher-side
`potential and the lower-side potential. This hastens deter-
`mination of a logic when an operation starts, enabling the
`circuit to be operated at higher speed. Thus,
`the second
`object can be achieved.
`According to the semiconductor integrated circuit drive
`method of the present invention, the power supply voltage is
`preferably a first power supply voltage higher than the
`grounding potential or a second power supply voltage lower
`than the grounding potential, and the power supply voltage
`changing step preferably comprises: a step of changing the
`first power supply voltage to a third power supply voltage
`smaller than the first power supply voltage, or a step of
`changing the second power supply voltage to a fourth power
`supply voltage larger than the second power supply voltage.
`With such an arrangement, the step of changing the first
`power supply voltage to the third power supply voltage
`smaller than the first power supply voltage, is effective for
`reduction in leak current when each element which is
`
`included in the plurality of elements of the logic circuit and
`which is driven by the first power supply voltage serving as
`the higher-side potential, is brought into a cutoff state, and
`the step of changing the second power supply voltage to the
`fourth power supply voltage larger than the second power
`supply voltage,
`is effective for reduction in leak current
`when each element which is included in the plurality of
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`0011
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`0011
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`

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`5,933,384
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`3
`elements of the logic circuit and which is driven by the
`second power supply voltage serving as the lower-side
`potential, is brought into a cutoff state. This securely reduces
`the leak current in the operation mode. Further, in a logic
`circuit in which the value of either higher-side potential or
`lower-side potential has a logic, the potential of each ele-
`ment substantially in the cutoff state is equal to an interme-
`diate potential between the higher-side potential and the
`lower-side potential. This hastens determination of a logic
`when an operation starts, enabling the circuit operation to be
`executed at higher speed.
`Preferably,
`the semiconductor integrated circuit drive
`method of the present invention further comprises a step of
`making the value of the third power supply voltage equal to
`the value of the fourth power supply voltage. With such an
`arrangement, there can simultaneously be set the third power
`supply voltage obtained by decreasing the first power supply
`voltage serving as the higher-side potential and the fourth
`power supply voltage obtained by increasing the second
`power supply voltage serving as the lower-side potential.
`This not only securely generates an intermediate potential
`between the higher-side potential and the lower-side
`potential, but also eliminates the generation of two different
`intermediate potentials. This results in simplification of the
`circuit.
`
`In the semiconductor integrated circuit drive method of
`the present invention, the logic circuit is preferably con-
`nected to a first power supply line to which the first power
`supply voltage is applied, and to a second power supply line
`to which the second power supply voltage is applied, and the
`power supply voltage changing step preferably comprises a
`step of stopping the application of the first power supply
`voltage to the first power supply line, stopping the applica-
`tion of the second power supply voltage to the second power
`supply line, and then connecting the first and second power
`supply lines to each other. With such an arrangement, the
`higher-side potential is decreased and the lower-side poten-
`tial is increased, and each of the decreased and increased
`potentials becomes the same potential having an intermedi-
`ate value between the first power supply voltage and the
`second power supply voltage. This not only securely gen-
`erates a potential having an intermediate value between the
`higher-side potential and the lower-side potential, but also
`eliminates the generation of two different
`intermediate
`potentials. This results in simplification of the circuit.
`To achieve the first object, the present invention provides
`a first semiconductor integrated circuit having a logic circuit
`comprising a plurality of elements, and this semiconductor
`integrated circuit comprises power supply voltage changing
`means for changing, according to the state of an input signal
`in the operation mode, the power supply voltage of each
`element which is included in the plurality of elements and
`which is substantially brought into a cutoff state, such that
`the drive ability of the above-mentioned element is reduced.
`According to the first semiconductor integrated circuit,
`the power supply voltage changing means changes the
`power supply voltage of each element which is included in
`the plurality of elements and which is substantially brought
`into a cutoff state in the operation mode, such that the drive
`ability of the above-mentioned element is reduced. This
`reduces the feedthrough leak current generated in the logic
`circuit in the operation mode. This reduces the leak current
`not only in the standby mode but also in the operation mode.
`This result
`in a reduction in power consumption in the
`operation mode.
`According to the first semiconductor integrated circuit,
`the power supply voltage changing means preferably com-
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`prises: a voltage decreasing unit connected to the logic
`circuit for decreasing, according to the state of an input
`signal in the operation mode, a first power supply voltage of
`each element which is included in the plurality of elements
`and which is substantially brought into a cutoff state, to a
`third power supply voltage such that the drive ability of the
`above-mentioned element is reduced; and a voltage increas-
`ing unit connected to the logic circuit for increasing, accord-
`ing to the state of an input signal in the operation mode, a
`second power supply voltage of each element which is
`included in the plurality of elements and which is substan-
`tially brought into a cutoff state, to a fourth power supply
`voltage such that the drive ability of the above-mentioned
`element is reduced. With such an arrangement, when each
`element which is included in the plurality of elements in the
`logic circuit and which is driven by the higher-side potential,
`is substantially brought
`into a cutoff state,
`the voltage
`decreasing unit decreases the power supply voltage of the
`above-mentioned element. Also, when each element which
`is included in the plurality of elements in the logic circuit
`and which is driven by the lower-side potential, is substan-
`tially brought into a cutoff state, the voltage increasing unit
`increases the power supply voltage of the above-mentioned
`element. This securely reduces the leak current
`in the
`operation mode.
`Further, in a logic circuit in which the value of either
`higher-side potential or lower-side potential has a logic, the
`potential of each element substantially in the cutoff state is
`equal to a potential having an intermediate value between
`the higher-side potential and the lower-side potential. This
`hastens determination of a logic when an operation starts,
`enabling the circuit operation to be executed at higher speed.
`Thus, the second object can be achieved.
`According to the first semiconductor integrated circuit,
`the value of the third power supply voltage is preferably
`equal to the value of the fourth power supply voltage.
`According to the first semiconductor integrated circuit,
`the logic circuit is preferably connected to a first power
`supply line to which the first power supply voltage is
`applied, and to a second power supply line to which the
`second power supply voltage is applied, and each of the
`voltage decreasing unit and the voltage increasing unit is
`preferably connected between the first and second power
`supply lines and preferably has a switch for opening and
`closing the electrical connection between the first and sec-
`ond power supply lines. With such an arrangement, there can
`securely be generated a single potential having an interme-
`diate value between the first and second power supply
`voltages.
`Preferably, the first semiconductor integrated circuit of
`the present invention is arranged in the following manner.
`There are further disposed (i) a first power supply line to
`which the first power supply voltage is applied, (ii) a second
`power supply line to which the second power supply voltage
`is applied and (iii) first and second pseudo-power supply
`lines connected to each of the voltage decreasing unit and
`the voltage increasing unit. The logic circuit is connected to
`the first and second pseudo-power supply line. Each of the
`voltage decreasing unit and the voltage increasing unit
`comprises (i) a first switch connected between the first
`power supply line and the first pseudo-power supply line, (ii)
`a second switch connected between the second power supply
`line and the second pseudo-power supply line and (iii) a
`third switch connected between the first and second pseudo-
`power supply lines. With such an arrangement, when the
`first and second switches are turned off and the third switch
`is turned on for each element which is included in the
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`0012
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`5,933,384
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`5
`plurality of elements in the logic circuit and which is
`substantially brought into the cutoff state, there can securely
`be generated a potential having an intermediate value
`between the first and second power supply voltages.
`According to the first semiconductor integrated circuit,
`the first power supply voltage preferably has the power
`supply potential, and the second power supply voltage
`preferably has the grounding potential. With such an
`arrangement, the logic circuit can securely be operated.
`To achieve the first and second objects,
`the present
`invention provides a second semiconductor integrated cir-
`cuit comprising: a plurality of logic circuits each comprising
`a plurality of elements; a first power supply line to which
`applied is a first power supply voltage higher than the
`grounding potential, and a second power supply line to
`which applied is a second power supply voltage lower than
`the grounding potential; voltage decreasing means con-
`nected to each of the logic circuits for decreasing the first
`power supply voltage according to the state of an input
`signal
`in the operation mode; voltage increasing means
`connected to each of the logic circuits for increasing the
`second power supply voltage according to the state of an
`input signal in the operation mode; and first, second, third
`and fourth pseudo-power supply lines connected to each of
`the voltage decreasing means and the voltage increasing
`means. In this second semiconductor integrated circuit, a
`portion of the logic circuits is connected to each of the first
`and third pseudo-power supply lines, and the remaining
`portion of the logic circuits is connected to each of the
`second and fourth pseudo-power supply lines, and each of
`the voltage decreasing means and the voltage increasing
`means has a first switch connected between the first power
`supply line and the first pseudo-power supply line, a second
`switch connected between the first power supply line and the
`second pseudo-power supply line, a third switch connected
`between the second power supply line and the third pseudo-
`power supply line, a fourth switch connected between the
`second power supply line and the fourth pseudo-power
`supply line, a fifth switch connected between the first
`pseudo-power supply line and the fourth pseudo-power
`supply line, and a sixth switch connected between the
`second pseudo-power supply line and the third pseudo-
`power supply line.
`In the second semiconductor integrated circuit, the volt-
`age decreasing means is arranged to decrease the first power
`supply voltage according to the state of an input signal in the
`operation mode, and the voltage increasing means is
`arranged to increase the second power supply voltage
`according to the state of an input signal in the operation
`mode. In the voltage decreasing means and the voltage
`increasing means, the first and fourth pseudo-power supply
`lines are brought into a floating state from the power supply
`voltage, by turning off, for example,
`the first and fourth
`switches, and each of the first and fourth pseudo-power
`supply lines is set to a potential having an intermediate value
`between the first power supply voltage serving as the
`higher-side potential and the second power supply voltage
`serving as the lower-side potential, by turning on the fifth
`switch. Accordingly, when this intermediate potential
`is
`applied to each element which is included in the plurality of
`elements and which is substantially brought into a cutoff
`state, this reduces a feedthrough leak current generated in
`the logic circuits in the operation mode. The potential having
`an intermediate value between the first and second power
`supply voltages is being decreased with respect to the first
`power supply voltage, and increased with respect to the
`second power supply voltage. Thus, based on logics entered
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`into the logic circuits, the logic circuits can be divided into
`one logic circuit group to be driven by the first and third
`pseudo-power supply lines, and the other logic circuit group
`to be driven by the second and fourth pseudo-power supply
`lines. Accordingly, each logic circuit to be cut off in the
`operation mode and each logic circuit to be operated in the
`operation mode, can be included in one logic circuit group
`and the other logic circuit group, respectively. It is therefore
`possible to change the operational voltage of each logic
`circuit to be cut off in the operation mode such that the
`element drive ability is decreased. This results in a reduction
`in leak current in the operation mode.
`Further, in each logic circuit, the value of either higher-
`side potential or lower-side potential has a logic and the
`potential of each element in the cutoff state is set to an
`intermediate potential. This hastens determination of the
`logic when an operation starts, enabling the circuit operation
`to be executed at higher speed.
`In the second semiconductor integrated circuit, the first to
`sixth switches are preferably controlled by an input signal in
`the operation mode. With such an arrangement, the voltage
`decreasing means and the voltage increasing means are
`securely controlled according to the logic value entered in
`the operation mode.
`In the second semiconductor integrated circuit, the first
`power supply voltage preferably has the power supply
`potential, and the second power supply voltage preferably
`has the grounding potential.
`In the second semiconductor integrated circuit, each of the
`logic circuits preferably comprises two field-effect transis-
`tors different in conduction type from each other, and first
`inverters each of which is connected to the first and third
`
`pseudo-power supply lines and second inverters each of
`which is connected to the second and fourth pseudo-power
`supply lines, are preferably alternately connected serially to
`each other. With such an arrangement, in the plurality of
`alternately serially connected inverters, the logic is succes-
`sively inverted in the direction from the input side to the
`output side. Accordingly, when the field-effect transistors of
`one conduction type are under operation,
`the field-effect
`transistors of the other conduction type are substantially cut
`off. Accordingly, when provision is made such that
`the
`potential of the pseudo-power supply line for driving the
`field-effect transistors of the other conduction type is set to
`a potential having an intermediate value between the first
`and second power supply voltages, there can be achieved a
`circuit capable of securely reducing the leak current in the
`operation mode. Therefore, when the semiconductor inte-
`grated circuit of the present invention is used for a high-load
`driver circuit for example, there can securely be achieved
`both a reduction in power consumption in operation mode
`and a high-speed operation.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a circuit diagram of a semiconductor integrated
`circuit according to a first embodiment of the present
`invention;
`FIG. 2 is a circuit diagram of the semiconductor inte-
`grated circuit according to the first embodiment of the
`present invention;
`FIGS. 3(a) and 3(b) are circuit diagrams of a standby
`control circuit unit according to the first embodiment of the
`present invention, in which FIG. 3(a) shows a first standby
`control circuit and FIG. 3(b) shows a second standby control
`circuit;
`FIG. 4 is a timing chart of the semiconductor integrated
`circuit according to the first embodiment of the present
`invention;
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`0013
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`0013
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`5,933,384
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`7
`FIG. 5 is a schematic view of a driver circuit for driving
`memory cells in a semiconductor memory;
`FIG. 6 is a circuit diagram of a semiconductor integrated
`circuit according to a modification of the first embodiment
`of the present invention;
`FIG. 7 is a timing chart of the semiconductor integrated
`circuit according to the modification of the first embodiment
`of the present invention;
`FIG. 8 is a block diagram of a semiconductor integrated
`circuit according to a second embodiment of the present
`invention;
`FIG. 9 is a circuit diagram of a first logic circuit in the
`semiconductor integrated circuit according to the second
`embodiment of the present invention;
`FIG. 10 is a circuit diagram of a second logic circuit in the
`semiconductor integrated circuit according to the second
`embodiment of the present invention; and
`FIG. 11 is a timing chart of the semiconductor integrated
`circuit according to the second embodiment of the present
`invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`First Embodiment
`
`The following description will discuss a first embodiment
`of the present invention with reference to attached drawings.
`FIG. 1 is a circuit diagram of a semiconductor integrated
`circuit according to a first embodiment of the present
`invention.
`In FIG. 1, voltage increasing and decreasing
`means 1 serving as power supply voltage changing means,
`is connected to a power supply line VDD to which applied
`is the power supply potential as a first power supply voltage,
`and to a grounding line VSS to which applied is the
`grounding potential as a second power supply voltage. Also,
`the voltage increasing and decreasing means 1 is connected
`to first to fourth inverters 21 to 24 which serve as logic
`circuits and which are serially connected in four stages.
`The voltage increasing and decreasing means 1 com-
`prises: a first P-FET switch transistor 11 connected between
`the power supply line VDD and a first pseudo-power supply
`line VDD1; a second P-FET switch transistor 12 connected
`between the power supply line VDD and a second pseudo-
`power supply line VDD2; a third N-FET switch transistor 13
`connected between the grounding line VSS and a third
`pseudo-power supply line VSS1; and a fourth N-FET switch
`transistor 14 connected between the grounding line VSS and
`a fourth pseudo-power supply line VSS2. The voltage
`increasing and decreasing means 1 further comprises a fifth
`N-FET switch transistor 15 connected between the first
`
`pseudo-power supply line VDD1 and the fourth pseudo-
`power supply line VSS2 and a sixth P-FET switch transistor
`16 connected between the second pseudo-power supply line
`VDD2 and the third pseudo-power supply line VSS1.
`The first inverter 21 is arranged to receive an input signal
`A entered into its input terminal and comprises: a P-FET
`low-threshold transistor Q1 of which source node is con-
`nected to the first pseudo-power supply line VDD1; and an
`N-FET low-threshold transistor Q2 of which source node is
`connected to the third pseudo-power supply line VSS1. The
`second inverter 22 is arranged to receive an output signal B
`of the first inverter 21 and comprises: a P-FET low-threshold
`transistor Q3 of which source node is connected to the
`second pseudo-power supply line VDD2; and an N-FET
`low-threshold transistor Q4 of which source node is con-
`
`8
`nected to the fourth pseudo-power supply line VSS2. The
`third inverter 23 is arranged to receive an output signal C of
`the second inverter 22 and comprises;
`a P-FET low-
`threshold transistor Q5 of which source node is connected to
`the first pseudo-power supply line VDD1; and an N-FET
`low-threshold transistor Q6 of which source node is con-
`nected to the third pseudo-power supply line VSS1. The
`fourth inverter 24 is arranged to receive an output signal D
`of the third inverter 23 and comprises; a P-FET low-
`threshold transistor Q7 of which source node is connected to
`the second pseudo-power supply line VDD2; and an N-FET
`low-threshold transistor Q8 of which source node is con-
`nected to the fourth pseudo-power supply line VSS2.
`Acontrol circuit 17 is arranged to receive the input signal
`A and a standby signal STB1 and to supply pseudo-power
`supply control signals P1, P2, N1, N2 for controlling the first
`to fourth switch transistors 11 to 14. Provision is made such
`
`that the pseudo-power supply control signal P1 is entered
`into the gate electrode of the first switch transistor 11, that
`the pseudo-power supply control signal P2 is entered into
`the gate electrode of the second switch transistor 12, that the
`pseudo-power supply control signal N1 is entered into the
`gate electrode of the third switch transistor 13, and that the
`pseudo-power supply control signal N2 is entered into the
`gate electrode of the fourth switch transistor 14. Similarly,
`the fifth and sixth switch transistors 15, 16 are also con-
`trolled by the input signal A.
`The FETs forming the first to fourth inverters 21 to 24 are
`low-threshold FETs and can therefore be operated at high
`speed at a low voltage. On the other hand, each of the FETs
`forming the first to fourth switch transistors 11 to 14 has a
`high threshold so as to restrain a leak current.
`FIG. 2 shows a specific example of the control circuit 17.
`As shown in FIG. 2, the control circuit 17 comprises a first
`voltage control inverter 31, a second voltage control inverter
`32, a first standby control circuit 18 and a second standby
`control circuit 19. The first standby control circuit 18 is
`arranged to receive, in parallel, a standby signal STB2, the
`input signal A and an input inversion signal/A obtained by
`inverting the input signal A by the first voltage control
`inverter 31, and to supply the pseudo-power supply control
`signals P1, P2 to the voltage increasing and decreasing
`means 1. The second standby control circuit 19 is arranged
`to receive,
`in parallel, a standby signal STB3,
`the input
`signal A and an input inversion signal/A obtained by invert-
`ing the input signal Aby the second voltage control inverter
`32, and to supply the pseudo-power supply control signals
`N1, N2 to the voltage increasing and decreasing means 1.
`FIGS. 3(a) and 3(b) are circuit diagrams of a standby
`control circuit unit according to the first embodiment, in
`which FIG. 3(a) shows the first standby control circuit 18
`and FIG. 3(b) shows the second standby control circuit 19.
`As shown in FIG. 3 (a), the first standby control circuit 18
`comprises: a first
`inverter 18a arranged to receive the
`standby signal STB2, which is then inverted and supplied
`thereby; first and second PMOS switch transistors 18b, 18c
`which are controlled by an output signal of the first inverter
`18a, of which source electrodes are connected to the power
`supply line VDD and of which drain electrodes are con-
`nected to output terminals; a first CMOS switch 18d which
`is controlled by the standby signal STB2 and which supplies
`the input inversion s