`PRINCIPLES OF
`CMOS VLSI DESIGN
`
`A Systems Perspective
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`SICL'UNI) EDITION
`
`NEIL H. E. \VESTE
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`KAMRAN liISIIRACIIIAN
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`AMD EX1034
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`US. Patent No. 6,239,614
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`0001
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`AMD EX1034
`U.S. Patent No. 6,239,614
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` Sponsoring Editor: Peter S. Gordon
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`Production Supervisor: Peggy McMahon
`Marketing Manager: Bob Donegan
`Manufacturing Supervisor: Fioy Logan
`Cover Designer: Eileen Hoff
`Composition Services: Mike Wile
`Technical Art Supervisor: Joseph K. Vetere
`Technical Art Consultant: Loretta Bailey
`Technical Art Coordinator: Alena B. Konecny
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`Library oi Cong reee Cataloging-In-Publicaflon Data
`Waste. Neil H. E.
`Principles of CMOS VLSI design : a systems perspective! Neil
`Waste. Kamran Eshraghian -- 2nd ed.
`p. cm.
`Includes bibliographical reterences and index.
`ISBN 0~201-53376—6
`
`1 . Intergrated circuits-Very large scale integration-design and
`construction 2. Metal oxide semiconductors. Complementary.
`I. Eshraghian. Kamran.
`. ll. Title.
`TK7874.W46 1992
`6213954620
`
`92-16564
`
`Cover Photo: Dick Morton
`Cover Art: Neil Waste
`Photo Credit: Plates 5. 12. and 13. Meigar Photography, Inc.. Santa Clara. CA
`
`ElIIHIIi
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`Copyright © 1993 by AT&T
`
`Reprinted with CO??ECE'J'":$ '12-
`
`‘99-:
`
`All rights reserved. No part of this publication may be reproduced. stored in a
`retrieval system. or transmitted. in any form or by any means, electronic. mechani-
`cal. photocopying, recording, or otherwise. without the prior written permission of
`the publisher. Printed in the United States of America.
`
`5 6 7 8 9 10-MA-969594
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`0002
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`6.3 CMOS CHIP DESIGN OPTIONS
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`FIGURE 8.23 Concurrent
`Logic array logic CB"
`
`Compared with the Algutrtmix cell it has considerably more functionality within
`a cell. A rest-liable register. XOR. and an AND gate an: included. Thus. for
`instance. a .slnglc-muntcr bit can be implemented in a single cell.
`
`Sea-of-Gate and Gate Array Design
`6.3.5
`Programming interconnect on chips is a method ofreductng the design cm! of
`an integrated circuit. For small-rulumc chips this can have a dimct impact on
`the part price. The mm: popular style in use for the implementation ul' general
`logic functions is the Sca-uf-Galfl ($00: or Cute Al’T‘d)‘ structure. in which
`
`0003
`
`407
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`
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`403
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`CHAPTER 6 CMOS DESIGN METHODS
`
`the cure of the chip cuntaim a eunlinunus array uf n— and p—tnimistnrs. A ven-
`dor stocks what are called master or base wulen that hate been prncefised up
`to the htage of laying duwu mlysilienn ti.e.. the transistor; have been formed).
`Personalization is then achieved hy using denign-spceifie metalization and
`enntaeLs. The cost I: kept down became ut‘ the following factors:
`
`- The water mat is kept low because large numbers of base wafers may
`he used for many different designs.
`
`' Only 2—5 11);:ka need m be generated. thus keeping mask costs 10w.
`
`- Design time is small due tn highly automated mule fur piaeement.
`muting. and testing.
`
`- Packaging east is kept low due tu standard bond-outs and packages.
`
`' Processing time is kept tn :-1 minimum because oniy the top metaiim—
`ttun Step5 need be run.
`
`. Testing cost» are kept low because mmtnun test fixtures are used fur
`multiple designs.
`
`A typical SOG structure is shown in Fig. (1.24. It (“mists of a cuntinnm
`strip (If n- and p-tranxistur diffusionx adjacent tu substrate dil't‘usionfi. P01} —
`
`FIGURE 6.24 Sea-of-gatas
`(BOG) chip tayoiut architec-
`ture
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`t: 6|". La? ntrip
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`s 3 cries crlrb HESIGN OPT—IONS
`
`- The mcrall mu: nt' Ihr: IJUI'L‘ amt)
`
`' Thu Inrtcm slructurc a] 1hr.- alrli‘t's.‘
`—Hu\t than) n rm“ and p raw» Ihcrc are per hnt'tzumul \trrp. and hem
`the} an: mutcd
`
`The IHIL‘I'U urchncclurc:
`
`—Th:: sin: and ratio at the n- and p-ttunsismrs.
`—Tl1t: number. rlircctmn. and la} (-r of mutmg Hacks.
`—The method ut‘ logic-gate lsnlutlnn‘
`— The personal Izutinrt ntcth: 5d.
`
`l suull}. 1hr: L‘lt'IrC-'.I.I'I"J_\ sires \ur} from \rum]! to lurgn: llh: \l!t."\_ When .1
`, --:n q stem i~ being pltuutcd. 1hr: actual density of trunmtors ix mapped It]
`I :qunalcm raw gnu: number .tml 1hcn In an effectin: usable gate 1::ch tlml
`-.".-.'1~ llh.‘ mat Mummy and placement murhuml». For instance. If thr: unl-
`."..'1 prtch u] the arm} IH lily Llllll Ihc r-zm pitch tx‘ Hutu. than an R ”rm-h}-
`
`silicon cruwng Ihc rt and p tltt'l'tmnm t'urmx a continuum hurlzunlul Arm}. n!
`trunsiflnrs. 'l'ht'sr.‘ tn“ ~ an: repeated \crtically. The: cnre 01' an 800 L'l'Hp m
`cunfitruclcd l‘- surmuttdcd h} .111 Mm} of [(0 cells that can ulw he pru-
`grummed h} ntctulizuliun Routing channels are I'urmed h} muting mcr the
`[up 01' unuwd trunmtura ('iulc arms. \thrch predate SOC} xtructurux. unctl
`titted-height muting lruclu. Wiring butttc‘cn acme Iugtc ruux it} an 50“
`chip UCt‘Ul'K m er thc mp nt unusL-Ll trutttsslurq, v. hm- tn :1 (Butt: Arm) ll'EL' mut-
`ing is mnklruincd m .1 r-Iuttttg channel. th. 15.2."! \l’lttW: a cullectinn ut' I'.tlt:\
`ts ircd together Illuxtrattng thc routing mcr the tnp of the transisltit' rnu x. The
`neccssit} lo ptck a number tnr thc Guts: Arm) muting truck (IL-nail} thereby.
`mnstrarning 1hr.- numhcr nf hurtmnlal “Hill." gnu: \\ a} e\ cntually tn the (I'llv
`”humus-arm) $00 approach.
`A number nl' design tlccismm tune to be mad: u hcn dewgnirtg tha: hmc
`arraymThcsc tncludc lhc lullmt mg:
`
`over unused transistors
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`h't“ la “36 ‘mns [520' 5710
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`FIGURE 8.25 506 gatas
`wtred together showtng routes
`
`0005
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