(12) United States Patent
`Takeuchi et al.
`
`111111
`
`1111111111111111111111111111111111111111111111111111111111111
`US006459331Bl
`US 6,459,331 Bl
`Oct. 1, 2002
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) NOISE SUPPRESSION CIRCUIT, ASIC,
`NAVIGATION APPARATUS
`COMMUNICATION CIRCUIT, AND
`COMMUNICATION APPARATUS HAVING
`THE SAME
`
`(75)
`
`Inventors: Hideki Takeuchi, Tokyo (JP); Masami
`Murakata, Tokyo (JP); Masaaki
`Yamada, Tokay (JP); Reiko Nojima,
`Tokyo (JP); Takashi Ishioka, Tokyo
`(JP); Mutsunori Igarashi, Tokyo (JP)
`
`6,191,647 B1 * 2/2001 Tanaka eta!. .............. 327/551
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`
`11/1984
`59-212027
`360217724 A * 10/1985
`
`OTHER PUBLICATIONS
`
`Takashima et al., Noise Suppression Scheme for Giga-Scale
`DRAM with Hundreds of 1/0s, (1996), pp 43-49.
`
`(73) Assignee: Kabushiki Kaisha Toshiba, Kawasaki
`(JP)
`
`* cited by examiner
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/146,035
`
`(22) Filed:
`
`Sep. 2, 1998
`
`(30)
`
`Foreign Application Priority Data
`
`Sep. 2, 1997
`Sep. 11, 1997
`Mar. 26, 1998
`
`(JP) ............................................. 9-237303
`(JP) ............................................. 9-247202
`(JP) ........................................... 10-079156
`
`Int. Cl? .................................................. H03K 5/00
`(51)
`(52) U.S. Cl. ....................... 327/554; 327/311; 327/558;
`327/551
`(58) Field of Search ................................. 327/552, 551,
`327/553, 554, 555, 556, 557, 558, 311;
`333/172, 173; 257/401, 202
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,367,187 A * 11/1994 Yuen .......................... 257/401
`
`Primary Examiner---Dinh T. Le
`(74) Attorney, Agent, or Firm-Foley & Lardner
`
`(57)
`
`ABSTRACT
`
`A noise suppression circuit encompasses an internal circuit,
`a bypass capacitor, first and second transistors. The internal
`circuit has high and low level terminals, and the low level
`terminal is connected to a low level power supply line. The
`internal circuit is supplied with enable and inverted enable
`signals. The first transistor has a first control electrode, and
`one main electrode is connected to the high level terminal.
`The first control electrode is supplied with the inverted
`enable signal. The bypass capacitor is connected between
`the other main electrode of the first transistor and the low
`level power supply line. The second transistor is connected
`between the other main electrode of the first transistor and
`a high level power supply line. The second transistor has a
`second control electrode supplied with the enable signal.
`The second transistor is not conductive when the internal
`circuit is active.
`
`5 Claims, 40 Drawing Sheets
`
`790
`' I
`I
`r-----------------------~---------~
`I
`
`I
`
`VDD 1
`I
`
`I
`
`GND:
`
`(
`21
`
`VDD'
`
`c~
`
`GN
`
`DIN
`
`Q
`
`L---------------------------------~
`
`AMD EX1033
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 1 of 40
`
`US 6,459,331 Bl
`
`FIG.l
`PRIOR ART
`
`VDD
`
`GND
`
`C----
`
`GN
`DIN
`
`VDD'
`
`Q
`
`0002
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 2 of 40
`
`US 6,459,331 Bl
`
`(V)
`3.50
`
`-
`
`FIG.2A
`
`GN
`
`1.40
`
`r--
`
`r--
`
`r - -
`
`0.00
`0.00
`
`20.00
`
`40.00
`
`85.00
`60.00
`TIME (nsec)
`
`(V)
`3.50 ~~--:::::;------;:::::====:::::::;-----;=====~
`
`FIG.2B
`
`DIN
`
`1.40
`
`0.00 ' - - - - ' - - - - - - - - - - ' - - - - - -___ .L . ._ - - - - - - ' - - - - - J
`0.00
`20.00
`40.00
`60.00
`85.00
`TIME (nsec)
`
`(V)
`3.50 ~---:----~======~-----;::::::::.=======1
`
`FIG.2C
`
`Q
`
`1.10
`
`-
`..____ __ __,
`-0.50 ' - - - - - - - - - - - - - - - - - - - - - - '
`0.00
`20.00
`40.00
`60.00
`85.00
`TIME (nsec)
`
`(p A)
`100.00
`FIG.2D
`-100.00
`
`VDD
`
`-300.00
`
`20.00
`
`40.00
`
`85.00
`60.00
`TIME (nsec)
`
`0003
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 3 of 40
`
`US 6,459,331 Bl
`
`FIG.3
`
`-80.0
`
`~ -90.0
`co
`""0
`.._.,
`-l
`UJ
`
`-100.0
`
`> UJ
`
`-l
`UJ
`
`[/) -0 z
`
`-110.0
`
`-120.0
`
`100
`
`200
`
`300
`
`400
`
`FREQUENCY (Hz)
`
`0004
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 4 of 40
`
`US 6,459,331 Bl
`
`FIG.4A
`PRIOR ART
`
`- -----------------
`1
`
`---------------- -,
`
`203
`nMOS
`TRANSISTOR
`COLUMN
`
`204
`pMOS
`TRANSISTOR
`COLUMN
`
`FIG.4B
`PRIOR ART
`
`~---- 201 u
`
`~---- 201 e
`
`I
`
`-,
`
`I
`I
`I
`
`~---- 261
`
`-} 202
`
`----------------- ----------------
`I L/ //1
`/
`/
`/
`
`/ / / .--l
`
`// /
`
`I/ /
`v /
`/
`/
`/
`/I
`II/
`- - - - - - - - - - - - - - - - - - -----------------
`D
`
`/
`
`/
`
`/
`
`/
`
`/
`
`/ /I
`
`D
`
`262
`
`263
`
`0005
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 5 of 40
`
`US 6,459,331 Bl
`
`FIG.5A
`PRIOR ART
`DDDD[]DDDDDDDDDD
`D
`D
`
`D W;7;>
`
`D-
`//
`/
`/
`D DRAM
`D "'MACRO CELL/
`D ~~~~
`
`D a 1-
`
`111
`
`D
`D
`D
`D
`0
`0
`D
`D
`D
`D
`D
`D
`D
`DDDDCJDDDDDDDDDD
`
`r-----GA TE ARRAY
`
`FIG.5B
`PRIOR ART
`
`DDDD[JDDDDDDDDDD
`D
`D
`103
`____.___._.__104
`103
`___,.---.,.__-ll- 1 04
`
`//;
`D DRAM
`D MACRO CELL
`/ ~
`D
`
`1--r----r---.------.--.----1
`
`103
`
`D
`D
`DDDD[JDDDDDDDDDD
`
`112 -
`
`112
`
`104
`
`0006
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 6 of 40
`
`US 6,459,331 Bl
`
`FIG.6
`PRIOR ART
`
`107
`
`.
`
`' \
`
`. ..
`·.·.·_ .. ·_ .
`. . . . .
`. . . . . .
`
`.
`.
`
`I
`
`I 106
`:
`
`p
`
`1
`
`n
`
`.
`"
`.
`.. • • . ·.
`
`- -----
`
`c----~
`:,
`~ /
`, ,
`.... ________ _
`
`t},;;;?,V:,~-105 r
`
`0007
`
`

`

`SENDER
`CHIP
`
`1 DATA "111 ... 11"
`
`"SEGMENT 0"
`
`"SEGMENT 1"
`
`I
`DATA "111 ... ll'':DATA "111 ... 11"
`I
`
`--J 128 BIT BUS
`f'-"111 ... 11"
`
`64 BIT BUS
`'
`[' "000 ... 00"
`
`- - - - - - -1
`
`-
`64 BIT BUS
`I
`' r - - - - - - l II
`NVERSION:
`[' :"000 ... 00":
`:I
`LAG="1"
`I
`I_
`I
`L ______ ....J
`iii ... il I
`
`1 1 "I
`RECEIVER I ~ A '"r A
`llJ rt 1 rt
`• • . 1 1 I
`CHIP
`FIG.7 A PRIOR ART
`
`" 1 1 1
`1 1 1
`
`ILinln i l i . . . i i :v.t\.ir:..
`
`FIG.7B PRIOR ART
`
`"ALL 1" DATA ??3 I
`
`"1" AND "0" DATA ~
`
`_l!_ 9~"1" 9~"1"
`C1 ---r:
`.
`.
`
`C1
`
`_l!_ 9~"1" 9~0"
`It ~~ DoutO ~~I Dout1
`
`FIG.7C
`PRIOR ART
`
`~·
`
`FIG.7D
`PRIOR ART
`
`~
`
`d •
`\Jl
`•
`~
`~ ......
`~ = ......
`
`0
`I")
`!"""
`'"""' ~
`N c c
`
`N
`
`'JJ. =-~
`~ .....
`-..J
`0 ......,
`~ c
`
`e
`
`rJ'l
`0'1
`'l.
`(It
`\0
`~
`~
`1-"
`~
`1-"
`
`0008
`
`

`

`FIG.8
`PRIOR ART
`
`BLOCK 0
`
`BLOCK 1
`
`BLOCK 2
`
`BLOCK 3
`
`FLAG 0 ...... 15
`0 0 ...... 0
`1 0 ...... 0
`
`16... 31
`0 .... 0
`1 . . . . 1
`
`FLAG 32 ... 47
`0 1 ..... 1
`1 1 ..... 1
`
`48 ... 63
`10101010
`01010101
`
`(BEFORE SENDING)
`(AFTER ENCODING)
`
`d •
`\Jl
`•
`~
`~ ......
`~ = ......
`
`0
`I")
`!"""
`'"""' ~
`N c c
`
`N
`
`'JJ. =-~
`~ .....
`00
`0 ......,
`~ c
`
`e
`
`rJ'l
`0'1
`'l.
`(It
`\0
`~
`~
`1--"
`~
`1--"
`
`0009
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 9 of 40
`
`US 6,459,331 Bl
`
`FIG.9A
`PRIOR ART
`
`[ SENDER CHIP
`
`1
`
`1
`
`1
`
`1
`
`(_
`
`[ RECEIVER CHIP
`
`r-- 121
`
`123
`
`r-- 122
`
`FIG.9B
`PRIOR ART
`
`SENDER CHIP
`
`r--
`
`121
`
`1 1
`
`1 1
`
`ENCODER
`
`r--
`
`124
`
`I
`
`1 1
`
`0 0
`
`1
`
`(_
`
`L DECODER
`
`1 1
`
`1 1
`
`1 23
`
`125
`r--
`
`[
`
`RECEIVER CHIP
`
`r------1
`
`22
`
`0010
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 10 of 40
`
`US 6,459,331 Bl
`
`FIG.lO 790
`
`I
`I
`I
`~--------------------~-------l
`GN
`GNI
`I
`I
`_6_
`_6_
`VDD:
`VDD' :
`N
`~ (
`:
`11
`12
`
`I
`I
`I
`1
`GNDI
`I
`I
`
`C----
`
`GN
`
`DIN
`
`Q
`
`T
`
`FIG.ll GN
`
`.. - - - - - l
`
`FIG.12
`
`790
`
`~ N
`
`c~
`
`I
`I
`I
`I
`GNDI
`I
`I
`
`GN
`
`DIN
`
`Q
`
`0011
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 11 of 40
`
`US 6,459,331 Bl
`
`FIG.13A
`
`790
`
`I
`I
`I
`r-----------------------~---------~
`
`I
`I . - - - - - - - - - - - - - -1
`
`VDD
`
`GND
`
`CLK
`__L
`
`(
`11
`
`(
`21
`
`c~
`
`CLKl
`~
`(
`12 GN
`
`VDD'
`
`I
`I
`I
`I
`I
`I
`L _________________________________ ~
`
`DIN
`
`Q
`
`FIG.l3B CLK
`
`31
`
`32
`
`GN
`
`FIG.13C CLK _...
`
`0012
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 12 of 40
`
`US 6,459,331 Bl
`
`Q
`
`FIG.14A
`
`VDD'
`
`VDD'
`
`-----1
`Nlo-4
`
`N2o-1
`-rl
`
`52
`
`FIG.14B
`
`VDD'
`
`VDD'
`56
`~
`
`0013
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 13 of 40
`
`US 6,459,331 Bl
`
`FIG.15A
`
`GN
`
`172
`
`VDD'
`174
`!
`
`DIN
`
`171
`
`CK
`
`JK03
`
`Q
`
`175
`
`176
`
`FIG.15B
`
`VDD'
`
`VDD'
`
`GNu----1----~
`
`DIN u----------4t------t
`
`GND
`
`0014
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 14 of 40
`
`US 6,459,331 Bl
`
`FIG .16A c~~oo - ·
`CLK
`
`1.60
`
`'
`
`0.00
`0.00
`
`20.00
`
`40.00
`
`85.00
`60.00
`TIME (nsec)
`
`FIG.16C
`
`20.00
`
`40.00
`
`85.00
`60.00
`TIME (nsec)
`
`20.00
`
`40.00
`
`85.00
`60.00
`TIME (nSEC)
`
`____,_, __.__ __ J . ._ ! -'---------''___._I __ __L! --'1
`20.00
`40.00
`60.00
`85.00
`TIME (nsec)
`
`FIG. 16D (~)()() D
`DIN ~:: ,____ _
`
`0.00
`
`(V)
`4.00~
`1.00
`.
`
`FIG.16E
`
`Q
`
`FIG.16F
`
`VDD
`-2o.oo''
`
`r l
`r .I
`B
`,
`~· "~ ~ H rl
`,
`r
`
`-1.00
`0.00
`85.00
`20.00
`40.00
`60.00
`TIME (nsec)
`i.boA) - - - - - - - - - - - - ,
`
`I
`
`-60.00 - - - - - - - ' - - - - - ' - - - - - - ' - - - - . . . J . . . __ J
`0.00
`20.00
`40.00
`60.00
`85.00
`TIME (nsec)
`
`I
`
`I
`
`I
`
`0015
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 15 of 40
`
`US 6,459,331 Bl
`
`FIG.17
`
`~
`
`!XI v
`'---'
`......l
`
`u.:l >
`
`u.:l
`......l
`u.:l
`
`r:/l -0 z
`
`-80.0
`
`-90.0
`
`-100.0
`
`-110.0
`
`-120.0
`
`-130.0 ' - - - - - - - - - - - - - - - - - - - - - - '
`50
`100 150 200 250 300 350 400 450
`
`FREQUENCY (Hz)
`
`0016
`
`

`

`U.S. Patent
`US. Patent
`
`Oct. 1, 2002
`Oct. 1, 2002
`
`Sheet 16 of 40
`Sheet 16 0f 40
`
`US 6,459,331 Bl
`US 6,459,331 B1
`
`00
`~
`
`• d
`~
`~
`
`~
`.,........,
`,,--...;-
`
`
`
`
`<
`
`-
`
`-- ----1
`I
`I
`
`0017
`
`

`

`U.S. Patent
`US. Patent
`
`Oct. 1, 2002
`Oct. 1, 2002
`
`Sheet 17 of 40
`Sheet 17 0f 40
`
`US 6,459,331 Bl
`US 6,459,331 B1
`
`00
`-.::1'"
`
`,........,
`-.::1'"
`
`:::3
`,........,
`-.::1'"
`
`r--
`-.::1'"
`
`00
`-.::1'"
`
`~
`0\
`~
`
`• 0
`~
`~
`
` <3.UE
`
`~
`,........,
`
`VJ
`
`VJ >
`
`~
`-.::1'"
`
`,
`
`H,
`
`Ji~§
`
`V
`
`0
`
`'0 >
`
`VJ
`
`VJ >
`
`-.::1'"
`-.::1'"
`
`
`
`0018
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 18 of 40
`
`US 6,459,331 Bl
`
`FIG.19B
`
`VDD
`
`46
`
`Vss
`
`,41
`
`I
`I
`
`I
`- - - - - - - - , I
`I
`I
`I
`I
`
`I
`
`
`
`I L __ :_
`
`I -
`I
`
`~-~--41u
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`I
`
`-------~: j
`
`~-~-- 41 e
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`I
`I
`I
`I
`I
`
`48 ~---"
`44
`
`43
`
`47
`
`FIG.19C
`
`81 48 81
`
`75
`
`n+
`
`Vss
`
`p+
`
`70
`
`71
`
`72
`
`73
`
`0019
`
`

`

`U.S. Patent
`US. Patent
`
`Oct. 1, 2002
`Oct. 1, 2002
`
`Sheet 19 of 40
`Sheet 19 0f 40
`
`US 6,459,331 Bl
`US 6,459,331 B1
`
`446de
`
`~
`0
`01
`• 0
`~
`~
`
`
`
`
`1:--
`'o::::t
`
`~
`
`'o::::t
`
`00
`'o::::t
`
`
`
`rJ)
`rJ)
`
`> ('(")
`
`'o::::t
`
`'o::::t
`'o::::t
`
`Q
`Q
`>
`
`
`
`0020
`
`
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 20 of 40
`
`US 6,459,331 Bl
`
`FIG.20B
`
`VDD
`
`46
`
`Vss
`
`,-41
`
`I
`I
`
`I
`I
`
`~--: __ 41 u
`
`I
`I
`I
`
`I
`I
`I
`
`: :
`
`I
`
`'---v-------'
`44
`
`43
`
`I
`I
`
`~--:-- 41 e
`
`47
`
`FIG.20C
`
`48
`
`75 84 47
`4946
`
`74
`
`70
`
`n-
`
`p+
`
`71
`
`72
`
`73
`
`0021
`
`

`

`U.S. Patent
`US. Patent
`
`Oct. 1, 2002
`Oct. 1, 2002
`
`Sheet 21 of 40
`Sheet 21 0f 40
`
`US 6,459,331 Bl
`US 6,459,331 B1
`
`:::::::1
`,......;
`
`~ -,: __ ~
`
`
` IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
`lllllllllllllllllllllllllllllllllllllllllllllllllllll
`
`EKIPLIE
`.............................................
`lllllllllllllllllllllllllllllllllllllll
`
`khwhmgfitng
`
`-amii§§hzfi§
`
`a
`a
`>
`
`<:::::.,)
`
`,......;
`-.::::1'"
`
`C/)
`
`rJJ >
`
`("r)
`~
`
`mv
`
`mm>
`
`I
`I
`
`I
`I
`
`I
`I
`
`r:-
`~
`
`I
`I
`
`I
`I
`
`I
`
`I
`
`_
`
`.4‘/
`
`a.lua§§mlfiu§
`
`.—_w*
`[an
`
`0022
`
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 22 of 40
`
`US 6,459,331 Bl
`
`CK
`_l_
`D /_/D
`
`321 T
`
`CK
`
`FIG.22A
`
`----~------~--VDD
`
`lVI
`
`IV2
`
`Q
`CK
`_L
`
`~
`322 T
`CK
`
`0023
`
`

`

`FIG.22B
`
`315
`315
`
`d •
`\Jl
`•
`~
`~ ......
`~ = ......
`
`
`
`JHBJBJ'S'fl
`
`0
`I")
`!"""
`'"""' ~
`N c c
`
`z00z‘I'100
`
`N
`
`'JJ. =-~
`~ .....
`N
`~
`0 ......,
`~ c
`
`017J0EZ133118
`
`e
`
`
`
`181188‘6917‘9sn
`
`rJ'l
`0'1
`'l.
`(It
`\0
`~
`~
`1--"
`~
`1--"
`
`CK
`411
`401 358 381 CK
`387 365
`CK
`411
`401 358
`381 fi;
`387
`365
`
`8
`II—IIIIIIIIIIIIAILIIV‘I’
`g 77
`412
`7 \\\\\\\\\\\“\\\\\\\\\\\laam/mwn\\\\\x\\\\\\\\\\\
`331 :ig‘pll—\\\\\\\\\l\\;‘oflk\\\"\:\\\\\v
`
`§V¢|X E
`7'“ '1I1\
`311
`§ 5p >14 -'rl K4'§ m
`§A’VIXPL§III_3““?4‘? ”1"”
`311
`332 3‘5 §r- 4;-dig
`354 :lfi Er)4x\\\\\\\\\\\.';'<n.\\\‘x\\\\\\\\>4-
`342
`
`
`
`
`
`
`
`/
`‘
`'
`
`382/’
`yvf
`i'\'\1 I/J?~f A/J V~llif\7 t::j
`I r" / / /J
`312---f/lXlM I X~ N
`312
`)2?! Ifi .14
`40241.??1
`g n1
`A
`351 a
`p §
`:\\um\\\\\\\Vfis\\\\\\“\\\\\\§_§
`343
`333 fiFm— m? 384 ——46s
`364 316
`335 fih§_ III"- 385”“
`§
`317
`g + \\\\\\\\\\\\‘fi51::3.\—\\\\\\\\\3 fi
`345
`V
`‘i‘ p §l§
`4,5 31'
`x \ m
`313---Y / /VJ1 I Xn, ~ ~ IV/~/~h~ ~x _ _,lr///~
`313
`II
`X133 \
`rig-vsgfislgfi'
`“X
`5{1‘er Ifi“. V476{lung'1'
`Iv \
`’7 I
`\
`314 /:'lpn\rIIIIINK“?(”Viki
`kw VIIIIIIIIIIIIII+
`403’1.77
`XM4 352
`361
`\\\\\\
`""/l
`1 r /// J
`N
`/VH I
`1"i71 1/ /IX~XV /1 11h0
`AII§ W L..'.IIii—J
`3473
`VIII/l
`
`314 -------1 /
`
`/
`
`IIIVIII/[19:0”III/III],VIIIA'IIIIIIIIII
`
`337
`48
`
`384
`VDD
`
`406 405
`
`VSS
`
`A
`N
`
`4; \J
`
`0024
`
`0024
`
`

`

`FIG.23A
`
`~ - !:
`
`/1 - -
`
`-
`
`D I
`
`- - -
`
`----
`
`I-.-;-
`
`- --
`7
`I
`
`PZ1 f I ~ I (v:/d
`rz:11 / j};z 5 I~
`D I
`I 0}42
`w:z z~ z:PZl
`I ~u : Wf 7 6+ 1 fW
`~/r I I I I~~:
`"--~-'--_/ _ ___. I
`n+
`--------------------------------,------"
`', 41 e
`
`-
`
`~~
`
`p+
`
`- -
`
`- -
`
`-
`
`I D
`
`n+
`
`44
`
`43
`
`44
`
`531
`\ 1
`
`'-
`
`43
`
`d •
`\Jl
`•
`~
`~ ......
`~ = ......
`
`0
`I")
`!"""
`'"""' ~
`N c c
`
`N
`
`'JJ. =(cid:173)~
`~ .....
`N
`~
`0 ......,
`~ c
`
`e
`
`\Jl
`0'1
`'l.
`(It
`\0
`~
`~
`1--"
`~
`1--"
`
`0025
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 25 of 40
`
`US 6,459,331 Bl
`
`FIG.23B
`
`47
`
`85
`
`48
`
`81
`
`74
`
`n-
`
`70
`~533
`----532
`
`531
`
`p
`
`531
`
`0026
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 26 of 40
`
`US 6,459,331 Bl
`
`FIG.24A
`
`581
`
`584 583
`
`~------ ---------- ---------------------------------l
`I
`I
`I
`I
`I
`1
`I
`
`c
`54 1 ...---__
`
`L
`
`c
`
`I :---- 41 u
`c
`
`I
`
`I
`
`542
`
`,
`
`l----------------------------------------------------
`
`:---- 41 e
`
`~---~------~~------~------~
`
`541
`
`542
`
`FIG.24B
`
`583
`
`-581
`
`581
`
`87
`
`0027
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 27 of 40
`
`US 6,459,331 Bl
`
`FIG.24C
`
`584 585 583
`
`~------ ---------- ---------------------------------,
`
`I
`I
`
`I :---- 41 u
`~~~~~~~mrr~-c
`
`I
`
`r.-·---542
`
`I II:
`
`c
`54
`
`c
`
`I
`'----------------------------------------------------
`
`:----41 e
`
`p+
`
`~-----~------~~------~----~
`
`541
`
`542
`
`FIG.24D
`(583
`
`585
`
`582
`
`p
`
`87
`
`0028
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 28 of 40
`
`US 6,459,331 Bl
`
`FIG.25A
`
`c
`
`541
`
`542
`
`FIG.25B
`
`c
`
`c
`
`~---~----~~------~----~
`
`541
`
`542
`
`0029
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 29 of 40
`
`US 6,459,331 Bl
`
`FIG.26A
`
`.56 2 .______.____ _
`561~
`
`564/
`Hit ___ _
`
`----551
`____._____._____, 563
`566
`~~ 567 552
`__ tm ~
`
`568
`
`---551
`
`FIG.26B
`
`564
`
`567
`
`~
`
`565
`
`566
`
`n
`p
`
`~569
`
`0030
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 30 of 40
`
`US 6,459,331 Bl
`
`FIG.27
`
`SENDER CHIP
`
`~ 601
`
`1
`
`1
`
`1
`
`1
`
`ENCODER
`
`~ 602
`
`1
`c
`
`1
`
`0
`
`0
`
`0
`
`1
`
`1~603
`
`DECODER
`
`~ 605
`
`1
`
`1
`
`1
`
`1
`
`RECEIVER CHIP
`
`r------604
`
`0031
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 31 of 40
`
`US 6,459,331 Bl
`
`FIG.28A
`
`4 BIT DATA
`
`_.,_ 6 BIT DATA
`
`(X 0 ,X 1 ,X 2 ,X 3)
`
`_.,_ (y 0 ,y 1 ,y 2 ,y 3 ,y 4 ,y 5 )
`
`(0,0,0,0)
`
`_.,_
`
`(0,0,1,1,1,0)
`
`(0,0,0,1)
`(0,0, 1 ,0)
`(0,0, 1 '1)
`(0, 1 ,0,0)
`(0,1,0,1)
`(0,1,1,0)
`(0,1,1,1)
`(1 ,0,0,0)
`(1 ,0,0, 1)
`(1 ,0,1 ,0)
`(1 ,0,1' 1)
`(1 '1 ,0,0)
`(1,1,0,1)
`(1,1,1,0)
`
`_.,_
`_.,_
`_.,_
`_.,_
`_.,_
`_.,_
`_.,_
`_.,_
`_.,_
`_.,_
`_.,_
`_.,_
`
`(0,0,0,1,1,1)
`(0,0,1,0,1,1)
`(0,0,1,1,0,1)
`(0,1,0,0,1,1)
`(0,1,0,1,0,1)
`(0,1,1,0,0,1)
`(0,1,1,1,0,0)
`(1,0,0,0,1,1)
`(1,0,0,1,1,0)
`(1,0,1,0,1,0)
`( 1 ,0,1 '1 ,0,0)
`(1,1,0,0,1,0)
`(1,1,0,1,0,0)
`~ (1,1,1,0,0,0)
`
`_ ..
`
`(1,1,1,1)
`
`~ (1' 1 ,0,0,0, 1)
`
`0032
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 32 of 40
`
`US 6,459,331 Bl
`
`FIG.28B
`
`NAME
`
`MATHEMATICAL
`SYMBOL
`
`CIRCUIT
`SYMBOL
`
`NOT
`
`-(over bar)
`
`OR
`
`AND
`
`EXCLUSIVE-
`OR
`
`+
`
`.
`
`(±)
`
`-t>o-
`=D-
`=er
`=jD-
`
`FIG.28C
`
`EQUATION
`
`Yo=xo
`
`y 3 =X 3 (±) (x O 'X l ·x 2 ·x 3 +X O ·X I ·X 2 ·X 3 )
`
`Y4=x3c±)(xt·x2·x3+xt·x2·x3)
`
`Ys=xo@Cx1·x2·x3+xt ·x2·x3)
`
`0033
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 33 of 40
`
`US 6,459,331 Bl
`
`FIG.28D
`
`X or----------------------------------~
`Xlr-~---------------~--------------~
`x2~~---------------~----------~
`x3~~~--~---------~--------~
`
`FIG.28E
`
`0034
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 34 of 40
`
`US 6,459,331 Bl
`
`FIG.29
`
`SENDER CHIP
`
`1 1
`
`'\..
`. . . "'-· .
`
`1 1
`
`~ 601
`
`ENCODER
`
`~ 606
`
`1 0
`
`\
`. . . 1\" .
`
`(
`
`1 0
`
`1
`
`DECODER
`
`1 1
`
`'\.. I' ..
`
`1 1
`
`RECEIVER CHIP
`
`60 7
`608 ~
`
`~ 604
`
`0035
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 35 of 40
`
`US 6,459,331 Bl
`
`FIG.30A
`
`615 --..__
`
`602,606
`
`AID
`f ( ----- t
`ENCODER
`
`------- 616
`
`D/A
`
`t t ----- t
`DECODER --.___ 605,608
`
`603,607 ~( - - - - )( - - - - ll 603,607
`
`(
`
`RESPONSE VOICE
`MEMORY
`
`~ 614
`
`FIG.30B
`
`615
`
`AID
`
`D!A
`
`616
`
`602,606-
`
`603,607
`
`605,608
`
`602,606
`
`614
`
`RESPONSE VOICE
`MEMORY
`
`0036
`
`

`

`1
`
`___,
`
`\
`
`625
`
`TRANSMITTER
`SIGNAL
`PROCESSOR
`
`TRANSMITTER
`~
`
`~
`
`1-
`
`I
`
`I
`
`630
`)
`
`,..__
`
`REGISTERED
`NUMBER
`~
`MEMORY
`
`-""
`
`""'"
`
`'\1
`~
`
`615
`
`rG-
`ER
`I
`
`619
`ER
`l
`J
`
`RIN
`SPE
`631
`
`SP
`633
`
`r622
`-o-
`616l_<i>_ ~
`"
`1
`AID
`r D/A
`t
`j_
`I RESPONSE
`614------ VOICE
`MEMORY
`t
`RINGING
`.J632---- GENERATOR
`f
`RECEIVED
`618---- VOICE
`MEMORY
`_t
`1
`D/A J
`AID
`.J,
`620
`6
`~""'>..
`v
`\l
`634
`
`626-1 SWITCH I 624
`\
`I
`627 ~- NUMERIC DISPLAY
`KEYPAD
`629
`t
`•
`
`~
`
`CONTROL
`UNIT
`
`AUTOMATIC
`CALL KEYPAD
`
`615
`
`1
`
`t
`RECEIVED
`VOICE
`REGENERATION
`KEYPAD
`
`636
`
`RECEIVED SIGNAL
`PROCESSOR
`\
`
`637
`
`~ RECEIVER
`
`k--
`
`\
`
`d •
`\Jl
`•
`~
`~ ......
`~ = ......
`
`0
`I")
`!"""
`'"""' ~
`N c c
`
`N
`
`'JJ. =(cid:173)~
`~ .....
`~
`0'1
`0 ......,
`~ c
`
`e
`
`rJ'l
`0'1
`'l.
`(It
`\0
`~
`~
`1--"
`~
`1--"
`
`0037
`
`

`

`U.S. Patent
`
`Oct. 1, 2002
`
`Sheet 37 of 40
`
`US 6,459,331 Bl
`
`FIG.32
`
`NO
`
`AUTOMATIC
`CALL MODE?
`
`YES
`
`YES
`
`YES
`
`YES
`
`IS
`CALLING NUMBER
`RESENTED?
`
`S913
`
`NO
`
`S905
`
`RING CALL-ACCEPTED I
`
`TONE
`
`S907
`
`RECORD
`~--C_O_N_V_ER~S_A_T __ IO_N ____ ,S9 lS~~_R_E_C_E_IV_E~D __ V_O_IC_E __ ~
`
`SEND RESPONSE VOICE
`
`--- ~ S908
`FINISHE~
`I S917
`
`DISCONNECTION
`
`S909
`
`DISCONNECTION
`
`S918
`
`0038
`
`

`

`FIG.33A
`
`,---.. DISPLAY
`
`r----798
`
`790--
`
`_ , . . ._ -
`
`,-----------,
`..... "T"T" ....... I
`I ....
`~ ......... _,.. T
`iLAlLtl LlKLUlll
`- -1 HAVING NOISE :
`:FILTER
`1
`L.. __________ _j
`
`I
`I
`I
`
`t - -
`
`'"""~"'
`/Uj
`(
`
`MAIN CONTROL UNIT ~
`
`792
`(
`I DRAM
`
`SRAM
`(
`794
`
`I
`
`I
`
`793
`(
`I MROM I
`
`I CD-ROM I/F I
`7~5
`
`\[7
`
`~
`
`GPS
`RECEIVER
`
`~
`
`CD-
`ROM
`
`~
`
`CD-ROM
`CONTROLLER
`
`..__
`
`791
`
`797
`
`796
`
`d •
`\Jl
`•
`~
`~ ......
`~ = ......
`
`0
`I")
`!"""
`'"""' ~
`N c c
`
`N
`
`'JJ. =(cid:173)~
`~ .....
`~
`00
`0 ......,
`~ c
`
`e
`
`rJ'l
`0'1
`'l.
`(It
`\0
`~
`~
`1--"
`~
`1--"
`
`0039
`
`

`

`FIG.33B
`
`32 BIT RISC MICROPROCESSOR
`
`780---------1
`
`781~.
`
`PROCESSOR
`CORE
`
`I
`
`DEBUGGING
`SUPPORT UNIT
`
`MEMORY
`PROTECTION
`UNIT
`
`~--783
`
`r-784
`
`WRITE
`782---------11 BUFFER BUS
`CONTROLLER
`
`II
`II
`
`II CLOCK
`GENERATOR
`
`1~785
`II
`
`I
`
`I
`
`d •
`\Jl
`•
`~
`~ ......
`~ = ......
`
`0
`I")
`!"""
`!""
`N c c
`
`N
`
`'JJ. =-~
`~ .....
`~
`'0
`0 ......,
`~ c
`
`e
`
`rJ'l
`0'1
`'l.
`(It
`\0
`~
`~
`1--"
`~
`1--"
`
`0040
`
`

`

`FIG.33C
`
`CPU CORE
`"\
`CPU REGISTER ~---781a
`781b
`CPO REGISTER
`)
`ALU
`SHIFTER
`MAC
`
`MMU
`
`~--781c
`781e
`)
`
`DATA
`CACHE
`
`781
`
`PROCESSOR
`CORE
`
`I
`
`r1 I
`
`781d
`)
`
`INSTR.
`CACHE
`
`781f
`
`)
`
`BIU
`
`I
`
`DEBUG I/F
`
`COPROCESSOR I/F
`
`CONTROLLER I(F
`
`BUS I/F
`
`d •
`\Jl
`•
`~
`~ ......
`~ = ......
`
`0
`I")
`!"""
`'"""' ~
`N c c
`
`N
`
`'JJ. =(cid:173)~
`~ .....
`~ c
`0 ......,
`~ c
`
`e
`
`rJ'l
`0'1
`'l.
`(It
`\0
`~
`~
`1--"
`~
`1--"
`
`0041
`
`

`

`US 6,459,331 Bl
`
`1
`NOISE SUPPRESSION CIRCUIT, ASIC,
`NAVIGATION APPARATUS
`COMMUNICATION CIRCUIT, AND
`COMMUNICATION APPARATUS HAVING
`THE SAME
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a technique to suppress an
`electromagnetic radiation noise, and more particularly to a
`switching noise suppression circuit to suppress a switching
`noise of a circuit in which an activation and a inactivation
`are repeated by an enable signal, a built-in noise filter type
`data holding circuit in which this switching noise suppres(cid:173)
`sion circuit is built, a car navigation apparatus which com(cid:173)
`prises this built-in noise filter type data holding circuit, a
`communication circuit for sending and receiving a digital
`signal through data buses and a communication apparatus
`which comprises this circuit. Moreover, the present inven- 20
`tion relates to a technique to suppress an electromagnetic
`radiation noise in an application-specific integrated circuit
`(ASIC).
`2. Description of the Related Art
`Recently, an environment problem of an electromagnetic 25
`radiation has been largely taken up. The generation of an
`EMI (electromagnetic interference) noise may cause another
`electronic apparatus to be erroneously operated, which may
`result in a serious trouble.
`The EMI noise is roughly classified into the three basic 30
`types listed below:
`(1) a conduction noise from a power supply line;
`(2) a leakage noise from a port; and
`(3) a radiation noise from an LSI surface.
`The (1) conduction noise from the power supply line
`depends on a waveform of a power supply current, and is
`conducted/radiated with the power supply line as an
`antenna. In a case of the (2) leakage noise from the port, a
`change of a potential of the power supply is conducted/
`radiated from a pin of an LSI, such as a port and the like,
`with an external wire as an antenna. The (3) radiation noise
`from the LSI surface is mainly radiated from the LSI surface
`to space with a current loop as an antenna.
`Among them, the conduction noise from the power supply
`line has the largest possibility of having a bad influence on
`other electronic apparatuses. Thus, the counter-plan thereof
`is of urgent necessity. As for this conduction noise from the
`power supply line, a change of a signal inputted to a circuit
`causes the power supply current to be changed, which results 50
`in the generation of the noise. This is typically referred to as
`a switching noise. Conventionally, an RC filter is inserted as
`shown in FIG. 1, in order to suppress such a switching noise.
`In FIG. 1, a capacitor C is referred to as "a bypass
`capacitor", and a resistor R is referred to as "a limiter
`resistor". For example, the bypass capacitor Cis made of the
`gate capacitance of transistors constituting an LSI. The
`limiter resistor R is made of a polysilicon-resistor or an
`aluminum resistor which is mounted on the predetermined
`portions of a semiconductor chip constituting the LSI.
`Moreover, in FIG. 1, an enable signal GN is a signal based
`on a clock signal, and an internal circuit 101 is constituted
`by, for example, a latch.
`FIGS. 2A to 2D are views of showing waves at respective
`nodes when the circuit shown in FIG. 1 is simulated by using
`simulation program with integrated circuit emphasis
`(SPICE). Then, FIG. 2A shows a voltage waveform of the
`
`5
`
`2
`enable signal GN, FIG. 2B shows a voltage waveform of an
`input signal DIN, FIG. 2C shows a voltage waveform of an
`output signal Q and FIG. 2D shows a current waveform of
`a high level power supply line VDD.
`When the enable signal GN is triggered to the internal
`circuit 101 connected to the high level power supply line
`VDD, the power supply current flows. If the activation
`current GN is similarly repeated for each constant period as
`shown in FIG. 2A, the power supply current also has a
`10 constant period as can be seen from FIG. 2D. An electro(cid:173)
`magnetic wave radiated by this power supply current can be
`determined by using the Maxwell equations. However, a
`noise analysis is usually performed by performing a Fourier
`analysis on the power supply current and using a spectrum
`15 represented as a transmission amount (dB) to a reference
`value for each frequency.
`FIG. 3 shows the spectrum to the power supply current
`shown in FIG. 2D. A reference value of a noise level shown
`on a vertical axis in FIG. 3 is assumed to be 1 A. Hereafter,
`a reference value is assumed to be 1 A when the spectrum of
`the noise is similarly shown. It is presumed that a smaller
`transmission amount (dB) has a lower noise level. Similarly,
`the power of a radiation can be represented by using the
`spectrum. However, it is omitted.
`In FIG. 1, when the enable signal GN is triggered and the
`internal circuit 101 is operated, a current is supplied from the
`high level power supply line VDD and further a current is
`supplied from charges accumulated in the bypass capacitor
`C. At this time, the current running through the high level
`power supply line VDD is limited by the limiter resistor R.
`Thus, the sudden change of the power supply current
`becomes small. This results in the reduction of the noise
`level as compared with a case having no RC filter.
`In the prior art shown in FIG. 1, the noise filter constituted
`35 by the limiter resistor R and the bypass capacitor C as shown
`in FIG. 1 is used to suppress the switching noise. However,
`especially, since many latches used in an integrated circuit
`are simultaneously operated in synchronization with a clock,
`the power supply current suddenly flows to thereby generate
`40 the switching noise. At this time, if the capacitance of the
`bypass capacitor C is small and a load current is large, the
`switching noise may exceed an allowable value.
`That is, in the conventional configuration in FIG. 1, the
`load current consumed by the internal circuit 101 is directly
`45 supplied from the high level power supply line VDD to
`thereby cause the sudden flow of the power supply current.
`Hence, it is necessary to mount the bypass capacitor C
`having a large capacitance in order to sufficiently suppress
`the switching noise generated at that time.
`However, it is conventionally difficult to insert the bypass
`capacitor having the large capacitance in the view of a
`limitation of a chip area, a cost and the like when the RC
`filter is inserted into the chip of the LSI. After all, the
`consideration of the chip area and the cost leads to the
`55 unavoidable utilization of the bypass capacitor having the
`small capacitance for them. In this case, it is very difficult to
`sufficiently suppress the switching noise generated by the
`sudden change of the power supply current. In the present
`condition, it is also impossible to deal with the generation of
`60 the switching noise which exceeds the allowable value.
`Incidentally, a semicustom design methodology of using
`a gate array and a standard cell has been mainly used as an
`approach of designing the LSI in order to respond to a
`requirement of shortening a turn around time (TAT) of a
`65 product and a system. In the gate array, as shown in FIG. 4A,
`a master chip in which basic cells 201 composed of a
`plurality of transistors are arranged in a form of a grid is
`
`0042
`
`

`

`US 6,459,331 Bl
`
`5
`
`3
`made in advance, and then any metal interconnect is dis(cid:173)
`posed on the master chip in accordance with a request of a
`client. The gate array has a feature of shortening the TAT of
`the chip, since various logic circuits can be formed only by
`changing the metal layer.
`The conventional basic cells 201u and 201! shown in FIG.
`4A have two n channel MOS transistors (hereafter, referred
`to as an nMOS transistor) and two p channel MOS transis(cid:173)
`tors (hereafter, referred to as a pMOS transistor), respec(cid:173)
`tively. A substrate contact region 202 is formed between the
`upper basic cell 201u and lower basic cell 201/. Contact
`holes are formed on this substrate contact region 202 to
`establish the ohmic contact between the metal interconnect
`on an upper level and the well region on a lower level. A
`signal line, a ground line and the power supply line are wired
`with the metal interconnect (conductive layer) on the upper
`level such as an aluminum layer and the like, although they
`are not shown in FIG. 4A.
`On the other hand, in a cell base LSI, standard cells
`having a desired logic function are formed in advance on a
`wafer, and a chip is formed by combining these standard 20
`cells in accordance with a request of a client. FIG. 4B shows
`an example of a layout of a standard cell. The standard cell
`261 is composed an nMOS transistor region 262 having the
`two nMOS transistors and a pMOS transistor region 263
`having the two pMOS transistors. A substrate contact region
`202 is formed between the adjacent standard cells similarly
`to FIG. 4A. In the semicustom design methodology of using
`the gate array and the standard cell as mentioned above, the
`connection between the signal line, the ground line and the
`power supply line can be selectively performed by using a 30
`CAD tool and the like.
`The above mentioned EMI noise is generated even in the
`LSI manufactured by using the semicustom architecture of
`using the gate array, the standard cell and the like.
`Accordingly, other electronic apparatuses may be errone(cid:173)
`ously operated by the EMI noise generated in the semicus(cid:173)
`tom LSI. For this reason, conventionally, the suppression of
`the EMI noise is tried by disposing the RC filter similar to
`that of FIG. 1 within the chip or outside an LSI package.
`In the gate array and the standard cell architectures, the
`bypass capacitor C is formed by using a gate oxide film of
`a transistor, and the limiter resistor R is formed by using a
`doped polysilicon resistor or an aluminum resistor. In the
`semicustom LSI, it is easy to form the bypass capacitor by
`using the gate oxide film of the transistor. However, the
`capacitance of the bypass capacitor per unit area on a device
`formation surface can not be made so large. Moreover, many
`transistors are required in order to form a desired capaci(cid:173)
`tance of the bypass capacitor. For this reason, the capaci(cid:173)
`tance necessary for the noise filter can not be obtained, and 50
`further the switching noise can not be sufficiently sup(cid:173)
`pressed. That is, this implies that it is impossible to attain the
`sufficient effect for the suppression of the EMI noise.
`On the other hand, in a case of designing the LSI chip, a
`synchronization circuit synchronizing with a system dock
`inputted from the exterior is typically designed in order to
`protect against a timing obstacle. For this reason, numerous
`flip-flops and numerous clock buffer cells which are oper(cid:173)
`ated on the basis of the clock are mounted within the LSI
`chip. In these flip-flops and clock buffer cells, a switching is
`brought about within the flip-flop on the basis of the logic of
`the clock. If a large current is dynamically consumed as
`mentioned above, the change of the current is observed as
`the EMI noise at the exterior through the parasitic induc(cid:173)
`tance of the chip.
`In order to suppress the EMI noise, two counter-plans
`listed below are effective:
`
`4
`(a) A first counter-plan is a method of reducing the power
`dissipation to thereby reduce the change of the current
`which causes the generation of the noise; and
`(b) A second counter-plan is a method of mounting
`numerous bypass capacitors on a chip so that the
`change of the power supply voltage becomes small.
`The former will be described later. As for the latter, a
`method in which the bypass capacitor is formed within the
`LSI chip and then the transient change of the electric power
`10 is absorbed by the bypass capacitor is proposed in the
`cell-base LSI. However, basic cells 1 having predetermined
`structures are mounted on a whole surface, in the LSI of the
`master slice type, such as the gate array and the like. These
`basic cells 1 are used to form a logic circuit. Hence, it is
`15 technically difficult to freely form the bypass capacitor cells
`on the chip. Now, there is no method to effectively suppress
`the EMI noise.
`Incidentally, the advancement of the semiconductor pro(cid:173)
`cess technique enables memories, such as DRAM and the
`like, to be mixed and mounted on the gate array and the
`standard cell. For example, FIG. 5Ais a schematic layout of
`showing an example of a chip on which a gate array 111 and
`a DRAM macro cell112 are mixed and mounted. FIG. 5B
`is a schematic layout of showing an example of a chip on
`25 which cell columns 103 of standard cells, metal intercon(cid:173)
`nects 104 and the DRAM cell112 are mixed and mounted.
`In the DRAM macro cell112, a memory cell is composed of
`a transistor and a capacitor. In short, the capacitor is located
`at each memory cell. The miniaturization of the size of the
`memory cell is required in conjunction with the DRAM
`having a larger capacitance. Typically, the capacitor is
`manufactured by a trench process and the like in order to
`make the capacitance larger.
`FIG. 6 is a sectional view of a capacitor C constituting the
`35 memory cell of the DRAM manufactured by th