United States Patent [191
`Shiba et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,937,649
`Jun.26, 1990
`
`[54] SEMICONDUCTOR INTEGRATED CIRCUIT
`HAVING A CAPACITOR FOR STABILIZING
`A VOLTAGE AT A POWER SUPPLYING
`WIRING
`
`[75]
`
`Inventors: Hiroshi Shiba; Hiroaki Mikoshiba,
`both of Tokyo, Japan
`
`[73] Assignee: NEC Corporation, Tokyo, Japan
`
`[21] Appl. No.: 383,292
`
`[22] Filed:
`
`Jul. 17, 1989
`
`Related U.S. Application Data
`[63] Continuation of Ser. No. 96,359, Sep. 11, 1987, aban(cid:173)
`doned.
`
`Int. CI.s ............................................. H01L 27/02
`[51]
`[52] U.S. CI •........................................ 357/51; 357/68;
`357/71; 357/23.6; 357/40; 357/41; 357/55
`[58] Field of Search .................... 357/51, 68, 71, 23.6,
`357/40, 41, 55
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,249,196 2/1981 Durney et al ......................... 357/51
`4,455,568 6/1984 Shiota ................................. 357/23.6
`4,583,111 4/1986 Early ..................................... 357/68
`4,675,717 6/1987 Herrero et al ........................ 357/51
`4,737,830 4/1988 Patel et al ............................. 357/51
`Primary Examiner-William Mintel
`Attorney, Agent, or Firm-Helfgott & Karas
`[57]
`ABSTRACT
`A semiconductor integrated circuit includes a semicon(cid:173)
`ductor substrate, a plurality of logic gates formed in the
`semiconductor substrate, power source wiring and
`ground wiring formed on the semiconductor substrate
`to supply power source voltage to the logic gates and a
`capacitor formed on the semiconductor substrate and
`distributively connected between the power source
`wiring and the ground wirings.
`
`9 Claims, 2 Drawing Sheets
`
`AMD EX1032
`U.S. Patent No. 6,239,614
`
`0001
`
`

`

`U.S. Patent
`
`Jun.26,1990
`
`Sheet 1 of2
`
`4,937,649
`
`4
`
`11/J !2
`FIG. Ia
`
`FIG. I b
`
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`
`z
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`
`0002
`
`

`

`U.S. Patent
`
`Jun. 26, 1990
`
`Sheet 2 of2
`
`4,937,649
`
`· FIG.3a
`
`2.9
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`
`

`

`1
`
`4,937,649
`
`This is a continuation, of application Ser. No.
`096,359, ftled September 11, 1987, now abandoned.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`
`SEMICONDUCfOR INTEGRATED CIRCUIT
`HAVING A CAPACITOR FOR STABILIZING A
`VOLTAGE AT A POWER SUPPLYING WIRING
`
`2
`proved structure for power supply in which constant
`power voltage is kept throughout power wirings and
`maximum power current is decreased.
`According to the present invention, there is provided
`5 a semiconductor integrated circuit comprising a semi(cid:173)
`conductor substrate, a plurality of logic gates formed in
`a semiconductor substrate, at least two power supply
`wirings formed on the semiconductor substrate and
`supply an operating power to the logic gates and a
`10 capacitor distributively connected between the two
`power supply wirings. The capacitor has a plurality of
`This invention relates to a semiconductor integrated
`circuit, and particularly to an improvement ~or stabiliZ. -
`connections to each of the two power supply wirings.
`••
`ing a voltage at a power supply wiring.
`The connections are distributed at a rate of one for each
`2. Description of the Related Art
`Recent semiconductor integrated circuits have a 15 logic gate or for ten to five hundred logic gates. The
`great number of logic gates on a single semiconductor
`capacitor may be formed as a single capacitor having
`chip. Each logic gate is formed of p- and n-channel
`two conductive layers formed on the two power supply
`MOS FET's to save power consumption but consumes
`wirings and having a dielectric layer interposed there-
`the power during a short transition period when its
`between or as an external chip-type capacitor. Altema-
`electrical state changes to other ele?trical state. If a
`· tively, the capacitor may be formed by interposing a
`great number of logic gates change their electrical
`dielectric layer between the two power supply wirings.
`states, a large current flows through a power supply
`In accordance with the present invention, since the
`wiring, causing a change in voltage at the power supply
`capacitor is distributively connected between the
`wiring. Such voltage changes at the power supply wir-
`power supply wirings, voltage swing becomes small at
`ing becomes large in accordance with a recent trend of 25 every portions thoughout the power supply wirings. All
`increasing the number of logic gates on a single semi-
`the logic gates perform a normal operation. Further-
`conductor chip.
`more, since the transitional large currents are supplied
`For example, if respective logic gates have a mean
`to logic gates from their neighboring section of the
`load capacitance CL of 0.2 pF, a switching time tpd of
`capacitor, the total current supplied from power
`0.1 nS a power supply voltage of 5 volts, a current Icc 30 sources decreases. The electromigration of power sup(cid:173)
`flowing through each logic gate can be expressed as
`ply wirings and the occurrence of burning out the
`power supply wirings become negligible so that the
`number of integrated logic gates can be increased.
`
`20
`
`(I)
`
`and is 10 mA. If, among 100,000 logic gates integrated
`on a single semiconductor chip, a hundredth of the 35
`whole logic gates, i.e. 1,000 logic gates, simultaneously
`change their electrical states, and instant peak current of
`10 A flows through a power supply wiring on the semi(cid:173)
`conductor chip. Such large current produces a large
`voltage drop at the power supply wiring. Some of the 40
`logic gates malfunction in response to the large voltage
`drop. In the worst case, the large current generates an
`electromigration on the power supplying wirings or
`bums out the power supply wirings.
`There has been proposed in Japanese Patent Applica- 45
`tion Examined Publication No. 49-393 which corre(cid:173)
`sponds to Great Britain Pat. No. 1287110 to mount a
`concentrated capacitor element on a backsurface of an
`IC chip for suppressing power voltage change. The
`capacitor is effective for power supply wirings near a 50
`circuit point at which the capacitor is connected. The
`power supply wirings electrically far .from the circuit
`point, however, still generate a voltage change. Fur(cid:173)
`thermore, the large current still flows through the
`power supply wiring near the circuit point, because the 55
`concentrated element of capacitor only supplies addi(cid:173)
`tional current and does not have a function to distribu(cid:173)
`tively supply the additional current. The electromigra(cid:173)
`tion and the wiring-bumning-out are not prevented by
`the concentrated capacitor.
`
`60
`
`SUMMARY OF THE INVENTION
`Therefore, a primary object of the present invention
`is to provide a semiconductor integrated circuit having
`an increased number of integrated circuit elements and 65
`having a capacitor connected to power wirings.
`It is another object of the present invention to pro(cid:173)
`vide a semiconductor integrated circuit having an im-
`
`BRIEF DESCRIPTION OF THE ORA WINGS
`The above and further objects, features and advan(cid:173)
`tages of the present invention will become more appar(cid:173)
`ent from the following detailed description taken in
`conjunction with the accompanying drawings, wherein:
`FIG. 1(a) is a partial section view of a first preferred
`embodiment of the present invention, and
`FIG. 1(b) is a partial plan view showing a relationship
`between the power source wiring, the ground wiring
`and upper metal layers of FIG. 1(a), FIG. 1(a) is a view
`taken along X-X' in FIG. 1(b);
`FIG. 2 is an equivalent circuit diagram of the first
`preferred embodiment;
`FIG. 3(a) is a partial sectional view of a second pre(cid:173)
`ferred embodiment of the present, and
`FIG. 3(b) is a partial plan view showing a relationship
`between the power source wiring and the ground wir(cid:173)
`ing of FIG. 3(b), FIG. 3(a) is a view taken along Y-Y'
`in FIG. 3(b);
`FIG. 4 is a partial sectional view of a third preferred
`embodiment of the present invention; and
`FIGS. S(a) and S(b) are respectively a sectional view
`and a bottom plan view of the chip-type capacitor em(cid:173)
`ployed in the third preferred embodiment of the present
`invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`The first preferred embodiment has a single capacitor
`on a semiconductor substrate, as shown in FIGS. 1(a)
`and 1(b). A plurality of MOS FET's are formed on a
`silicon substrate 1. Each MOS FET has a source region
`11, a drain region 12 and a polycrystalline silicon gate
`13 between the source and drain regions 11 and 12 and
`
`0004
`
`

`

`3
`is surrounded by a groove 14 for isolation from neigh(cid:173)
`boring MOS FET's. A plurality of logic gates such as
`inverter gates are formed by, for example, connecting a
`drain region of one MOS FET and a source region of
`another MOS FET with wirings 8. The resulting whole 5
`surface is covered with silicon oxide layer 4. One source
`region in each logic gate is connected to a ground wir(cid:173)
`ing 2. One drain region in each logic gate is connected
`to a power source wiring 3. The ground wiring 2 is
`connected to all inverter gates, but is connected to an 10
`uppermost metal layer 7 through conductive through(cid:173)
`holes 9 at every 100 logic gates. Similarly, the power
`source wiring 3 is connected to another upper metal
`layer 5 through conductive through-holes 10 at every
`100 logic gates. The metal layer 5 is formed in a form of 15
`comb, as shown in FIG. 1(b) to form spaces for the
`conductive through-holes 9. Fingers of the comb run
`perpendicularly to the ground wiring 2 and the power
`source wiring 3. A dielectric layer 6 of Ta20s is inter(cid:173)
`posed between the metal layers 5 a:nd 7 to form a capaci- 20
`tor. Ta20s has a dielectric constant of about 20. When
`the dielectric layer 6 has a thickness of 0.1 ,.,_m, the
`capacitor has a capacitance of about 2,000 pFfmm2.
`The capacitor formed with the metal layers 5 and 7
`25
`and the dielectric layer 6 can be considered as a combi(cid:173)
`nation of a plurality of partial capacitors 15, 15' ....
`Therefore, the integrated circuit shown in FIGS. 1(a)
`and 1(b) can be expressed as an equivalent circuit shown
`in FIG. 2. The partial capacitors 15, 15' ... are added to 30
`every 100 logic gates by the conductive through-holes 9
`and 10.
`Transient large currents flowing through every 100
`logic gates are supplied from neighboring partial capac(cid:173)
`itors 15, 15' . . . . Thus, the transient current becomes 35
`small. Additionally, the supplied transient current flows
`through short lengths of the power supply wirings 2
`and 3. These facts causes a little voltage swing at any
`portion of the power supply wirings 2 and 3, to supply
`a stabilized power voltage to all the logic gates.
`As another advantage, the metal layers 5 and 7 have
`a function of electro-magnetic shield. The logic gates
`covered with the metal layers 5 and 7 are not affected
`by external noise.
`The fact that the transient current is supplied to every 45
`100 logic gates from neighboring partial capacitors 15,
`15' ... causes another advantage. When a large number
`oflogic gates operate simultaneously, a large part of the
`transient large current is supplied from the partial ca(cid:173)
`pacitors 15, 15' . . . . In other words, the current sup- 50
`plied from external power source is smaller than the
`case where no capacitor or a concentrated capacitor is
`added to the power supply wirings 2 and 3. Therefore,
`there are few chances of electromigration in the power
`supply wirings 2 and 3. The chance of burning out the 55
`power supply wirings 2 and 3 is also decreased. Other(cid:173)
`wise, the number of logic gates integrated in a single
`silicon chip can be increased.
`Although the power supply wirings 2 and 3 are con(cid:173)
`nected to the metal layers 5 and 7 at every 100 logic 60
`gates, the number of logic gates may be selected in a
`range from 10 to 500 to obtain similar effects. If the
`power supply wirings 2 and 3 can be connected to the
`metal layers 5 and 7 at every logic gate, the present
`invention is most effective, but the connections at every 65
`logic gate are not necessary to obtain sufficient effect.
`Si3N4 or other dielectric material may be replaced with
`Ta20s of the dielectric material 6.
`
`40
`
`4,937,649
`
`4
`The second preferred embodiment of the present
`invention uses power supply wirings as electrode metals
`of a capacitor, as shown in FIGS. 3(a) and 3(b). A plu(cid:173)
`rality ofMOS FET's are formed in a silicon substrate 21
`with source regions 31, drain regions 32 and polycrys(cid:173)
`talline silicon gate electrodes 33. Some MOS FET's are
`connected by wirings 28 to form logic gates such as
`inverter gates. The resulting whole surface is covered
`with silicon oxide layer 24. A power source wiring 22 is
`formed in a form of comb, as shown in FIG. 3(b), hav(cid:173)
`ing a plurality of fingers which are parallely arranged.
`The power source wiring 22 is connected to one or
`more drain regions of MOS FET in every logic gate
`through conductive through-holes 30. A dielectric
`layer 26 of Ta20s having a thickness of 0.1 ,.,_m covers
`the power source wiring 22 and the exposed surface of
`the silicon oxide layer 24 and is covered with a ground
`wiring 23. The ground wiring 23 covers the whole
`surface of the silicon substrate except regions for wire(cid:173)
`bonding. The ground wiring 23 is also connected to one
`or more source regions ofMOS FET in every logic gate
`through conductive through-holes 29.
`According to the second preferred embodiment, par(cid:173)
`tial capacitors are added to every logic gate. Voltage
`swings at power supply wirings are more effectively
`suppressed, compared to the first preferred embodi(cid:173)
`ment. The decrease of total current flowing through the
`power supply wirings and the shielding effect are also
`obtained, similar to the first preferred embodiment.
`The third preferred embodiment uses a chip-type
`capacitor to be mounted on an integrated circuit device,
`as shown in FIGS. 4, 5(a) and 5(b). The integrated
`circuit device 41 may be any type. One example of the
`device 41 is a gate-array in which a plurality of logic
`gates are formed. Power supply wirings, i.e. a power
`source wiring 42 and a ground wiring 43 are formed on
`uppermost surface. Each power supply and ground
`wirings 42 and 43 has a form of comb. Fingers of the
`combs are alternatively arranged. On each finger a
`plurality of bump electrodes 44 are formed. The bump
`electrodes 44 are to be formed on every portion of the
`power supply and ground wirings 42 and 43 where 10 to
`500 logic gates are connected.
`A chip-type capacitor 80 has electrode layers 81 and
`82 and large dielectric ceramics layer 83 interposed
`between the electrode layers 81 and 82, as shown in
`FIGS. 5(a) and 5(b). The dielectric ceramics may be
`barium titanate. Si3N4 or Ta20s may be used in place of
`the dielectric ceramics. The electrode layers 81 and 82
`have a form of comb on a bottom surface of the chip(cid:173)
`type capacitor 80. The comb's fingers of the electrode
`layers 81 and 82 are alternatively arranged to face the
`comb's finger's of the power supply and ground wirings
`42 and 43 on the integrated circuit device 41.
`The chip-type capacitor 80 is put on the integrated
`circuit device 41 to face the power source wiring 42 to
`the electrode layer 81 and the ground wiring 43 to the
`electrode layer 82. The circles 84 in FIG. 5(b) represent
`portions to be connected with bump electrodes 44 on
`the integrated circuit device 41. Under this condition,
`the assembly is subjected to anneal to connect the bump
`electrodes 44 and the electrode layers 81 and 82.
`According to this third preferred embodiment of the
`present invention, the capacitance of the capacitor
`added between the power supply wirings 42 and 43 can
`be enlarged, irrespective of surface area of the inte(cid:173)
`grated circuit device 41, by increasing number of piled
`dielectric layers 83 together with piled electrode layers
`
`0005
`
`

`

`4,937,649
`
`s
`
`10
`
`·5
`81 and 82. Therefore, the voltage swing on the power
`supply and ground wirings 42 and 43 may be avoided by
`using a chip-type capacitor 80 having a sufficiently
`large capacitance. The transient large current may also
`be sufficiently decreased.
`As above-explained, the present invention improves
`the voltage swing on the power supply wirings' electro(cid:173)
`migration of the power wirings and possibility of burn(cid:173)
`ing out the power wirings by distributively adding ca-
`pacitance to the power wirings.
`What is claimed is:
`1. A semiconductor integrated circuit comprising:
`a semiconductor substrate;
`a plurality of logic gates formed on said semiconduc-
`tor substrate;
`a plurality of pairs of power and ground wirings
`formed on said semiconductor substrate, each of
`said pairs being provided for each one of said logic
`gates to supply power thereto;
`an insulator layer formed on said semiconductor sub-
`strate;
`a capacitor overlying said insulator layer and cover(cid:173)
`ing said power and ground wirings through said
`insulator layer, said capacitor being formed of a
`lower conductive layer distributed over substan(cid:173)
`tially a whole surface of said semiconductor sub- 25
`strate, a dielectric fJ.J.m layer covering said lower
`conductive layer and an upper conductive layer
`formed on said dielectric film layer to cover sub(cid:173)
`stantially the whole surface of said semiconductor
`substrate;
`first means for connecting said power wirings to one
`of said lower and upper conductive layers, each of
`said power wirings being connected to a first con(cid:173)
`necting portion of said one of said lower and upper
`conductive layers, which is positioned directly 35
`upon respective power wirings; and
`second means for connecting said ground wirings to
`the other of said lower and upper conductive lay(cid:173)
`ers, each of said ground wirings being connected to
`a second connecting portion of said other of said 40
`lower and upper conductive layers, which is posi(cid:173)
`tioned directly upon respective ground wirings,
`whereby said power and ground wirings are elec(cid:173)
`trically shielded from external noise.
`2. A semiconductor circuit as claimed in claim 1, 45
`wherein said insulator layer is an insulation film formed
`over said power and ground wirings and having holes
`having said frrst and second means.
`3. A semiconductor integrated circuit as claimed in
`claim 1, wherein said lower conductive layer is of a
`comb-like pattern and has a plurality of teeth to allow
`said second means to pass through spaces between said
`teeth.
`4. A semiconductor integrated circuit comprising:
`a semiconductor substrate;
`a plurality of logic gates formed on said semiconduc- ·ss
`tor substrate;
`a plurality of ground wirings formed on said semicon(cid:173)
`ductor substrate via an insulator material to supply
`a ground potential to said logic gates, each of said
`ground wirings being provided for each of said 60
`logic gates;
`a plurality of power source wirings formed on said
`semiconductor substrate via said insulator material
`to supply a power voltage to said logic gates, each
`of said power source wirings being provided for 65
`each of said logic gates;
`an insulating film formed on said ground and power
`source wirings to overlie said wirings, said insulat-
`
`50
`
`15
`
`20
`
`30
`
`6
`ing film having first holes on said ground and
`power source wirings;
`a first metal layer formed on said insulating film to
`cover substantially a whole surface of said semi(cid:173)
`conductor substrate, said first metal layer having a
`comb-like pattern and being connected to said
`power source wiring with a plurality of first con(cid:173)
`necting means through said first holes on said
`power source wirings;
`a dielectric material layer of a dielectric material
`different from that of said insulator material,
`formed on said first metal layer, said dielectric
`material layer having second holes extending from
`said ground wirings, said second holes being
`formed so as to be separate from said first metal
`layer; and
`a second metal layer formed on said dielectric mate(cid:173)
`rial layer to cover substantially a whole surface of
`said semiconductor substrate, said second metal
`layer being connected to said ground wirings with
`a plurality of second connecting means through
`said first holes on said ground wirings and said
`second holes.
`5. A semiconductor integrated circuit as claimed in
`claim 2, wherein said dielectric fJ.J.m layer is made of
`tantalum oxide.
`6. A semiconductor integrated circuit comprising:
`a semiconductor substrate;
`a plurality of logic gates formed on said semiconduc(cid:173)
`tor substrate;
`a plurality of pairs of power and ground wirings
`formed on said semiconductor substrate, each of
`said pairs being provided for each one of said logic
`'
`gates to supply power thereto;
`an insulator layer formed on said semiconductor sub(cid:173)
`strate;
`a capacitor superposed on said insulator layer, said
`power and ground wirings being surrounded by
`said insulator layer, said capacitor covering said
`wirings via said insulator layer and being formed of
`a lower conductive layer distributed over substan(cid:173)
`tially a whole surface of said semiconductor sub(cid:173)
`strate, a dielectric film layer covering said lower
`conductive layer, and an upper conductive layer
`formed on said dielectric film layer to cover sub(cid:173)
`stantially the whole surface of said semiconductor
`substrate;
`first means for connecting said power wirings to one
`of said lower and upper conductive layers, each of
`said power wirings being connected to a first con(cid:173)
`necting portion of said one of said lower and upper
`conductive layers, which is positioned directly
`upon respective wirings; and
`second means for connecting said ground wirings to
`the other of said lower and upper conductive lay(cid:173)
`ers, each of said ground wirings being connected to
`a second connecting portion of said other of said
`lower and upper conductive layers, which is posi(cid:173)
`tioned directly upon respective ground wirings.
`7. A semiconductor circuit as claimed in claim 6,
`wherein said insulator layer is an insulation film formed
`to cover said power and ground wirings and having
`holes carrying said first and second means.
`8. A semiconductor integrated circuit as claimed in
`claim 7, wherein said dielectric film layer is made of
`tantalum oxide.
`9. A semiconductor integrated circuit as claimed in
`claim 6, wherein said lower conductive layer is of a
`comb-like pattern and has a plurality of teeth to allow
`said second means to pass through spaces between said
`teeth.
`• • • • •
`
`0006
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`PATENT NO.
`4,937,649
`June 26, 1990
`DATED
`INVENTOR(S) : HIROSHI SHIBA et al.
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is hereby
`corrected as shown below:
`
`ON TITLE PAGE:
`
`add the following:
`
`[30] Foreign Application Priority Data
`
`Sept. 12, 1986 [ JP]
`
`Japan . . . . . . . . . 216485/1986
`
`Signed and Sealed this
`
`Twenty-eighth Day of April, 1992
`
`Attest:
`
`Attesting Officer
`
`Commissioner of Patents and Trademarks
`
`HARRY E MANBECK. JR.
`
`0007
`
`