(12) United States Patent
`US 6,340,825 B1
`(10) Patent N0.:
`Shibata et al.
`(45) Date of Patent:
`Jan. 22, 2002
`
`USOO6340825B1
`
`(54) METHOD OF DESIGNING
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND SEMICONDUCTOR
`INTEGRATED CIRCUIT DEVICE
`
`(75)
`
`Inventors: Ryuji Shibata, Higashiyamato; Shigeru
`Shimada, Hoya, both of (JP)
`
`(73) Assignee: Hitachi, Ltd., Tokyo (JP)
`
`ot1ce:
`* N'
`
`lSC a1mer, t e term 0 t 15
`u ect to an
`yd'l'
`h
`fh’
`Sbj
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/131,393
`
`(22)
`
`Filed:
`
`Aug. 7, 1998
`
`(30)
`
`Foreign Application Priority Data
`
`JP
`JP
`JP
`JP
`WO
`
`6—120439
`6—334010
`7—235608
`6—017183
`WO97/21247
`
`4/1994
`12/1994
`9/1995
`1/1996
`6/1997
`
`OTHER PUBLICATIONS
`
`Kuroda et al., “A 0.9V 150MHz 10mW 4mm2 2—D Discrete
`Cosine Transform Core Processor with Variable—Threshold-
`
`—Voltage Scheme”, ISSCC96.
`Kuroda et al., “A High—Speed Low—Power 0.3Mm CMOS
`Gate Array with Variable Threshold Voltage (VT) Scheme”,
`IEEE 1996 Custom Integrated Circuits Conference.
`W. Murry, “Chapter 5: CMOS Technology”, Zusetsu Cho
`Eruesuai Kogaku (Illustrated ULSI Engineering in English),
`pp. 167—191 (in Japanese with English translation).
`
`* cited by examiner
`
`Primary Examiner—Jerome Jackson, Jr.
`(74) Attorney, Agent, or Firm—Antonelli, Terry, Stout &
`Kraus, LLP
`
`(57)
`
`ABSTRACT
`
`In a semiconductor integrated circuit device and a method of
`designing the same, design information about circuit cells
`each having a desired function are described as objects
`according to selected purposes. The pieces of design infor-
`mation are registered in a cell library as cell information
`capable of forming any of substrate potential fixed cells and
`substrate potential variable cells. Further, a data sheet com-
`mon to the substrate potential fixed cell and the substrate
`potential variable cell is offered to a user, so that the user is
`able to make a selection according to the user’s purposes.
`The substrate potential fixed cells and the substrate potential
`variable cells are mixed together on a semiconductor chip so
`as to be properly used according to the functions or the like
`of circuit portions in which the cells are used.
`
`53 Claims, 20 Drawing Sheets
`
`Aug. 21, 1997
`Dec. 9, 1997
`
`(JP)
`(JP)
`
`............................................. 9-224560
`9-338337
`
`
`..... H01L 27/092; H01L 27/118
`
`Int. Cl.7
`(51)
`(52) US. Cl.
`..............
`257/207; 257/338; 257/369
`
`(58) Field of Search ................................. 257/207, 338,
`257/369
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4/1992 Kim ........................... 257/338
`5,105,252 A *
`5/1994 Takahashi
`...... 257/207
`5,311,048 A *
`
`5,376,839 A * 12/1994 Horiguchi
`...... 327/541
`
`5,434,436 A *
`7/1995 Taniguchi
`...... 257/207
`9/1998 Yamada ...................... 257/207
`5,801,407 A *
`
`FOREIGN PATENT DOCUMENTS
`
`GB
`JP
`JP
`
`2269049
`63—090847
`6—085200
`
`1/1994
`4/1988
`3/1994
`
`
`
`
`
`0001
`
`AMD EX1028
`
`US. Patent No. 6,239,614
`
`0001
`
`AMD EX1028
`U.S. Patent No. 6,239,614
`
`

`

`US. Patent
`
`Jan. 22, 2002
`
`Sheet 1 0f 20
`
`US 6,340,825 B1
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 2 0f 20
`
`US 6,340,825 B1
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`FIG. 3(A)
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 3 0f 20
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`US 6,340,825 B1
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`US. Patent
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`Jan. 22, 2002
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`Sheet 4 0f 20
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`US. Patent
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`Jan. 22, 2002
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`US. Patent
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`Jan. 22, 2002
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`Sheet 6 0f 20
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`US 6,340,825 B1
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 7 0f 20
`
`US 6,340,825 B1
`
`FIG. 6(B)
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 8 0f 20
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`US 6,340,825 B1
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`US. Patent
`
`Jan. 22, 2002
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`Sheet 9 0f 20
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`US 6,340,825 B1
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`US. Patent
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`Jan. 22, 2002
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`Sheet 10 0f 20
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`US 6,340,825 B1
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 11 0f 20
`
`US 6,340,825 B1
`
`FIG. 10(A)
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 12 0f 20
`
`US 6,340,825 B1
`
`FIG. 11(A)
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`US. Patent
`
`Jan. 22, 2002
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`Sheet 13 0f 20
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`US 6,340,825 B1
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 14 0f 20
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`US 6,340,825 B1
`
`FIG. 13
`
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`
`FIG. 14
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`

`US. Patent
`
`Jan. 22, 2002
`
`Sheet 15 0f 20
`
`US 6,340,825 B1
`
`FIG. 15
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`

`

`US. Patent
`
`Jan. 22, 2002
`
`Sheet 16 0f 20
`
`US 6,340,825 B1
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 17 0f 20
`
`US 6,340,825 B1
`
`SER LOGIC
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`

`

`US. Patent
`
`Jan. 22, 2002
`
`Sheet 18 0f 20
`
`US 6,340,825 B1
`
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`US. Patent
`
`Jan. 22, 2002
`
`Sheet 19 0f 20
`
`US 6,340,825 B1
`
`FIG. 20(A)
`
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`

`US. Patent
`
`Jan. 22, 2002
`
`Sheet 20 0f 20
`
`US 6,340,825 B1
`
`FIG. 21(A)
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`

`

`US 6,340,825 B1
`
`1
`METHOD OF DESIGNING
`SEMICONDUCTOR INTEGRATED CIRCUIT
`DEVICE AND SEMICONDUCTOR
`INTEGRATED CIRCUIT DEVICE
`
`BACKGROUND OF THE INVENTION
`
`This invention relates to a method of designing a semi-
`conductor integrated circuit device, and a technique effec-
`tive in a case in which a plurality of circuits different in
`characteristic from each other are prepared as a cell library
`and a user selects a desired circuit from the cell library in the
`course of design of a semiconductor integrated circuit
`device. This invention also relates to a technique which is
`effective for use in the design of an ASIC (Application
`Specific Integrated Circuit), for example.
`It has been known that a semiconductor logic integrated
`circuit device principally using field effect transistors like
`MOSFETs (Metal-Oxide-Semiconductor Field Effect
`Transistors) is capable of operating at high speed as the
`threshold voltage of each MOSFET decreases; whereas,
`since a substantial leakage current is produced during its off
`state when the threshold voltage thereof is low, the use of a
`semiconductor logic integrated circuit device will lead to an
`increase in power consumption. As a characteristic of each
`MOSFET, a so-called substrate bias effect
`is known,
`wherein the threshold voltage thereof will go high as a
`reverse bias voltage between the source thereof and a base
`(substrate or well region) increases. Further, a technique for
`controlling a standby current has been described in Japanese
`Published Unexamined Patent Application No. Hei
`7-235608, for example.
`SUMMARY OF THE INVENTION
`
`A technique, wherein an inverter circuit or an inverter
`INV, capable of switching the potentials of bases (n well and
`p well) to a source voltage Vcc and a reference voltage Vss,
`and base or substrate bias voltages pr (pr>Vcc) and Vbn
`(Vbn>Vcc), as shown in FIGS. 21(A) and 21(B), is used in
`place of an inverter INV wherein the potentials of bases (n
`well and p well) shown in FIGS. 20(A) and 20(B) are fixed
`to a source voltage Vcc and a reference voltage Vss
`(Vcc>Vss), respectively, has been described in, for example,
`“ISSCC Dig. of Tech. Papers”, pp. 166—167, 437, February
`1996, or IEEE CICC, pp. 53—56, May 1996.
`According to this technique, the source voltages Vcc and
`Vss are applied to the bases (n well and p well) when the
`circuit
`is in operation (active),
`to thereby supply a low
`reverse bias voltage between the source and substrate or
`base, whereby each MOSFET is set to a low threshold so as
`to operate the circuit device at high speed. On the other
`hand, when the circuit
`is deactivated (at standby),
`the
`substrate bias voltages pr and Vbn are applied to the bases
`(n well and p well) to supply a high reverse bias voltage
`between the source and the base (well), thereby increasing
`the threshold of each MOSFET to reduce the leakage
`current, whereby low power consumption is provided. The
`present inventors have discussed the semiconductor inte-
`grated circuit device using MOSFETs capable of performing
`switching to the subtrate bias voltages. As a result, it became
`evident that the following problems were inherent in such a
`device.
`
`When the threshold of each MOSFET is controlled using
`the above described substrate bias effect in an attempt to
`realize an IC having desired characteristics, an inconve-
`nience occurs in that wiring or wires for supplying the bias
`voltages to the well regions used as the bases of the
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
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`
`respective MOSFETs are required in large numbers (Vcc
`line, Vbh/Vcc line, Vss line and Vbn/Vss line) and the area
`occupied by the circuit, and, in turn, the chip size of the IC,
`increases.
`
`The development of an ASIC or the like will call for
`consideration of two cases: a first case where a user desires
`an IC having low power consumption or reduced chip size
`even if its operating speed is slow; and a second case where
`the user desires an IC capable of operating at high speed
`even if the power consumption increases more or less. When
`the reverse bias voltage between the source and base (well)
`is increased or decreased in an attempt to realize the above-
`described ICs which are different in characteristic from each
`other, a maker must separately design substrate potential
`fixed circuit cells and substrate potential variable circuit
`cells suitable for the respective ICs and prepare them as
`separate cell libraries. Therefore, the design effort increases,
`and the labor, such as the extraction of characteristics
`including delay times or the like of the circuit cells, required
`when the user designs and evaluates the chip using these
`circuit cells,
`the description thereof in the specifications
`(data sheet or data book), etc. also increases, i.e., the burden
`of preparing respective specifications for corresponding cell
`libraries increases.
`
`An object of the present invention is to provide a design
`technique capable of implementing ICs which are different
`in cell type from each other without having to increase the
`burden on the designer.
`Another object of the present invention is to provide a
`design technique capable of easily implementing a semicon-
`ductor integrated circuit device in which its chip size, power
`consumption and operating speed are optimized.
`The above, other objects and novel features of this inven-
`tion will become apparent from the description provided by
`the present specification and the accompanying drawings.
`Asummary of a typical one of the features disclosed in the
`present application will be described as follows:
`Design information about circuit cells each having a
`desired function are described as objects according to
`desired purposes and are registered in a cell library regis-
`tered with a plurality of circuit cells for forming ASIC or the
`like as design resources in the form of cell information
`capable of forming any of substrate potential fixed and
`variable cells by only the deletion or addition of information
`about predetermined objects. Incidentally, the present cell
`library is stored in a storage medium such as a magnetic disc,
`an optical disk, a printed material or the like.
`As a typical one of the above-described circuit cells, a cell
`is known which comprises a pair consisting of a p channel
`MOSFET and an n channel MOSFET constituting a CMOS
`inverter which falls under the designation of a minimum unit
`in a circuit, for example. Others used as the circuit cells
`registered in the cell library may include a basic circuit cell,
`such as a flip-flop, a NOR gate, a NAND gate or the like, as
`frequently used in a logic LSI, a CPU peripheral circuit
`module, such as a CPU core used as a control circuit, a
`random access memory used as a memory circuit, a timer, a
`serial communication interface circuit or the like, and a
`macrocell like an A/D converter, a D/A converter or the like
`used as a signal processing circuit.
`According to the above feature, since only one kind of cell
`may be designed for circuits having the same function, a
`maker can reduce the burden on the design and labor, such
`as the extraction of characteristics such as voltage
`dependency, temperature dependency, delay times or the like
`of each designed cell,
`the description thereof in the
`specifications, etc., and, in its turn, achieve a reduction in
`cost as well.
`
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`US 6,340,825 B1
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`3
`Further, a semiconductor integrated circuit device
`wherein the chip size, power consumption and operating
`speed are optimized, can easily be implemented by properly
`using substrate potential fixed and variable cells according
`to the functions or the like of circuit portions used with cells
`on one semiconductor chip and mixing them together in this
`condition.
`
`Typical ones of various features of the present invention
`have been described in brief. However, the various embodi-
`ments of the present invention and specific configurations of
`these embodiments will be more fully set forth in the
`following description.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`While the specification concludes with claims particularly
`pointing out and distinctly claiming the subject matter which
`is regarded as the invention, it is believed that the invention,
`the objects and features of the invention and further objects,
`features and advantages thereof will be better understood
`from the following description taken in connection with the
`accompanying drawings in which:
`FIG. 1 is a plan view showing one example of the layout
`pattern a common cell topology for a CMOS inverter to
`which the present invention is applied;
`FIG. 2 is a cross-sectional view illustrating an example of
`a section taken along line II—II of FIG. 1;
`FIG. 3(A) is a plan view of a layout pattern showing an
`object A;
`FIG. 3(B) is a plan view of a layout pattern depicting an
`object B;
`FIG.
`3(C) is a plan view of an object CP;
`FIG.
`3(D) is a plan view of an object CN;
`FIG.
`3(E) is a plan view of an object DWL;
`FIG.
`3(F) is a plan view of an object DTH;
`FIG.
`3(G) is a plan view of an object E;
`FIG.
`3(H) is a plan view of an object F;
`FIG. 3(1) is a plan view of an object G;
`FIG 3(J) is a plan view of an object H;
`FIGS. 4(A) and 4(B) are, respectively, plan views show-
`ing layout patterns of a substrate potential fixed CMOS
`inverter and a substrate potential variable CMOS inverter,
`each constructed using a common cell topology for a CMOS
`inverter;
`FIG. 5(A) is a circuit diagram illustrating an example of
`a configuration of a substrate bias control circuit using
`substrate potential variable CMOS inverter cells;
`FIG. 5(B) is a plan view showing a layout pattern of
`substrate potential variable logic cells;
`FIG. 5(C) is a plan view illustrating a layout pattern of
`substrate potential fixed logic cells;
`FIG. 6(A) is a circuit diagram depicting another example
`of a substrate bias control circuit using substrate potential
`variable CMOS inverter cells;
`FIG. 6(B) is a plan view showing a layout pattern of a
`substrate potential fixed logic cell row;
`FIG. 7(A) is a plan view of a layout pattern illustrating
`another example of a common cell topology for a CMOS
`inverter;
`FIG. 7(B) is a plan view of a layout pattern depicting an
`object B';
`FIG. 8(A) is a plan view showing one example of a
`memory array to which the present invention is applied;
`FIG. 8(B) is a plan view of a detail of FIG. 8(A);
`
`4
`FIG. 9 is a plan view illustrating a memory mat having
`memory cell power supply portions to which the present
`invention is applied;
`FIG. 10(A) is a plan layout pattern view and FIGS. 10(B)
`and 10(C) are cross-sectional views showing an embodiment
`of a common cell topology for a memory cell power supply
`portion;
`FIG. 11(A) through FIG. 11(D) are respective plan views
`illustrating the layout pattern of an example of each object
`configuration of a memory cell power supply portion;
`FIG. 12(A) through FIG. 12(C) are respective plan views
`depicting the layout pattern of an embodiment of a cell
`topology of each memory cell;
`FIG. 13 is a circuit diagram showing one embodiment of
`a memory cell;
`FIG. 14 is a flowchart for describing a procedure for
`creating a library registered with cells;
`FIG. 15 is a diagram showing a portion of an inverter cell
`part prepared in Step ST3 of the flowchart shown in FIG. 14;
`FIG. 16 is a block diagram showing an example of an
`ASIC configuration used as one example of a semiconductor
`integrated circuit device constructed using a common cell
`topology according to the present invention;
`FIG. 17 is a block diagram illustrating another embodi-
`ment of an LSI which can be designed using a common cell
`topology according to the present invention;
`FIG. 18(A) to FIG. 18(C) are conceptual diagrams show-
`ing modifications of an LSI to which the present invention
`is applied.
`FIG. 19(A) is a cross-sectional view showing a structure
`of an LSI having a well-separate configuration, which is
`used as another embodiment of the present invention, and
`FIGS. 19(B) and 19(C) are respective plan views showing an
`example of each object configuration;
`FIG. 20(A) is a circuit diagram illustrating an equivalent
`circuit of a substrate potential fixed CMOS inverter;
`FIG. 20(B) is a cross-sectional view depicting a structure
`of the circuit shown in FIG. 20(A);
`FIG. 21(A) is a circuit diagram illustrating an equivalent
`circuit of a substrate potential variable CMOS inverter; and
`FIG. 21(B) is a cross-sectional view showing a structure
`of the circuit shown in FIG. 21(A).
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`Preferred embodiments of the present invention will here-
`inafter be described with reference to the accompanying
`drawings.
`A description will first be made of how to think about
`common cell
`topology, using a CMOS (Complementary
`MOS) inverter cell INV as an illustrative example.
`FIGS. 1 and 2 respectively show one example of a
`common cell
`topology for a CMOS inverter cell INV
`comprised of a pair of elements including a p channel
`MISFET (Metal Insulator Semiconductor FET) Qp and an n
`channel MISFET Qn. Of these, FIG. 1 illustrates an example
`of a layout pattern of a circuit cell and FIG. 2 shows an
`example of a sectional view taken along line II—II of FIG.
`1
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`In FIGS. 1 and 2, reference numeral 100 indicates a p-type
`single-crystal silicon substrate used as a base, for example.
`Reference numeral 1001'
`indicates a device or element
`
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`separator, and reference numerals 101 and 102 indicate an n
`well region (101a, 101b) and a p well region (102a, 102b)
`
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`US 6,340,825 B1
`
`5
`defined as relatively low-density n-type and p-type semi-
`conductor regions provided side by side in contact with each
`other, respectively.
`Reference numerals 103 and 104 respectively indicate a
`Vcc line and a Vss line used as power wired layers, which
`are respectively provided along the upper and lower sides of
`the n well region 101 and p well region 102. Reference
`numerals 105 and 106 respectively indicate a VBP line and
`a VBN line used as substrate potential supply wired layers
`located on the further outer sides of the Vcc line 103 and Vss
`
`line 104 and arranged in parallel to these wired layers. These
`power supply lines (103 through 106) are made up of a metal
`(aluminum) layer corresponding to a first layer, for example.
`Further,
`the power supply lines (103 through 106) are
`constructed so as to extend in a cell row direction.
`
`Reference numeral 107 indicates an active region in
`which the p channel MISFET Qp is formed. Reference
`numeral 108 indicates an active region in which the n
`channel MISFET Qn is formed. The active regions 107 and
`108 are defined by the device separator 1001'. Reference
`numerals 107a and 107b respectively indicate relatively
`low-density p-type semiconductor regions and relatively
`high-density p+type semiconductor regions provided in the
`n well region 101 and the active region 107. They serve as
`a source-to-drain region of the p channel MISFET Qp.
`Reference numerals 108a and 108b respectively indicate
`relatively low-density n-type semiconductor regions and
`relatively high-density n+type semiconductor regions pro-
`vided in the p well region 102 and the active region 108.
`They serve as a source-to-drain region of the n channel
`MISFET Qn. Reference numeral 109 indicates a gate elec-
`trode comprised of a polysilicon film or the like, which is
`provided so as to extend in the direction normal to the power
`supply lines 103 and 104 across the p well region 101 and
`the n well region 102. The gate electrode 109 is formed
`integrally with a gate electrode 109p of the p channel
`MISFET Qp and a gate electrode 10911 of the n channel
`MISFET On.
`
`The gate electrodes 10911 and 109p are respectively
`formed on the well regions 101 and 102 with gate insulating
`films 109i interposed therebeween. Further, a channel form-
`ing region of the p channel MISFET Qp is formed integrally
`with the n well region 101, whereas a channel forming
`region of the n channel MISFET Qn is formed integrally
`with the p well region 102.
`Further, reference numeral 110 indicates a common drain
`electrode comprised of, for example, the metal (aluminum)
`layer or the like corresponding to the first layer, which is
`disposed in the direction orthogonal to the power supply
`lines 103 and 104 across the n well region 101 and the p well
`region 102- The common drain electrode 110 is designed so
`as to be electrically connected via contact holes CHI and
`CH2 to the p-type semiconductor regions 107a and 107b and
`n-type semiconductor regions 108a and 108b respectively
`used as the source-to-drain regions at both ends.
`Incidentally, symbols CH3 indicate contact holes for
`electrically connecting the Vcc line 103 to the n well region
`101, symbols CH4 indicate contact holes for electrically
`connecting the Vss line 104 to the well region 102, symbols
`CH5 indicate contact holes for respectively electrically
`connecting the VBP line 105 to the n well region 101,
`symbols CH6 indicate contact holes for respectively elec-
`trically connecting the VBN line 106 to the p well region
`102, symbol CH7 indicates a contact hole for electrically
`connecting the Vcc line 103 to the p-type semiconductor
`regions 107a and 107b serving as the source-to-drain region
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`of the p channel MISFET Qp, and symbol CH8 indicates a
`contact hole for electrically connecting the Vss line 104 to
`the n-type semiconductor regions 108a and 108b serving as
`the source-to-drain region of the n channel MISFET Qn.
`Further, contact regions 111 through 114 comprised of
`high-density semiconductor regions for reducing contact
`resistance are respectively provided at substrate surface
`positions corresponding to the contact holes CH3 through
`CH6 of these contact holes, for supplying potentials to the
`well regions.
`the contact regions 111 and 113 indicate
`Incidentally,
`n+type semiconductor regions, which are formed in the
`same process as that for the semiconductor region 108b, for
`example. The contact regions 111 through 114 and the active
`regions 107 and 108 are defined by the device separator
`1001'. The device separator 100i is formed by a structure in
`which an insulating film is embedded in a groove defined in
`the base 100.
`
`Referring to FIGS. 1 and 2, symbol TH1 indicates a
`through hole used as an input
`terminal for electrically
`connecting the gate electrode 109 to a metal layer (upper
`wire or interconnection) 110' used as a first layer, which is
`located above the gate electrode 109 and is made up of an
`aluminum layer or the like. Symbol TH2 indicates a through
`hole used as an output terminal for electrically connecting
`the drain electrode 110 to a metal
`layer
`(upper
`interconnection) 110" used as a first layer, which is located
`above the drain electrode 110 and is comprised of an
`aluminum layer or the like. CH1 through CH9 and TH1 are
`formed at the same height.
`In FIG. 2, conductive layers 120 formed over the surfaces
`of the source-to-drain regions 107a and 107b and 108a and
`108b and the contact regions 111 through 114 are formed of
`a metal silicide layer (CoSi, TiSi or the like) for providing
`low resistance as well as on the surface of the polysilicon
`gate electrode 109. The conductive layers 120 and the power
`supply lines 103 through 106 are respectively spaced away
`from one another by an interlayer insulating film 121 and are
`respectively electrically connected to one another by con-
`necting bodies 122 comprised of a conductive material such
`as tungsten or the like charged into the contact holes CH1,
`CH2, CH3, CH4 and CH5 through CH8 defined in the
`interlayer insulating film 121.
`In the present embodiment, design data constituting the
`CMOS inverter INV is divided into the following objects A,
`B, CP, CN, DWL, DTH, E, F, G and H. That is, the VBP line
`105 and VBN line 106, the contact holes CH5, CH6, contact
`regions 113 and 114 for respectively connecting these to the
`n well region 101 and p well region 102, and the n well 101a
`and p well 102a corresponding to parts of the well regions
`101 and 102 just below or under the VBP line 105 and VBN
`line 106, respectively, constitute design data. These design
`data are prepared as one united object A (see FIG. 3(A).
`Similarly,
`the contact holes CH3 and CH4 and contact
`regions 111 and 112 for electrically connecting the Vcc
`line(103 arid the Vss line 104 to the n well region 101 and
`p) well region 102, and protrusions 103,a and 104a used for
`providing contact with the Vcc line 103 and the Vss line 104,
`respectively, constitute design data. These design data are
`prepared as one united object B (see FIG. 3(B).
`The active region 107, p-type semiconductor regions
`107a and 107b and gate electrode 109p constitute design
`data as the p channel MISFET Qp which constitutes the
`inverter cell. These design data are prepared as one united
`object CP (see FIG. 3(C). The active region 108, n-type
`semiconductor regions 108a and 108b and gate electrode
`
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`US 6,340,825 B1
`
`7
`10911 make up design data as the n channel MISFET On
`which constitutes the inverter cell. These design data are
`prepared as one unified object CN (see FIG. 3(D).
`As shown in FIGS. 3(C) through 3(J), other objects are
`also similarly configured as a unit of design data. That is,
`there are known, as other objects, an output contact structure
`(object DTH) comprising the drain electrode 110 (object
`DW) of the metal layer used as the first
`layer, and the
`through hole TH2 for connecting the drain electrode 110 to
`a wired layer (signal line) defined as an upper layer; an input
`contact structure (object E) comprising the through hole
`TH1 for connecting each gate electrode to an upper wired
`layer (signal line), and a buffer conductive layer BFM; a
`contact structure (object F) comprising the contact holes
`CH1, CH2, CH7 and CH8 for connecting the conductive
`layers such as the power supply lines 103 and 104, the drain
`electrode 110, etc. to the diffusion layers 107a, 107b, 108a
`and 108b, and high-density contact regions 107' and 108';
`and a well structure (object 11) for providing a conductive
`layer pattern (object G) constituting the power supply lines
`103 and 104, arid the well regions 101b and 102b.
`Since the contact regions 107' and 108' are respectively
`substantially formed in the same process as that for the
`p-type semiconductor regions 107a and 107b and the n-type
`semiconductor regions 108a and 108k and formed integrally
`therewith, the illustration of these in FIG. 2 is omitted for
`ease in understanding the drawing. Incidentally, chain lines
`and two-dot chain lines in the objects, A, B, F and G shown
`in FIG. 3(A), FIG. 3(B), FIG. 3(H) and FIG. 3(I),
`respectively, indicate border lines indicative of the outside
`shapes of cells and do not indicate the components that
`constitute the respective objects.
`The design data for the obj ects Athrough H are developed
`as hierarchical data called “plural layers” corresponding to
`a mask used in a production process- For example,
`the
`removal of the object A means that information about the
`layer constituting the object A is removed. A mask used in
`the production process is created by synthesizing or com-
`bining together the same data (hierarchical data) divided into
`or distributed to the objects A through H. For example, the
`gate electrode 109p of the object CP and the gate electrode
`10911 of the object CN are placed under the same layer
`(hierarchical data). A mask pattern for forming the polysili-
`con gate electrode 109 is formed by combining these hier-
`archical data together.
`Further, the wiring 110 of the object DWJT, the Vcc line
`103 and Vss line 104 of the object G, and the VBP line 105
`and VBN line 106 of the object A are the same hierarchical
`data. Amask pattern for forming the metal layer correspond-
`ing to the first layer is created by combining these hier-
`archiical data together. Thus, the design data for forming the
`same mask pattern constitutes the same hierarchical data. In
`regard to the inverter cell
`illustrated in the present
`embodiment, the same layer may be associated with com-
`ponents or elements of different objects other than the
`objects A and B.
`When data obtained by eliminating the design data for the
`object A from the cell design data for forming the CMOS
`inverter cell shown in FIG. 1 are used (i.e., when the design
`data for the objects B through H are used), a substrate
`potential fixed CMOS inverter INV having a circuit con-
`figuration shown in FIG. 20(A) is constructed as shown in
`FIG. 4(A) wherein a Vcc line 103 and a Vss line 104 are
`electrically connected to the n well region