370
`
`IEEE JOURNAL Of SOUD·STATE CIRCUITS. VOL. 24. "'0- 2. AI'RIL 1989
`
`A CMOS-Based Analog Standard Cell
`Product Family
`
`LARRY D. SMITH, MEMBER, IEEE, HENRY R. FARMER, MARIE KUNESH,
`MICHAEL A. MASSEITI, MEMBER, IEEE, DENNIS WILLMOIT, MEMBER, IEEE,
`ROBERT HEDMAN, RAY RICHEITA, AND TIMOTHY J. SCHMERBECK
`
`Abstract-Successful integration of mixed analog-logic standard cells
`has ~n demon.strated in a t.0-11m CMOS.based technology. Considera·
`lions for analog cell area, power distribution, noise immunity, circuit
`library design, and product test are described.
`
`N-FET
`
`P-FET
`
`I.
`
`INTRODUCTION
`
`A N analog standard cell (ASC) product family that
`
`provides a chip designer with the capability to inte(cid:173)
`grate structured analog functions with logic standard cells
`has been developed. Experimental 40K and llK equiva(cid:173)
`lent gate chips have been designed and manufactured. All
`the attributes of a high-performance logic technology and
`methodology have been maintained [1], [2]. Performance,
`density, multiple part number capability, and testabiJjty
`have not been compromised in extending the logic technol(cid:173)
`ogy and design methodology to include analog.
`This paper focuses on a description of the chip charac(cid:173)
`teristics and design considerations that enable precision
`analog circuitry to be integrated onto a high-performance
`logic chip. Analog primitive functions (i.e., op amps, com(cid:173)
`parators, voltage references, etc.) are laid out transistor by
`transistor in a custom design environment and then sub(cid:173)
`mitted to a standard cell library. A product chip is pro(cid:173)
`duced by selecting circuits from the analog and digital
`standard cell libraries and placing and wiring them into a
`chip image in one design environment. The chip image is a
`framework of power buses, wiring channels, inputjoutput
`(IjO) ports, and standard cell positions. Part of the image,
`called the analog terrain, is specially designed to protect
`sensitive analog circuits from the noisy logic environment.
`Details of these concepts and an overview of the CMOS(cid:173)
`based process, design system, and test methodology are
`described in this paper.
`
`Manuscript received August 22, 1988; revised December 2. 198&.
`L. D. Smith, H. R. Farmer, M. Kunesh, M. A. Masseui. and D.
`Willmott arc with IBM General Technology Division, Essex Junction , VT
`05452.
`R. Hedman. R. Richeua. and T. J. Scbmerbeck arc v.~th IBM Systems
`Product Division, Rochester. MN 55901.
`IEEE Log Number 8826146.
`
`(a )
`
`NPN
`
`MOSCAP
`
`p+ - Subttre1t
`
`( h)
`
`Fig. 1. Device cross sections: (a) n-FET and p- FET. and (b) n-p-n and
`MOSCAP.
`
`II. TECHNOLOGY
`
`The technology chosen for ASC products is an extension
`of a 5-V n-well CMOS logic technology with 1-J..tm mini(cid:173)
`mum ground rules, a single polysilicon layer, and two
`levels of metaL Bipolar transistors, resistors, and MOS
`capacitors have been added to the process to provide
`high-performance devices for analog circuits. These addi(cid:173)
`tions are accomplished with three additional masks and
`implants. A cross section of the devices is shown in Fig. 1.
`An 850-U/0 boron implant within then-well region forms
`the bipolar n-p-n base and a precision high-value resis(cid:173)
`tor. A 30-n;o phosphorous implant forms the n-p-n
`reachthrough and the low-resistivity back plate for a gate
`oxide capacitor. An additional mask step and implant
`
`0018-9200/89/0400-0370$01.00 ©1989 IEEE
`
`0001
`
`AMD EX1027
`U.S. Patent No. 6,239,614
`
`

`

`SMtiH e/ a/.: CMOS·BASLD ANALOG STANDARD CELL PRODUCT FAMILY
`
`371
`
`TABLE I
`BIPOLAR- C:-10S DEVICE PARA~I.EleRS
`1-1' 1
`v, ..
`82
`v,_,.
`- 69
`.39
`V._t r
`v,N mooch @ ~m IS
`O.:ha V, @~m
`60
`1'-P'
`fr
`V nr matchm1
`II,,
`111, maoclung
`Rc~I$IOn
`RcsJStivlty
`Tnlcrontt @ l~m
`M31t htng @! I S\lm
`C:\p.1citors
`C'"apaciutncc
`Molt hong @l iOpl'
`
`v
`v
`v
`mV
`mV
`
`GilT
`mY
`•.r.
`
`ohm<J•
`o/.
`%
`
`ff'/~m'
`%
`
`6.0
`I
`90
`10
`
`8SO
`R
`I.S
`
`1.4
`I
`
`form an antimony subcollector for the n-p-n and a low(cid:173)
`resistivity buried layer at the bottom of every n-well on the
`chip. T he buried layer improves n-p-n VC/i.SAT and current
`drive capability and increases latch-up immunity for the
`entire chip. The base technology plus the additional analog
`processing provide the analog designer with the devices
`with specifications shown in Table I. FET device perfor(cid:173)
`mance is not altered by the process adders and logic circuit
`performance is unchanged.
`The base technology that ASC was derived from would
`sustain no more than S V from drain to source. Technolo(cid:173)
`gies for mixed analog-logic products with medium-range
`analog voltage (0- 10 V and ± 5 Y) capability have been
`reported (3]. however. traditional analog voltages would
`require additional performance compromises and addi(cid:173)
`tional process complexity. A survey of ASC users revealed
`that most analog applications could be accommodated
`using 0- 5 Y. The technology chosen for ASC products
`retains high-performance logic circuits at the expense of
`medium-voltage analog capability. A low threshold-voltage
`n-channel device is avaiJable to revive some of the dynamic
`range lost by limiting power supplies to 5 Y.
`
`Ill. C IIJP IMAGE AND PACKAGE
`
`Several discrete chip image/package combinations are
`offered to satisfy the circuit count, chip 1/0, performance.
`and packaging requirements of ASC products. Chip im(cid:173)
`ages are divided into logic terrain for logic circuits, analog
`terrain for analog circuits, and peripberaJ terrain for 1/0
`circuits (analog or logic). The proportion of image area
`and chip 1/0 allocated to analog or logic is adjustable to
`meet an application's needs. Each 1/ 0 on the chip is
`predefined as power or signal. Pin-grid-array (PGA) im(cid:173)
`age/ package sets with IBM llip-clllp (C4) solder-bump
`technology and wire bond imagej package sets are avail(cid:173)
`able.
`The ASC 40K chip image is 9.44x9.35 mrn2• has room
`for 40 000 equivaJent two-way NAND circuits. and is pack(cid:173)
`aged in a 200-pin ceramic PGA. The image and package
`power plan are shown in Fig. 2. For Fig. 2. the entire left
`bay and lower third of the right bay are filled with analog
`terrain and the remainder of the interior is set up for logic.
`
`Gnd
`
`·~~~
`
`LOQIC
`Gnd
`
`,.,
`
`110 Uj Aru
`
`c
`
`:g 'l!
`d ( >
`<;>
`Gn
`~
`'
`. "f!f.:•
`Logic v 00
`l
`Gn d K
`~l
`I
`~;"
`
`<
`
`Gnd
`
`Logic
`Gnd
`
`IIOllAru
`.....
`l <>9IC
`Gnd
`(h i
`
`Gnd
`
`)
`
`-~£~>
`.., >
`..,
`..,
`c
`u >
`
`Gnd
`
`L09l~ d~
`
`Gnd
`
`c "'
`<;> >
`
`.., -... >
`.
`
`-·;~
`
`Gnd
`
`Fig 2. ASC 40K product (a) chip image. and (b) package power pl~n
`
`TABLE II
`ASC 40K C HIP PAD/ PIN C Oli NT
`
`ASC 40 K
`Ch1p lm•g•
`Gnd ·Mllog
`G nd-lo(!ic
`Gnd·•wo1Chable
`Vno·•nAlog
`Yno·logJc
`V0o·•witchablt
`Signal 1/0
`TO fAL
`
`Chip/l'ackagc
`Pad~
`120
`so
`44
`120
`S2
`2S
`180
`591
`
`l•;tcb~
`Pin'
`
`2
`8
`
`2
`4
`IRO
`196
`
`The periphery consists of power and signal 1/0. The
`image pad and package pin count is in Table II. There are
`591 solder bumps between the ASC chip image and the
`package. Logic power connections to the internal cell
`positions are located on the vertical columns in the center
`of the image. Solder bumps for analog power are located
`in the outer two circuit areas. A hole etched in the chip's
`final passivation layer connects the analog-power solder
`bumps only if a major analog power bus is at that location.
`This technique aJlows a common PGA package and wafer
`probe card to be used for products with varying analog
`content. The image is a standard Wienberger image with
`two rows of cell positions followed by a wiring area
`repeated 35 times in the vertical direction (51.
`For all ASC images, the analog power-bus structure can
`be grown from each comer of the chip with a maximum of
`
`0002
`
`

`

`372
`
`four separate analog power terrains on the chip. It is
`created during chip physical design. Digital power is re(cid:173)
`moved automatically £rom the analog area. Sensitive ana(cid:173)
`log functions are grouped together on the chip to increase
`noise immunity. The maximum size of one analog area is
`one quarter of the chip width and the full chip in height.
`The middle section of an ASC image is always logic.
`Package connection for logic power is similar to the CSC
`image which contains no analog. There are two pair!> of
`second-metal stripes running in the vertical direction on
`the image breaking the image into three parts. Each pair
`contains logic V00 and Gnd and is connected to the
`package through numerous bump joints. The vertical stripes
`are connected to first-metal buses running in the horizon(cid:173)
`tal direction. Internal logic circuits get their power from
`these buses.
`There are two wide rings of second metal around the
`peripheral of the image. The rings provide power for the
`1/ 0 circuits. Numerous bump joints and package pins
`supply power to the second-metal rings to minimize induc(cid:173)
`tance, thereby maximizing the number of off-chip drivers
`that can switch simultaneously. The rings are broken into
`discrete sections of analog and logic power by the design
`system. Logic drivers are not allowed to access analog
`power to eliminate spikes on analog power buses. The
`number of l/0 slots allocated to analog is determined by
`the amount of analog on the chip. Chip assembly tools
`sense the presence of analog in the interior of the chip and
`automatically separate adjacent l/0 power buses for ana(cid:173)
`log. Additional l/0 slots are allocated when an analog
`1/ 0 cell is placed in a section that was formerly logic.
`Analog pins at the package level are allocated in a consis(cid:173)
`tent way.
`The ASC llK chip image is 5.5 x 5.5 mm2 and bas room
`for 11 000 equivalent two-way NAND circuits and 68 chip
`1/0 (signal and power). It can be packaged with wire
`bond, TAB, or flip-chip technologies. The basic structure
`of the ASC llK chip image is similar to the ASC 40K.
`This allows the use of a common design system and
`common circuit libraries to construct both PGA and wire
`bond chips. The major difference with this image is that all
`package-to-chip connections are at the edge of the chip, a
`requirement for wire bond images.
`
`IV. A NALOG PowER Bus
`
`A grid power-bus structure in which a single analog
`standard cell is supplied from many directions was selected
`over a tree structure which forces analog power to take one
`direct path. Several criteria were considered in the analog
`power-bus design. First, the power bus determines the cell
`position framework for the chip image and the analog unit
`cell size. Standard cells may be several unit cells in size.
`Second, voltage drop in the power bus determines the
`minimum power supply voltage available to analog cir(cid:173)
`cuitry. Finally, equivalent series resistance in the power
`bus must be minim.iz.ed to reduce the power supply noise
`
`I CCL JOURNAL 0~ SOLID·STIITE CIRCUITS. VOL. 24. NO. 2 , APRIL 1989
`
`Anolov
`O..lgn
`
`......
`
`(Ooublo Row)
`
`I ,_
`, __
`
`I
`. ..
`1,_
`
`Vo<tlcol
`Second-Mot ol
`
`Hotbofltol
`Flrat-Mot ol
`Powerlua
`Hort-.tal
`Wk1ngArea
`
`' 1-
`
`I
`
`I
`
`I
`
`' ..
`
`t
`
`it
`
`'t
`
`M
`
`S.C:ond- Motal
`Bu.•••• tor
`Solder Bump•
`
`I
`VOI'IIcol
`Wiring Aroa
`Fig. 3. Analog power bus six double rows high.
`
`Gnd
`1 M
`J
`
`Gnd
`
`'\LSTs
`
`\
`M t-M2
`lnt..-connectron
`tal
`Fig. 4.
`(a) Fo ur anal<>& and (b) 24 IQ&ic unil cells_
`
`( b )
`
`(IR drop) generated when ac current is drawn by analog
`circuits. Fig. 3 is an example of an analog power bus
`consisting of horizontal fi rst-metal stripes and vertical
`second-metal stripes. There are six double rows of analog
`unit cells separated by seven horizontal wiring areas. Large
`second-metal buses at the top and bottom of the power-bus
`structure connect to the package through solder bumps.
`Details of the analog power-bus design are given in the
`following paragraphs.
`The size of the analog unit cell was determined by
`considering the average size of analog circuits, number of
`wiring channels required to service the unit cell, compati(cid:173)
`bility with the existing logic image, and power-bus electri(cid:173)
`cal analysis. Analog and logic unit cells are compared in
`Fig. 4. Analog or logic service terminals (ASTs or LSTs)
`are the ports by which a global wiring program can access
`a circuit. Circuit specifications generally require analog
`circuits to be larger than logic circuits because device
`matching. noise properties. high active load impedance,
`and low output impedance are improved with large de(cid:173)
`vices. Consideration of these factors resulted in an analog
`unit cell which is six times larger than the logic unit cell in
`this 1-j.Lm ground-rule technology.
`First-metal power buses in the logic terrain are conve(cid:173)
`nient for logic gates but severely restrict the placement of
`large analog devices. It is more efficient to distribute
`analog power on second metal. because it is less resistive
`than first metal. The power-bus grid is completed with first
`
`0003
`
`

`

`SMITH Cl a/.: CMOS-BASED ANALOG STANDARD CELL PRODUCT fAMJLY
`
`373
`
`tal
`Fig. 5. Power-bus electrical analysis: (a) de vol tage drop from fully loaded ana log power hus: and (h) equivalent scric,
`resistance to local cell location.
`
`18
`
`TARtE Ill
`POWER-Bus COMPAIUSON
`
`SO ohms
`O.R ohm•
`
`metal in the wiring area rather than in the circuit design
`area. First metal is budgeted for circuit layout, horizontal
`wiring channels, and power redistribution. Second metal is
`available for circuit layout, but must be constrained to
`wiring channels. Analog circuits access power by intercon(cid:173)
`nections to second metal. The analog power bus reduces
`the available wiring area in the analog terrain. but does not
`impact wirability because analog circuits have a lower
`service terminal density than logic circuits.
`DC voltage drop and equivalent series resistance were
`determined by electrical analysis of the analog power bus.
`Two networks of resistors were described to a circuit
`analysis program: one for V00 and one for Gnd. The
`resistor values were calculated from the resistivity of firs t
`and second metal and the dimensions of the power-bus
`s tripes. The analog terrain chosen for analysis was 15
`double unit cells high and 18 unit cells wide. First, the
`voltage drop along the fully loaded power bus was deter(cid:173)
`mined with a 0.5-mA current sink placed at each analog
`unit cell location. Fig. 5(a) shows the voltage drop at each
`unit cell location for a fully loaded bus with respect to the
`voltage supplied to the module package. Analog circuits
`must be designed to tolerate a 50-mV power supply drop
`from the card to the circuit location. A maximum of
`12.5-mV common-mode voltage difference is expected be(cid:173)
`tween randomly placed circuits referenced to either V00 or
`Gnd. Next, the equivalent resistance of the power supply
`network from the circuit back to the card was determined.
`A 1-mA current source was placed at selected cell posi(cid:173)
`tions on the grid and V00 and Gnd were short-circuited at
`the package terminals. Fig. 5(b) shows the power supply
`resistance network having a maximum of 800 mY with
`1 rnA applied. The equivalent resistance from the worst(cid:173)
`case cell position to the card is 0.8 n.
`Voltage drop and series resistance for tree and grid
`power-bus structures are compared in Table Ill. The grid
`gives less voltage drop and equivalent resistance. The
`performance of the analog power-bus structure is well
`
`inside the specification limits known to cause chips to
`malfunction {6).
`
`V. NOISE CONSIDERATIONS
`
`Noise is the greatest concern in integrating analog func(cid:173)
`tions onto a logic chip. Major contributors to noise arc
`power supply coupling, crosstalk. substrate fluctuations,
`and stray carriers (holes and electrons) [7). The man-made
`noise is typically several orders of magnitude greater than
`the thermal shot and f[jcker noise associated with physical
`silicon devices. The remainder of this section describes
`how ASC products are protected from the noise associated
`with analog and logic integration with the a nalog power-bus
`structure, signal separation, and a specially designed n-well
`structure.
`Power supply coupling occurs when circuits draw power
`current with a signal component. Analog and digital V00
`are totally separated and grounds meet only a1 the chip
`substrate to eliminate logic signal components from analog
`power buses (4]. The power supply voltage at the circuit
`terminals has noise proportional to the signal current anq
`equivalent series resistance in the analog power bus. Power
`supply noise is minimized on ASC chips by reducing the
`resistance of the analog power bus and decoupling with an
`n-well capacitor described later.
`Crosstalk occurs when a noisy analog or logic wire is
`coupled capacitively with a nearby quiet wire. Coupling is
`proportional to the voltage transitions and frequency of
`the noisy wire. Logic wires transiting between V0 0 and
`Gnd at clock frequency are potential noise makers. Prod(cid:173)
`uct performance may be affected if 10 mY of noise is
`coupled to a wire with a quiet analog signal. The magni(cid:173)
`tude of capacitive coupling can be calculated from basic
`electromagnetics. For example, in Fig. 6, a quiet analog
`wire with a sensitivity of 10 mY is parallel to a noisy wire.
`The output resistance of the analog driver circuit and the
`parasitic capacitance on the driven wire determjne a pole
`frequency. Above the pole frequency. the a nalog output
`has little effect on the quiet wire. The voltage on the quiet
`wire is determined by the capacitance divider between the
`noisy and quiet wires and the quiet wire to ground plane.
`For the specifications and the parasitic capacitance shown.
`the pole is 513 MHz and the impedance divider is 10.6
`
`0004
`
`

`

`374
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 24, NO.2, APRIL 1989
`
`Logic Circuit
`
`Output Swing: 0 to 5 V
`Rise Time: 1 nsec
`
`Analog Circuit
`
`Output Precision: 10mV
`Output Impedance: Ro;; 1
`Kohm
`Input Impedance: C1 e 200 IF
`
`A$$Umtd Noise Frequency: ·500 MHz
`Cn = 47 fF
`Wire Capacitance:
`CLo=631F
`Pole Freqiency = - --'------ - :513MHz
`2 PI Ro (CLo + Cu + C;l
`
`j w RoC LL
`t +J w Ro(CLo+CLL+Cr) • 0.106 angle 4.7 Degree
`
`vnols•
`v,oolc
`Fig. 6. Crosstalk noise is a potential problem. A noisy logic wire with
`5 V of signal is adjacent to a quiet analog wire with 10 mV of signal.
`Capacitive coupling is 10.6 percent or 530 mV of noise injected onto
`the quiet wire.
`
`percent. If Vvv is 5 Y and the rise time on the noise
`waveform is 1 ns (noise frequency is 500 ·MHz), 530 mY of
`noise appears on the analog wire with a si'gnal sensitivity
`of 10 mY. Crosstalk noise is clearly a potential problem on
`integrated analog and logic chips.
`Crosstalk is re~uced by minimizing the output resistance
`of analog circuits and increasing the distance between
`sensitive and noisy circuitry. Below the pole frequency,
`crosstalk is proportional to the output resistance of the
`driving circuit. The capacitive divider dominates above the
`pole frequency and noise is controlled by separation of
`wires. With the wiring channel pitch and technology cho(cid:173)
`sen for ASC products, Coupling between wires is reduced
`by appro~mately 20 dB for every wiring channel that
`separates noisy and quiet wires. The design system creates
`one clear wiririg channel between analog and logic wires. A
`constant potential surface in the form of a grounded
`conductor in· the clear wiring channel can be used to
`separate and further reduce capacitive coupling between
`wires. Where extreme noise immunity is required, wiring
`areas may be dedicated to quiet wires [8], [9].
`A specially designed n-weU structure has been developed
`for ASC products. It protects analog circuits from free
`carriers and substrate noise and provides power supply
`decoupling capacitance. Fig. 7(a) shows the n-well struc(cid:173)
`ture at the end of the analog circuit design area and lying
`beneath the wiring area i.n the analog terrain. N-well
`resides below thick oxide so global wiring capacitance is
`not affected and is biased using first-metal power redistri(cid:173)
`bution straps of the analog power bus.
`
`I Book ~ Anelog Power and r- Book
`wl::ITJ=
`J,
`
`4.5
`
`_j_
`}s
`
`~
`e- 2:
`
`~
`2:
`
`e
`
`(a!
`
`Design Ar11
`
`- Wiring Channels -
`
`Design Area -
`
`I
`~
`
`~ 1-
`.L
`$ DecoupllngT
`/ Capacitance
`
`Highly Doped Subs trate
`Substr1t1
`Current
`
`( b)
`
`Fig. 7. N-wcll structure for carrier barrier, substrate contact, and de(cid:173)
`coupling capacitance: (a) layout. and (bl cross section.
`
`CircuitJype
`ADCs
`
`llufTc,.
`
`DACs
`
`Comparators
`
`Op i\Jnps
`
`Linear Amps
`Variable Gain
`Amps (VGA)
`VCOs
`
`Reference
`Filters
`
`TABLE IV
`ANALOG LIBRARY F UNCTION TYPES
`
`Typical l'erfonnance
`6 llit, 85 Mllz, nash Ajl)
`16 nit, J Kllr. (864 Kllr. clock). ovcr.wnpling /1/D
`LFIIT, 68 Mll7. 3·dR fn:qucncy into 5 pF parasitic,
`500 ohm load
`Dipolar, ISO Mllz 3dD, differential current oulput
`CMOS. 12 bit. 500 Kl17., T, - 2 ~s/ KJI>.
`DipoLar, 5 bil, 27 Mll7., bi·directional current output
`CMOS, V,. -
`:ldOmV,clnckfn:q = 2. 59 Mllz
`Bipolar, V~= * 3 mV, 10 ns rc.<ponsc to .SO mV step
`with 5 m overdrive, gain> Jk
`3 stage CMOS, GllW s [O Mllz. R4 dll/1 0 , v.,• J mV,
`CL• IO pF
`ISO M117. bandwidth x2 video amplifrcr
`Dipolar, 3·dll freq e 100 Ml 17., II ~ gain < f,
`Bipolar. 3·dR freq c 100 Mllr., :1: 40 d R gain range
`CMO$, center freq - 75 Mil?.
`DiCMOS. center frcq = 100 Mllr.
`2.3V, 3%, T C ~ .SO ppmrc. I'SRR • 80 dll (de)
`7 pole lluuerwonh 10 Mllr. active low"''"
`2nd order 'IWIN-T 10 Mll7. 3ctivc notch frltcr
`
`The n-well structure forms an effective carrier barrier
`against free holes and electrons injected into the substrate
`by logic or analog circuits. The n-well is 4.5 J.Lm deep and
`3.5 J.Lm above a highly doped substrate as shown in the
`cross-section drawing, Fig. 7(b). It is biased at Vvv and
`forms an effective collector of electrons. Holes are con(cid:173)
`tained by the n-well structure or forced down into the
`highly doped substrate. Stray electrons and holes are pre(cid:173)
`vented from crossing circuit design rows. N-well straps are
`used to exclude carriers from sensitive circuits within a
`design row or to contain carriers in circuits that emit them.
`A "safe area" for substrate contacts is provided by the
`n-well structure. Holes are forced down into the highly
`
`0005
`
`

`

`S~lll H et u/. : C:MOS·RASLI) ANALOG STANIJI\RO Cl:U. PRODUCT ti\MILY
`
`375
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`T16 t NF ET REFI
`
`Fig. 8. Library reference circui t ~chemutic.
`
`doped 50-m!l/0 substrate and stay there until attracted
`up by an ohmic contact in the p-cpi. The IR voltage drop
`associated with current flowing from the highly doped
`substrate up to a substrate contact can alter the potential
`at the epi surface. Through body effect, this will alter the
`threshold voltage and matching properties of an FET or
`induce latch-up in extreme cases. Substrate contacts are
`therefore avoided in analog standard cells and placed in
`the wiring area where they arc contained by the n-well
`structure. Voltage drop in the epi under the contact has no
`detrimental effect on analog circuits and poses no latch-up
`exposure. T he resistance from the analog power bus to the
`highly doped substrate is typically 5.6 Q and compares
`favorably wi th impedances previously repon ed [6]. T he
`analog and logic substrate contacts compete for control of
`the substrate voltage. The associated noise risk is necessary
`to avoid latch-up.
`An effective decoupling capacitor from V00 to Gnd is
`formed by the n-well structure. Both the bottom surface of
`the n-well and the sidewalls contribu te capacitance. The
`holes in the n-well increase the sidewall area and therefore
`the "capacitance density." Typical analog terrains will
`have at least 150-pF capacitance distributed close to ana(cid:173)
`log circuits for maximum effect.
`
`V I. ANALOG CIRCUIT LIBRARY
`
`A mixed bipolar- CMOS process provides the designer
`with maximum flexibility for circuit design an implementa(cid:173)
`tion. The ObJectives and concerns for CMOS-based analog
`libraries and the possibility of analog cell compilation have
`been previously reported (10), (11]. The technology de(cid:173)
`scribed above provides a broad menu of devices including
`p- and n-channel FITs. bipolar transistors, capacitors,
`
`and resis tor~ for building a library of analog circuit~.
`Bipolar transistors dominate in the higher frequency cir(cid:173)
`cuits because of larger transconductance. smaller output
`impedance, and larger fr· Table IV shows circuit function
`classifications in the analog library. Each circuit classifica(cid:173)
`tion has many different circuits with performance appro(cid:173)
`priate for a wide range of information processing applica(cid:173)
`tions. An analog circuit's function may be modified by
`interconnecting several standard cells from the library. For
`example, the gain, bandwidth. and output impedance of an
`operational amplifier may be adjusted by the choice of
`resistors and capacitors in the input and feedback net(cid:173)
`works surrounding an operational-amplifier gain stage.
`All analog circuits have a maximum envelope of perfor(cid:173)
`mance. For example. a specific operational amplifier has
`an open-loop gain and uni ty-gain bandwidth inheren t in
`the topology and physical design of the circ uit. Attach(cid:173)
`ment of passive input and feedback networks will not alter
`these specifications. Performance beyond the gain- band(cid:173)
`width product of the operational amplifier will require
`alteration of topology or physical design and result in a
`new circuit in the library. Each circuit represents a design
`trade-off between size. power dissipation. speed. accuracy.
`PSRR. and other performance parameters. High-perfor(cid:173)
`mance products often require new analog circuits to meet
`aggressive performance objectives. Analog libraries will
`have a propensity to grow even faster than logic libraries.
`A library of general-purpose analog standard cells re(cid:173)
`quires a s tandard voltage reference scheme (12]. [131. Fig. 8
`shows the s tandard reference circuit used for the ASC
`library. It has a 3-percent tolerance with 50-ppm;oC tem(cid:173)
`perature coefficient and 80-dB PSRR with no trimming. A
`standard voltage reference has tolerance. temperature sta(cid:173)
`bility. PSRR. and global circuit matching advantages over
`
`0006
`
`

`

`376
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 24 , NO. 2, APRIL 1989
`
`(a)
`
`(b)
`
`Fig. 9. Chip photographs: (a) analog circuit test chip. (b) l!K ASC chip. and (c) 40K ASC chip.
`
`(c)
`
`the alternative of stand-alone circuits that generate local
`references. The reference described here accommodates the
`needs of the majority of circuits in the library and mini(cid:173)
`mizes overhead in each circuit. It produces a temperature(cid:173)
`independent voltage and current reference along with
`p-channel, n-channel, and n-p-n current-source hias refer(cid:173)
`ences. The p-channel, n-channel, and n-p-n references are
`potentials which, when applied to the appropriate device,
`produce a current. This current produces a temperature
`and power supply independent voltage when dropped
`across a base implant resistor. It is based on a bandgap
`cell similar to the one described by Brokaw [14). Circuit
`details are now described.
`A capacitor at BCO stabilizes the reference. Node DIS(cid:173)
`ABLE is pulled low by a power on reset circuit during low
`power supply conditions to limit substrate currents emitted
`
`by saturated bipolar transistors. A variable multiple of the
`bandgap voltage is produced at node V REF· An n-p-n
`emitter follower from node V REF! produces buffered ver(cid:173)
`sions of V REF for use in analog circuits. V REF is converted
`to a temperature-compensated current at node I REFJ· V REF
`is also converted at node I REF v to a current which repro(cid:173)
`duces a scaled copy of VREF when dropped across a base
`implant resistor. Using current mirrors, multiple copies of
`the I REFI or I R EFV currents are produced with good chan(cid:173)
`nel isolation. Nodes PREF• NREF• and A REF are tap points
`to connect p-cbannel gates, n-cbannel-gates, and n-p-n
`bases, respectively, to produce mirrored or scaled versions
`of the lREFv current. The FET device W/ L ratio is scaled
`to adjust the current. By using different size and type of
`emitter degeneration resistors, some scaling and tempera(cid:173)
`ture-coefficient tailoring of the n-p-n current-source value
`
`0007
`
`

`

`SMITH eta/.: CMOS·IlASEI> ANALOG STANDARD CELL PRODUCT FA~fli.Y
`
`377
`
`is possible. All circuits on an experimental 11 K chip used
`this reference and resulted in excellent tracking between
`circuits. No noise problems due to coupling over the
`common reference were found.
`Test chips for discrete circuit characterization were man(cid:173)
`ufactured. Fig. 9(a) shows an ASC test chip with analog
`circuits attached to probe pads for test purposes. Struc(cid:173)
`tures that aid the characterization effort such as feedback
`loops, linear output buffers, impedance matching resistOrs,
`etc. are included in silicon. Output buffers are duplicated
`in a stand-alone situation so that the gain/phase response
`of the output buffer can be accounted for in the ac
`response of the device under test (DUT). Test chip hard(cid:173)
`ware is used for both wafer- and module-level characteri(cid:173)
`zation. Measured results compare favorably with simula(cid:173)
`tion.
`Analog circuits on the test chip were stressed to evaluate
`circuit performance over product lifetime. Elevated tem(cid:173)
`perature and voltage were used to accelerate circuit aging
`rates. Circuit degradation due to hot-electron, ionic, and
`negative-bias temperature instability (slow trapping) relia(cid:173)
`bility mechanisms were measured by tracking input offset
`voltage shifts of several CMOS operational-amplifier cir(cid:173)
`cuits [1 5]. Test measurements were taken in a geometric
`progression in time and correlated to actual device power(cid:173)
`on hours. The stress results revealed no new reliability
`mechanisms occurring in product lifetimes and were con(cid:173)
`sistent with device performance previously measured on
`device test chips. They confirmed that large channel length
`FET's and careful circuit biasing reduce the impact of
`known reliability mechanisms to less than 1 mV of input
`offset drift.
`
`VII. D ESIGN SYSTEM
`
`The ASC design system is an extension of the CSC
`design system [2]. Circuits listed in Table IV are designed
`for the ASC library with a self-contained set of standard
`cell design tools. The ASC design methodology is a combi(cid:173)
`nation of electrical design, physical design. and design data
`translation tools. Electrical design tools provide for design
`capture. device generation, and circuit simulation without
`parasitics. Physical design tools provide for device place(cid:173)
`ment with template aids, technology ground-rule checking,
`logical-to-physical checking, and circuit simulation with
`parasitics. Iteration between electrical and physical design
`tools is required until simulation yields successful results.
`Circuit design data are then translated into design rules for
`chip assembly tools to use.
`The chip design methodology assembles standard cells
`onto the chip image and compiles data suitable for manu(cid:173)
`facturing. Design verification and physical design enhance(cid:173)
`ments have been made to the original logic design system
`to accommodate the analog terrain, noise isolation struc(cid:173)
`tures, and multiple wire widths. Design verification tools
`such as synthesis, delay, and timing concentrate on digital
`design areas and analog/digital interfaces. Mixed-mode
`
`simulation is performed on clusters of analog standard
`cells (i.e., filters. DAC's, ADC's. etc.) by modeling them as
`transfer equations and coding them as behaviorals