4,001,869
`[11]
`United States Patent
`Jan. 4, 1977
`[45]
`Brown
`
`
`[19]
`
`i
`
`[54] MOS-CAPACITOR FOR INTEGRATED
`CIRCUITS
`
`'
`[75]
`Inventor:
`John L- Brown, Shrewsbury, Mass.
`[73] Assignee: Sprague Electric Company, North
`Adams, Mass.
`
`[22]
`Filed:
`June 9, 1975
`[21] App]. No.2 585,278
`
`[52] US. Cl. ................................... 357/51; 357/14;
`357/23; 357/48; 357/54; 357/91; 148/15;
`148/ 175
`Int. Cl.2 ................... H01L 27/04; H01L 29/94
`Field of Search .................. 357/51, 54, 48, 91.
`357/23, 14
`
`[51]
`{58]
`
`[56]
`
`3:23:33:
`3,727,151
`3.860:836
`3,864,817
`3,892,596
`3,902,926
`
`’
`
`5
`
`References Cited
`UNITED STATES PATENTS
`.
`
`213.613 Eager“ iii/i2
`Koehler .1112:
`:::-'331/116 M
`4/1973
`Pedersen ............................. 357/14
`1/1975
`2/1975
`Lapham, Jr. et a1.
`............... 357/51
`7/1975
`Bjorklund et a1.
`................... 357/51
`9/ 1975
`Perloff et al.
`........................ 357/91
`
`OTHER PUBLICATIONS
`Gay et al, “Capacitors for Monolithic Circuits,” SCP
`and Solid State Technology, Apr. 1966, pp. 24—27.
`Primary Examiner—Wi11iam D‘ Larkins
`Assistant Examiner—Marcus S. Rasco
`Attorney, Agent, or Firm—Connolly and Hutz
`[57]
`ABSTRACT
`In an integrated circuit formed in a P-type silicon crys—
`tal body having an N-type epitaxial
`layer grown
`thereon, and having at least one bipolar transistor and
`at least one ion implanted resistor formed therein, a
`MOS type capacitor is formed requiring no additional
`processing steps beyond those normally required to
`form the resistor and the transistor. The capacitor com-
`prises a first electrode of P-type material, a thin layer of
`silicon oxide grown simultaneously with the oxide
`through which the resistor is implanted, and a metal
`electrode over the oxide dielectric layer. The capacitor
`of this invention exhibits a relatively high capacitance
`per unit area of integrated circuit real estate and may
`be manumcmred "Sing only Process Steps that are 'e'
`quired to form bipolar transistors and ion implanted
`resrstors.
`
`'
`
`8 Claims, 6 Drawing Figures
`
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`US. Patent No. 6,239,614
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`0001
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`AMD EX1020
`U.S. Patent No. 6,239,614
`
`

`

`US. Patent .
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`Jan. 4, 1977
`
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`1
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`4,001,869
`
`MOS-CAPACITOR FOR INTEGRATED CIRCUITS
`BACKGROUND OF THE" INVENTION
`
`This invention relates to integrated metal-oxide-
`semiconductor (MOS) type capacitors; and more par-
`ticularly to such a capacitor that is formed in an inte-
`grated circuit having at least one bipolar transistor and
`at least one ion implanted resistor.
`Such capacitors are typically formed in an integrated
`cicuit employing only process steps that are required
`for forming the other integrated components. In this
`manner the number of steps required for forming the
`integrated circuit are minimized. It is well known that
`the quality of an integrated circuit tends to be degraded
`and the cost increases as the number of process steps
`required increases. For reasons that will be explained
`more fully, the conventional integrated MOS capacitor
`has an oxide layer that typically ranges in thickness
`from above 3000 to 6000 angstroms, and it overlies a
`semiconductor electrode of N-type conductivity when
`the crystal body is of P—type conductivity, as is almost
`always the case. The adjacent underlying semiconduc—
`tor electrode being of N-type conductivity is partly
`responsible for the dielectric oxide layer being so thick.
`Thinner oxide layers are desirable to provide a high
`capacity per unit area of the integrated circuit surface.
`Many integrated circuits have employed the conven-
`tional MOS capacitors that occupied as much as a third
`of the total area.
`
`It is therefore an object of this invention to provide
`an integrated MOS capacitor requiring significantly
`less circuit area than a conventional MOS capacitor
`having the same capacity value.
`It is a further object of this invention to provide a
`small integrated MOS capacitor that can be formed by
`processes already required by the other of the inte-
`grated components, when such other components in-
`clude at least one bipolar transistor and at least one ion
`implanted resistor.
`It. is yet a further object of this invention to provide
`an integrated MOS capacitor capable of being formed
`by routine process steps to a close capacity tolerance.
`SUMMARY OF THE INVENTION
`
`In an integrated circuit including at least one bipolar
`transistor and at least one ion implanted resistor, there
`is formed a metal-oxide—semiconductor (MOS) type
`capacitor. The semiconductor capacitor electrode is of
`P-type conductivity, being capable of being formed
`simultaneously with the formation of the P—type base of
`a NPN type transistor or capable of being formed si-
`multaneously with the formation of the P-type isolation
`walls that define and isolate the epitaxial region con—
`taining the elemental
`integrated components. More
`generally, when there is included an ion implanted
`resistor and an integrated transistor that contains a
`P~type region of moderate to high impurity concentra-
`tion equivalent to a sheet resistivity of about 300 toO.l
`ohms per square, such as isolated vertical and lateral
`PNP types or PNPN devices, then the MOS capacitor
`of this invention may be formed in that integrated cir-
`cuit entirely by process steps that are already necessary
`to form the ion implanted resistor and the transistors.
`The oxide dielectric layer of the capacitor is from 1000
`to 3000 angstroms thick, being formed simultaneously
`with the high quality oxide layer having been grown
`over the ion implanted resis‘tor‘b‘ody. This thickness of
`
`5
`
`10
`
`IS
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`0003
`
`2
`the oxide layer that is suitable for use over ion im—
`planted resistors,
`is about half the thickness of the
`oxide layers employed as the dielectric layer in a con-
`ventional integrated MOS capacitor having a N-type
`semiconductor electrode. Therefore the MOS capaci—
`tor of this invention requires about half the surface area
`on the integrated circuit Compared with that required
`for the conventional MOS capacitor of the same capac-
`itance.
`'
`‘
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`FIG. 1 shows a cross sectional view of a portion of a
`conventional
`integrated circuit
`including a conven-
`tional MOS type capacitor.
`.‘
`FIG. 2 shows an equivalent circuit of the capacitor of
`FIG. 1.
`
`FIG. 3 shows a cross sectional view of a portion of an
`integrated circuit including a MOS type capacitor of
`this inventiOn.
`‘
`’
`FIG. 4 shows an equivalent circuit of the capacitor of
`FIG. 3.
`
`FIG. 5 shows a cross sectional view of a portion of an
`integrated circuit including another MOS type capaci-
`tor of this invention.
`FIG. 6 shows an equivalent circuit of the capacitor of
`FIG. 5.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The MOS capacitor conventional employed in inte-
`grated circuits is illustrated in FIG. 1, along with a
`typical ionimplanted resistor and a typical NPN transis—
`tor, each being formed in separate portions 11, 12 and
`13, respectively, of an epitaxial layer. The vertical scale
`in FIGS. 1, 3 and 5 is shown magnified for clarity. The
`epitaxial layer typically contains a low concentration of
`N-type impurities (e.g. from 5X10” to 5X1017 dopant
`atoms per cubic centimeter),,having been grown on a
`silicon crystal body 10 that is lightly bulk doped with
`P-type impurities. Buried layers 14, 15 and 16 having a
`sheet resistivity of about 20 ohms per square contain a
`heavy concentration of N-type impurities and lie at the
`interface between the body'and the epitaxial layer por—
`tions 11, 12 and 13, respectively.
`A network of isolation walls '17, 18, 19 and 20 sepa-
`rate and define the epitaxial layer portions 11, 12 and
`13. The isolation walls are formed by growing an oxide
`on the surface of the epitaxial layer, applying a sheet of
`photo resist thereto, exposing the photo resist sheet to
`an appropriate light pattern asdjefined by a light mask,
`selectively removing the photo resist material in areas
`over the location of the desired =walls, diffusing P—type
`dopant impurities through the ,oxide holes into the
`epitaxial layer and annealing the silicon to drive the
`impurities through the epitaxial layer. The resistivity of
`these walls is usually about 4 ohms per square. During
`the last phase of this heating step it is common practice
`to admit an oxidizing gas into the furnace so that a new
`oxide layer is formed over the walls. The silicon wafer
`is now ready for a second series of photo lithographic
`etch and diffusion steps that for example are designed
`to provide the transistor base region 21 and the two
`P—type resistor contact regions 22 and 23 in epitaxial
`portion 12.
`In a further series of steps, the oxide is again opened
`in other selected areas and a heavy concentration of
`N—type impurities is diffused into regions that become
`the emitter region 24, the collector contact region 25
`
`0003
`
`

`

`v 4,001,869
`
`4
`
`3
`of the transistor and an electrode region26 'of the ca—,
`pacitor. These regions have a sheet resistivity of about
`5 ohms per square.
`When the integrated circuit is to include an «ion im-
`planted resistor, the oxide is once again opened for
`. selectively exposing the epitaxial region 12 in an area
`between and including a portion of the resistor contact
`regions 22 and 23. Again an oxide15 grown forming a
`uniformly thick layer 27 of silicon oxide from between
`800 and 3000 angstroms thick over the freshly opened
`resistor area. A resistor body is then formed by direct-
`ing high energy P-typeions at the wafer..The ions pene—
`trate the relatively thin oxide layer 27 and become
`lodged in the underlying epitaxial layer forming a thin
`resistor region 30 that overlaps regions 22 and 23. The
`oxide elsewhere is much thicker and does not admit the
`
`described above. An overlayer 5 of glass is normally
`deposited over the completed integrated circuit by a
`vapor deposition step to provide physical protection
`and to insulate the integrated circuit from atmospheric
`contaminants.
`’
`-
`-
`*
`'
`An equivalent circuitdiagramofthe MOS capacitor
`structure of FIG. 11s shown1n FIG. 2. The capacitor 48
`has a series resistor 26 that represents the resistance of
`the doped region 26. The capacitor 49- between termi-
`10 nal 36 and the P—body, serving as the ground reference
`point for the integrated circuit, is the normally reverse
`biased p-n junction between the epitaxial region 1 1 and
`the surrounding P-type material. Capacitor 49 typically
`has acapacity of 0.07._picofarads persqure mil ( 1 mil =
`15 0.001 inch) at 5 volts reverse bias. Capacitor 48 typi-
`cally has a capacity of 0.055 picofarads per square mil,
`high energy ions to the wafer body. This ion implanta-
`for a dielectricoxide thickness of 4000 angstroms.
`A MOS capacitor of this invention is shown in FIG. 3,
`tion process for forming a resistor body through a thin
`oxide layer is sometimes preferred as being more pre-
`incorporated in an integrated circuit along with a typi—
`cise and providing a more reliable passivation for the
`20 cal ion implanted resistor and a typical NPN transistor,
`resistor, compared with another standard method
`each being formed in separate portions 61, 62 and 63,
`wherein the passivating oxide is grown over-the resistor
`respectively, of the epitaxial layer having N-type con—
`region after implantation.
`ductivity. Buried layers 64, 65 and 66 contain a heavy
`For the purpose of making the necessary ohmic
`concentration of N-type impurities and lie at the inter-
`contacts to portions of the integrated components,
`25 face between the body and the epitaxial, layer portions
`holes are again opened in the oxide and by a selective
`61, 62 and 63. A network of isolation walls 67, 68, 69
`deposition means, metal is deposited through the holes
`and 70 separate and define the above noted portions of
`overlapping the adjacent oxide to various extents. Thus
`the epitaxial layer.
`contacts 31, 32 and 33 are made to the transistor col-
`The transistor and the ion implanted resistor may be
`lector, base and emitter regions, respectively. Also
`‘30 formed by the conventional steps as'were described
`contacts 34 and 35 are made to P-type regions 22 and
`above for making the integrated circuit of FIG. 1. The
`23, respectively, for terminating the resistor 30. At the
`transistor and resistor, formed in epitaxial layer por—
`same time a contact 36 is made to the N—type electrode
`tions 63 and 62, respectively, as shown in FIG. 2 are
`region 26. Finally a second capacitor electrode 37 is
`identical to those in epitaxial layer portions 13 and 12,
`deposited over electrode 26 being spaced therefrom by
`35 respectively, as shown in FIG. 1; and the elementary
`a portion 40 of the oxide layer. The MOS capacitor
`parts of each are designated in FIG. 2 by numerals that
`formed in this manner employs the oxide layer portion
`are greater by 50 than the numerals of the correspond-
`40 as the dielectric layer and the capacitance is in-
`ing elementary parts in FIG. 1.
`versely proportioned to the thickness of this layer.
`As in the capacitor of FIG. 1, the MOS capacitor of
`This above general description of well known meth-
`40 FIG. 3 is formed during the formation of the transis—
`ods for forming specialized doped regions in a semicon-
`tor(s) andion implanted resistor(s) without requiring
`ductor is provided to illustrate how the steps in forming
`an additional process step. However, a large region 88
`an integrated circuit are normally made minimal in
`having a heavy concentration of P—type impurities oc-
`number and are designed to_ affect the structure of
`cupies most of the central portion of epitaxial layer 61
`several different elementary components .of the inte- 45 and is formed simultaneously with the isolation walls
`grated circuit simultaneously, and more particularly to
`67, 68, 69 and 70. The P-type dopants in the walls and
`illustrate and emphasize how the oxide on the epitaxial
`region 88 are most highly concentrated at the epitaxial
`surface,
`the concentration being diminished several
`surface is repeatedly grown and selectively removed in
`the normal course of making an integrated circuit.
`-
`order of magnitude at the interface between the epitax—
`By the above noted process, the oxide portion 40 is
`50 ial layer and the lightly P-doped body 50. The buried
`typically 4000 angstroms thick, and usuallyrepresents
`layer 64 has a high enough concentration of N-type
`an accumulation of oxide growth during the last phase
`dopants that this region retains an N-type conductivity
`of the emitter diffusion cycle plus the oxidation step for
`character and the P-type region 88 is effectively sur-
`growing the above noted resistor passivating layer 27.
`rounded in the epitaxial region 61 by N-type material ,
`55 as shown
`Furthermore, oxide grows at a higher rate over regions
`A small region 781s heavily doped with N-type1mpu-
`of the epitaxial layer such as the capacitor electrode
`region 26 that contain high concentrations of N-type
`rities during the diffusion step in which the transistor
`dopants, especially phosphorous. Also, the fast grown
`emitter 74 is formed. When the oxide is opened over
`oxide 40 over the N-type capacitor electrode 26 tends
`the resistor body region 80 it is simultaneously opened
`to be more porous, to contain more pin holes, and to
`60 over a major portion of the region 88 and when the
`have a lower voltage withstanding capability per unit
`uniformly thick oxide layer 77 of between 800—3000
`thickness than the oxide grown elsewhere. Thus the
`angstroms is grown over the resistor body region, a
`dielectric oxide in a conventional integrated MOS ca-
`similar layer 90 is simultaneously grown over region 88.
`pacitor is generally of inferior quality and is generally
`Furthermore, when P-type ions are implanted into re-
`P-type ions are im-
`65 gion 80 to form the resistor body,
`thicker than desired.
`.
`The profile of the oxide in oxide layer portions 41,
`planted through the oxide layer 90 forming a shallow
`surface region 76” that, nowhas a concentration of P—
`42, 43, 44, 45 and 46 is shown to vary as can be appre-
`ciated from the selective removal and growing steps as
`type impurities=that isgreater than that of the bulk of
`
`0004
`
`0004
`
`

`

`4,001,869
`1
`the surrounding region 88byan amount equal to the
`of theimplanted reSistorTherefore, both standard
`concentration of P—type impurities in the resistor body
`proceduresforforming a passivated iOn implanted
`.region 80, and having the same depth or thickness.It1s
`resistor require the format-ion of a thin high quality
`noted here, that1on implanted resistors contain a layer
`silicon oxide filmoverthe resistor body.
`,
`,
`.
`of implantedlons ranging from about 0 l
`to 0.8 mi-
`5 » AlSo, the quality of the oxide-1s required to be high
`crons thick. Such resistor bodies are distinguishable
`forresistor passivationand thus the special require-
`from diffused resistor bodies that contain a layer of
`ments of control and quality. of the resistor oxide are
`diffusedmm of about 2.0 to _4 microns thick
`compatiblewith those of the capacitor oxide Both are
`Simultaneous to the deposition of the metal contacts
`advantageouslygrown over P-type material1n this in-
`to the transistor and resistor, metal terminal 86 is 10. vention as has been explained.
`'
`‘
`formed in contact with region 78 and thus having
`An equivalent circuit diagram of the MOS capacitor
`ohmic contact to the N—type epitaxial region61, while
`structure of FIG. 318 shown1n FIG. 4. The capacitor 98
`,capacitor electrode 97 is formed over the region 76
`has a series resistor 88 and a series shorted diode 79.
`being spaced therefrom by the dielectric silicon dioxide
`The capacitor 99 betweenterminal 86 and the P body
`layer 90.. Metal terniinal 86 also contacts a portion of 15 50, body 50 serving as the integrated circuit ground
`.the P—type region 88, effectively shorting the diode
`point, represents the reverse biased junction capaci—
`formed at the junction of the region. 88 and surround-
`‘tance between epitaxial region 61 and the body 50.
`ing N-type epitaxial region 61.
`- .
`Another MOS capacitor of this invention is shown in
`In the MOS integrated capacitor1llustrated1n FIG. 3,
`.FIG. 5, included in an integrated circuit having in a
`the P-type surface region 76 provides a higher conduc- 20 .1 separate region a typical ion implanted resistor and a
`tivity capacitor electrode than would exist if only re—
`typical NPN transistor. These three components are
`gion 88 served as this electrode,and in principle the
`formed in epitaxial layer portions 111,112 and 113,
`implanted region advantageously contributes to reduc— respectively. The conventional transistor and resistor
`ing the effective series resistance and thus the ‘dissipa-
`are identical to those'1n FIG. 1. The elements of the
`tion factor of the capacitor However, as a. practical 25 transistor and. resistor in FIG. 5 are .designated by nu-
`matter, the implanted ion density here is usually onlya
`1mera‘lsthat are greater in each case by 7100 than the
`small fraction of the density of P-type dopantatoms
`numeral designation of the corresponding elements in
`already existing in region 88. Thus the addition of re-
`FIG. 1, The capacitor of FIG. 5 has a region 138 that is
`gion 76 is merely the by-product of the step saving
`of P-type conductivity andthat has been formed simul-
`simultaneous method employed here, wherein the 301taneously with the diffusion of the transistor base re-
`oxide layer 77 and 90 are grown over the resistor and
`gion 121. The capacitor dielectric oxide layer 140 is of
`capacitorregions prior‘to the resistor ion implantation
`the same thickness and character as the, oxide layer 127
`step, and the region 76 usually has no practical effect
`that overlies the resistor body 130, having been formed
`on the electrical characteristics of the .capacitor.
`simultaneously, as was described for the capacitor of
`. This capacitor dielectric oxide layer 90, however, is 35 FIG. 13. Likewise the P-type region 126.}vas formed by
`greatly superior to the counterpart oxide layer 40 of the
`ion implantation through oxide layer 140, simulta-
`conventional MOS capacitor of FIG. 1. Most signifi-
`neously with the implanting of the resistor .body 130.
`cantly it is thinner, and of better quality. MOS capaci—
`Thus the capacitor comprises electrode 138 (including
`tors of this invention have been made and measure—
`region 126) and electrode 137 having a silicon dioxide
`ments made thereon reveal that 0.11 picofarads per 40 dielectric layer 140 therebetween, and is capable of
`square mil is realized for an oxide thickness of 2000
`being terminated at contact 136 and electrode 137.
`angstroms while 0.13 picofarads per square mil results
`Ohmic contact is had to the N-type epitaxial region 1 l 1
`from a dielectric thickness of 1700 angstroms. Thinner
`by means of the metal contact 139 through region 128
`oxides than 800 angstroms are not desirable, this being
`that contains a heavy concentration of N-type impuri-
`about the minimum thickness for adequate passivation 45 ties.
`and protection of the resistor. Greater thicknesses than
`An equivalent circuit diagram of the MOS capacitor
`3000 angstroms inhibit through-ion-implantation and
`structure of FIG. 5 is shown in FIG. 6. The MOS capac-
`are of no practical consequence for use in the capacitor
`itor 148 is effectively in series with a resistor 138 that
`of this invention, since the conventional MOS capaci~
`represents the resistance of region 138 in FIG. 5. The
`tor is capable of almost as high a capacity per unit area 50 diode 107 and the capacitor 108 represent the p-n
`of integrated circuit real estate. The preferred thick-
`junction between the region 138 and the N-type epitax-
`nesses are from 1600 to 2200 angstroms.
`ial region 111. The capacitor 109 represents the p-n
`The capacitor dielectric oxide through which ’ion
`junction between the body 110 and the N-type epitaxial
`implanted resistor bodies are formed are more care-
`portion ,1 11. The capacitor 109 has the same character-
`fully formed than those for other purposes. The pene-155 istics as the equivalent capacitor 49 and 99 in FIGS. 2
`tration of ions forming the resistor body is inversely
`and 4, respectively. The capacitor 108 exhibitsacapac—
`related to the oxide thickness and thus it is common
`ity per square mil ofjunction area of about 0.055 pico-
`practice to carefully grow and control the oxide to a
`farads when the diode 107 is back biased at 10 volts.
`predetermined thin layer so that the implanted resistor
`Terminal 139 is provided for applying such a bias volt—
`body so produced has a predictable resistance. On the 60 age.
`other hand, when the resistor body is implanted in a
`The MOS capacitors of this invention are seen to
`bare silicon surface, the growth of the overlying oxide
`offer a capacity per unit area of integrated circuit real
`is again carefully controlled and of a thickness less than
`estate that maybe about two times that of a conven-
`3000 angstroms and preferably less than 2200 ang-
`tional integrated MOS capacitor, because the oxide
`stroms to prevent converting, to a significant depth, the 65 dielectric layer is thinner. The MOS capacitor of FIGS.
`implanted silicon surface and thereby significantly di-
`5 and 6 may be made to have an even higher effective
`minishing the thickness of the shallow implanted resis-
`capacitance by connecting electrode terminal 137 to
`tor body region which in turn increases the resistance
`terminal 189 and placing junction capacitor 108 in
`
`0005
`
`
`
`0005
`
`

`

`' 4,001,869
`
`parallel with MOS capacitor 148’ On the other hand,
`such a connection has thepotential disadvantages that
`the Correct exciting polarity must be Obseived to back
`bias diode 107 and the Capacitor 108'1s more voltage
`and temperature dependent. Also in comparison 'with ’
`the MOS capacitor of FIG.’ 5,‘the capacitor of FIG..6
`has a higher effective series resistance 138, sinCe' the
`base doped region 138 typically has a-sheet res'iStivity
`of about 135 ohms per square, as measured at the'sur-
`face of the epitaxial
`layer, while the more heavily
`doped region 88, in FIG 3, typically has a resistivity of
`*4 ohms per sqdare.
`What15 claimed'1s:
`,
`,
`,
`
`10
`
`1. In an integrated cir'Cuit including'at least one bipo-
`lar transistor, at leastLOne‘ resistor and a MOS type
`capacitor, said integrated circuit" being formedin a
`P-type silicon 'body having an epitaxial layer of N—‘type
`conductivity grown thereon; said transistor having been
`formed in a first portion of said epitaxial layer, said'
`resistor having been formed by'*ion implantation of
`P-type impurities in a second portion of said epitaxial
`layer at the surface thereof, a siliCon oxide film 'of 'a
`uniform thickness 'between 800 and 3000‘ angstroms
`having been grown over and covering said resistor, the
`improvement comprising said capacitor having one
`electrode consisting of a P-type region in a thirdpor-
`tion of said epitaxial layer and extending to the surface
`thereof, said oxide film of said uniform thickness hav-
`ing also been grown over said P-type electrode region,
`and anOther electrode of metal lying over and being
`spaced from said P-t-ype region by said film.
`2. The integrated circuit of claim 1 wherein said first,
`second and third portions of said epitaxial layer are
`defined therein- by Surrounding isolation walls of P—type
`conductivity, and'wherein said P-type electrode region
`Contains essentially the same concentration of P—type
`dopants' as contained in said ‘walls.
`
`IS
`
`20
`
`'25
`
`30
`
`35
`
`40
`
`8
`3. The integrated circuit of claim 2 wherein said
`capacitor additionally includes a buried layerofN-type
`conductivity being positibned at the interface of said
`second epitaxial layer portion and said body, and being"
`interposed between said P-type region and said p—type
`body fOr providing electrical isolation therebetween.
`4. The integrated circuit of claim 2 Wherein said
`metal electrode serves as a first terminal of said capaci-
`tor and Wherein said capacitOr additionally includes a
`secOnd metal capacitor terminal making Ohmic contact
`‘to both said P-type electrode regions and the adjacent
`of said N-type third portionOf said epitaxial layer.
`5. The integrated circuit of Claim 1 wherein said at
`least one transistor has a standard NPN structure, said‘
`first portion serving as the COllector thereof, said P—type
`regiOn in said one epitaxialportion having essentially
`the same concentration of P~type dopants as the base
`region of said NPN transistor.
`'
`6‘. The integrated circuit of claim 1 wherein said
`uniform silicon oxide film15 from 1600 angstroms to
`2200 angstroms thick.
`»
`7. The integrated c1rcuit '-of claim 1 wherein said
`P-type region has a portion thereof extending laterally
`beyond said oxide film Of said uniform thickness grown
`over said P-type region, said P-type= region containing a
`cohCentratio'n of'P-type impurities in a surface'region
`thereof under said oxide film of uniform thickness that
`is greater than the concentration-1 of P-type impurities in
`said laterally extending portion of said P-type region by
`an amount? that 'is equal to the concentration of said
`P-type impurities in said ion implanted resistOr, said
`surface region having the same thickness as said P-type
`resistor.
`8. The integrated circuit of claim 7 wherein said
`thickness of said shallow P-type region of said capaci-
`.
`- *
`*
`* \* alt
`tor is from 0.1 to 0.8 microns.
`
`45‘
`
`50 f
`
`55
`
`‘60 .
`
`'65
`
`0006
`
`0006
`
`