A CMOS-BASED HIXED ANALOG-LOGIC STANDARD CELL PRODUCT FAMILY
`
`M. A. Massetti, E. D. Johnson, D. L. Mariano,
`L. D. Smith, and D. R. Willmott
`IBM General,Technology Division
`Essex Junction, VT
`05452
`
`M. R. Gruver, R. L. Hedman, B. R. Owens, and M. J. Russell
`IBM System Products Division
`Rochester, MN
`55901
`
`epitaxial process is required to insure that the
`n-well electrical characteristics are identical
`to the base CMOS process. The second step is a
`30 ohmsjo P implant to form the back plate of a
`voltage
`and
`temperature
`insensitive MOS
`capacitor and the NPN collector contact. The
`last mask/implant step is a 900 ohmsjo B implant
`to form the resistor and the NPN base region.
`The addition of these steps to the CMOS tech(cid:173)
`nology provides the analog designer with a full
`slate of precision analog devices. Device cross
`sections are illustrated in Fig. 1. Table 1
`contains a summary of key analog and logic de(cid:173)
`vice parameters.
`
`N-FET
`
`P-FET
`
`ABSTRACT
`
`integration of mixed analog-logic
`Successful
`standard cells has been demonstrated
`in a
`1.0-pm CMOS-based
`technology. Considerations
`for analog cell area, power distribution, noise
`immunity, circuit library design, and product
`test are described.
`
`INTRODUCTION
`
`An experimental 40K equivalent gate CMOS-based
`analog-logic standard cell (ASC) chip has been
`developed to provide a chip designer the capa(cid:173)
`bility to integrate structured analog functions
`with logic circuits without sacrificing per(cid:173)
`formance, density, multiple part number capa(cid:173)
`bility, or testability. All the attributes of
`the 40K CMOS standard cell (CSC) chip have been
`maintained while extending the product capabil(cid:173)
`ity to incorporate analog circuitry [1].
`
`This paper focuses on a description of the chip
`characteristics and design considerations. An
`overview of the CMOS-based processes is provided
`to aid in understanding the key analog design
`requirements. An overview of the design system
`and test methodology is provided for complete(cid:173)
`ness.
`
`TECHNOLOGY
`
`P+
`
`The base CMOS process is a 5V n-well technology
`with 1-pm minimum image, a single polysilicon
`layer and
`two
`levels of metal. The merged
`bipolar-CMOS process available for the ASC pro(cid:173)
`ducts has evolved from the base CMOS process.
`N-channel and p-channel devices have identical
`specifications in the
`two processes. Bipolar
`transistors, resistors, and MOS capacitors have
`been developed with minimal process adders
`to
`provide devices
`for high performance analog
`circuits.
`
`The bipolar-CMOS process incorporates three ad(cid:173)
`ditional mask steps and implants beyond the base
`process. The first mask/implant step is an Sb
`implant for the n+ buried layer (NPN subcollec(cid:173)
`tor). The n+
`layer also provides additional
`latchup immunity as it is placed under all n(cid:173)
`wells. A revised n-well implant, drive-in, and
`
`NPN
`
`MOSCAP
`
`P+
`
`Figure 1. Bipolar-CMOS device cross sections
`
`24.1.1
`IEEE 1988 CUSTOM INTEGRATED CIRCUITS CONFERENCE
`
`CH2584-1/88/0000-0142 $1.00 © 1988 IEEE
`
`0001
`
`AMD EX1018
`U.S. Patent No. 6,239,614
`
`

`

`Table 1: Bipolar-CMOS Device Parameters
`
`FET:
`Vtn
`Vtp
`Vtn match @ S].lm
`Delta Vtn @ S].lm
`
`NPN:
`Ft
`Vbe matching
`Hfe
`Delta Hfe
`
`Resistors:
`Resistivity
`Tolerance @15].lm
`Matching @15].lm
`
`Capacitors:
`Capacitance
`Matching @10pF
`
`. 94
`-.14
`15
`60
`
`3.2
`1
`90
`so
`
`895
`8
`1.5
`
`1.4
`
`v
`v
`mV
`mV
`
`GHz
`mV
`
`+;-
`
`ohmsjo
`%
`%
`
`fF/].lm~
`%
`
`CHIP HIAGE
`
`Figure 2. ASC 40K chip Image
`
`The ASC 40K chip image is 9. 44mm x 9. 35mm and
`is packaged in a ceramic pin grid array package
`with 200 pins, 180 are used for digital or ana(cid:173)
`log
`input/output CI/0) signals. The ASC chip
`image allows an analog and logic mix whereas the
`CSC 40K chip image is strictly for logic pro(cid:173)
`ducts. There are 591 contacts between the ASC
`chip image and the ceramic package in the pe(cid:173)
`ripheral area, the two vertical busses, and in
`the outer two circuit bays of the chip. The pe(cid:173)
`ripheral area consists of power and I/0. Digital
`SV and ground connections to the internal books
`are located on the vertical columns. Separate
`analog
`SV
`and ground
`connections
`for
`the
`internal books are located in the outer two bays
`[2]. Figure 2 is a schematic of the chip image.
`Figure 3 is a schematic of the ceramic package
`structure. Table 2 identifies chip pad and pin
`count.
`
`Table 2: ASC 40K Chip Pad/Pin Count
`
`ASC 40K
`Chip Image
`
`Chip/Package
`Pads
`
`Package
`Pins
`
`Gnd-analog
`Gnd-logic
`Gnd-switchable
`
`Vdd-analog
`Vdd-logic
`Vdd-switchable
`
`Signal I/0
`
`TOTAL
`
`120
`so
`44
`
`120
`52
`25
`
`180
`
`591
`
`2
`8
`
`2
`4
`
`180
`
`196
`
`Gnd
`
`Logic
`Gnd
`
`Gnd
`
`Logic
`vdd
`
`Logic
`vdd
`
`Gnd
`
`Logic
`Gnd
`
`Gnd
`
`Figure 3. ASC 40K PGA package
`
`The internal chip area is organized into 70 rows
`of 64].lm high by 17.6].lm wide digital cells. The
`analog cells are six digital cells in width,
`64].lm by 105.6].lm. Each row contains 432 digital
`cells. These rows are organized by double rows
`in the vertical direction.
`In the horizontal
`direction
`these
`rows are divided into three
`
`24.1.2
`
`0002
`
`

`

`bays. Initially, the entire chip is set up for
`digital cells. Analog cell rows are placed in
`one or more of the four corners of the chip and
`replace the digital cells originally there. The
`middle bay is always reserved for digital cells.
`
`The chip image can be viewed as a wiring grid
`of horizontal first-metal channels on a 3. 2]lm
`pitch and vertical second-metal channels on a
`4.4)lm pitch. Global analog wiring is permitted
`only on first- or second- metal wiring. Analog
`wiring is either single-pitch or double-pitch.
`First-metal is on a 3.2)lm pitch or 6.4)lm pitch,
`and second-metal is on a 4.4]lm or a 8.8)lm pitch.
`Double-pitch wires allow for de current to flow
`for analog. The use of single-pitch or double(cid:173)
`pitch is determined for each analog circuit.
`
`Global wiring where analog and logic signals run
`adjacent to one another may cause cross talk
`problems. These problems are minimized by main(cid:173)
`taining sufficient distance between sensitive
`and noisy circuitry to reduce coupled capacitive
`noise. Analog and logic wires are separated by
`at least one clear wiring channel. Additional
`noise
`immunity
`is achieved with first-metal
`wiring bays dedicated to quiet wires [3,4].
`
`The internal analog power busses connect chip
`power to the package and other distributes power
`to the analog circuits. The analog area contains
`potential connection points between the chip and
`package power distribution networks. These are
`selectively connected by vias through the insu(cid:173)
`lation layer on the borders of the analog sec(cid:173)
`tion. This technique allows a common PGA package
`and wafer probe card to be used for products
`with varying analog content. The power bus cov(cid:173)
`ers the entire analog area t·-, supply voltage to
`the analog circuits. The result is a power grid
`of vertical second-metal and horizontal first(cid:173)
`metal power busses. All analog circuits have
`standardized coordinates to pick up
`the power
`and adhere to specific maximum current sinking
`specifications.
`
`The peripheral I/Os are also separated into an(cid:173)
`alog and logic sections. Initially, the entire
`I/0 area is set up for logic. Once analog books,
`internal or I/0, are introduced, the adjacent
`Ijq areas are dedicated to analog by splitting
`the peripheral power busses. Only analog books
`or digital receivers can be placed in this re(cid:173)
`gion.
`Separation of the power busses and the
`analog books reduces simultaneous switching and
`other noise concerns. Digital power pins on the
`chip and package are also redefined to analog
`power as analog circuits are placed on the chip.
`
`ANALOG POWER BUS STRUCTURE
`
`into. One of the determinants of analog cell
`size is the analog power bus analysis described
`below.
`
`A grid power bus structure in which a single
`analog book is supplied from many directions was
`selected over a tree structure. Figure 2 shows
`the analog power bus complete with the bump
`joint chip pads for analog SV and ground. Figure
`4 shows the unit analog cell with analog power
`supplied to the book with second-level metal.
`
`4 Analog Cells
`
`24 Logic Cells
`
`LSTS
`
`Figure 4. Analog and logic unit cells
`
`Using metal resistivities and dimensions of the
`unit cell, a resistor network analyzed in a
`statistical electrical analysis package to sim(cid:173)
`ulate the performance of the analog power bus.
`Figure Sa shows power supply voltage drop if 1
`rnA of current is drawn from each analog book in
`a
`fully populated analog terrah. Figure Sb
`shows the voltage drop to a single analog book
`drawing 1 rnA on the edge of the analog terrain.
`The equivalent series resistance of the power
`supply to each analog book location can be ana(cid:173)
`lyzed in this manner. Voltage drop and series
`resistance for tree and grid power bus struc(cid:173)
`tures are compared in Table 3. The performance
`of the analog power bus structure is well inside
`the specification limits known to cause chips
`to malfunction [5].
`
`Table 3: Power Bus Comparison
`
`DC Voltage Drop! Series Resistance!
`
`Tree!
`Grid!
`
`149 mV
`36 mV
`
`5.0 ohms
`0.8 ohms
`
`The analog power bus structure was designed to
`satisfy two criteria: voltage drop and equiv(cid:173)
`alent series resistance. Minimizing voltage drop
`maximizes the dynamic range of the analog books.
`Minimizing equivalent series resistance reduces
`the power supply rejection ratio that analog
`books must have. The power bus structure pro(cid:173)
`vides a framework that all analog books must fit
`
`the
`Critical noise concerns associated with
`analog-logic integration are power supply cou(cid:173)
`pling, cross talk, substrate fluctuations, and
`stray carriers [6].
`An n-well structure has
`been designed to reduce the impact of noise in
`three ways: protect analog books
`from stray
`carriers, substrate
`fluctuations,
`and power
`supply noise coupling.
`
`24.1.3
`
`0003
`
`

`

`mV
`
`48
`
`24
`
`Analog Rows
`
`a) DC Voltage Drop
`
`mV
`
`0.8
`
`0.4
`
`18
`
`18
`
`Figure 6. Analog power bus n-well structure
`
`logic, ROS, and SRAM functions.
`150 different
`Approximately 100 different analog circuits are
`available for use on ASC chips. The major func(cid:173)
`tion classifications in the analog library are
`shown in Table 4. Analog circuits are redesigned
`when performance requirements are not met with
`the existing library.
`
`Analog Rows
`
`Analog Columns
`
`Table 4: Analog Library Function Types
`
`Buffers
`ADCs
`Comparators
`DACs
`Detectors
`Op Amps
`Filters
`Linear Amps
`Resistor Arrays
`Variable Goin Amps (VGA)
`Capacitor Arrays
`VCOs
`Switch Arrays
`References
`Analog I/0
`Multiplexors
`L--------------------------------------------~
`
`I
`I
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`b) Equivalent Resistance
`
`Figure 5. Analog power bus analysis
`
`Figure 6 shows a section of the analog area. The
`n-well is connected to analog 5V forming an ef(cid:173)
`fective carrier b~rrier to free holes and is an
`effective collector of electrons. N-well straps
`partition individual analog books to block car(cid:173)
`riers
`from
`those books
`that are sensitive to
`carriers or those that are known to emit carri(cid:173)
`ers. Analog substrate contacts are necessary
`because of latchup concerns. The n-well struc(cid:173)
`ture provides a safe area for substrate con(cid:173)
`tacts. These contacts are avoided
`in analog
`books to reduce latchup sensitivity and to re(cid:173)
`duce body effect noise.
`
`The n-well structure also provides an effective
`decoupling capacitor from analog 5V to ground.
`Both the bottom surface of the n-well and the
`sidewalls contribute capacitance of 15 pF for
`each design row. The capacitance is distributed
`very close to analog books and is in the most
`effective position possible.
`
`ANALOG CIRCUIT LIBRARY
`
`The size of the unit analog cell was determined
`by considering the average size of analog books,
`the number of wiring channels required to access
`the unit cell, compatibility with the existing
`logic
`image, and the results of the power bus
`analysis. Each analog cell contains 8 analog
`service terminals
`(ASTs). ASTs are located on
`every other second-level metal wiring channel
`on the cell boundary adjacent to the first-level
`metal wiring bay. Typically, analog functional
`and performance requirements (matching, output
`impedance, etc.) are satisfied with larger de(cid:173)
`vices than logic circuits. The cell width of
`105.6vm was established by taking into account
`the number and size of devices
`required by
`primitive analog functions and the need to match
`the granularity of the digital books.
`
`ASC products are assembled from analog and logic
`circuit
`libraries [7]. Circuit compatibility
`with
`the chip design system
`is checked and
`guaranteed. The logic library contains more than
`
`Analog books access power by interconnections
`to second-level metal on the edge of the cells.
`Logic books access power from first-level metal
`power busses within the cell. First-level metal
`
`24.1.4
`
`0004
`
`

`

`analog power redistribution was placed in the
`wiring bays to maximize the room available for
`circuit design in the cell. The number of wiring
`channels is reduced but they satisfy the lower
`analog book interconnect requirements. Figure 4
`compares the analog and logic cells.
`
`In the 40K equivalent gate ASC chip, the gate
`count was established as if the chip were en(cid:173)
`tirely logic.
`
`DESIGN SYSTEM AND TEST
`
`This section gives a very brief overview of the
`design system, which is an extension to the esc
`system. The analog books are designed within a
`self-contained set of design tools. Once com(cid:173)
`plete,
`the books are placed into the database
`with the logic books. Book net lists are entered
`by the chip designer using a standardized lan(cid:173)
`guage. Design verification consists of analog
`and logic simulation and timing verification for
`the logic. Physical design, 0lacement, and wir(cid:173)
`ing, are done after successful simulation. De(cid:173)
`sign rules are
`in place to
`insure that the
`design is correct by construction. Once com(cid:173)
`plete,
`the artwork file is submitted to manu(cid:173)
`facturing.
`
`ASC product test is done in two passes: digital
`and analog. Test pattern generation for
`the
`digital circuits is predicated on compliance
`with the LSSD discipline [ 8] . Additional re(cid:173)
`strictions have been established for ASC chip
`design to allow for very high coverage of logic
`faults. In this manner, the integrity of logic
`testing is equal to the CSC products. Analog
`test patterns are generated manually and provide
`functional test coverage for
`the analog cir(cid:173)
`cuits.
`
`sum!ARY
`
`equivalent gate
`lOK
`and
`40K
`Experimental
`C~IOS-based analog-logic standard cell chips have
`been developed. The bipolar-CMOS process,
`the
`chip
`image, analog power distribution, analog
`circuits, and the design system were described.
`All elements of the successful CSC chips were
`maintained and extended to include structured
`analog circuits for a variety of mixed analog(cid:173)
`logic products. Figure 7 is an example of a
`completed 40K chip. Figure 8 is an example of a
`completed lOK chip.
`
`Figure 7. Experimental ASC 40K chip
`
`ACKNOWLEDGEMENTS
`
`The authors would like to thank the members of
`the IBM System Product Division and the General
`Technology Division for their efforts in devel(cid:173)
`oping the ASC product capability.
`
`REFERENCES
`
`1. A. W. Aldridge, R. F. Keil, J. H. Panner,
`G. D. Pittman, and D. R.
`Thomas, "A 40K
`Equivalent Gate CMOS Standard Cell Chip,"
`
`Figure 8. Experimental ASC 10K chip
`
`24.i .5
`
`0005
`
`

`

`IEEE 1987 Custom Integrated Circuits Con(cid:173)
`ference, May 5-8, 1987.
`
`cuits," IEEE 1987 Custom Integrated Circuits
`Conference, May 5-8, 1987.
`
`2.
`
`Seidel,
`D.
`Analog/Digital
`May 15, 1986.
`
`"Interactive Methods Ease
`Design," Computer Design,
`
`3. T. Pletersek, J. Trontelj, L. Trontelj, I.
`Jones, G. Shenton, Y. Sun, "Analog LSI De(cid:173)
`sign with CMOS Standard Cells,"
`IEEE 1985
`Custom Integrated Circuits Conference, May
`20-23, 1985.
`
`4. C. D. Kimble, A. E. Dunlop, G. F. Gross, V.
`L. Hein, M. Y. Luong, K. J. Stern, and E.'
`J. Swanson, "Autorouted Analog VLSI," IEEE
`1985 Custom Integrated Circuits Conference,
`May 20-23, 1985.
`
`5.
`
`J. A. Olmstead, S. Vulih,
`in Mixed Analog-Digital
`
`"Noise Problems
`Integrated Cir-
`
`6.
`
`"The Design of High(cid:173)
`E. A. Vittoz,
`Performance Analog Circuits on Digital CMOS
`Chips,"
`IEEE Journal of Solid-State Cir(cid:173)
`cuits, June 1985.
`
`7. C. A. Laber, C. F. Rahim, S. F. Dreyer, G.
`T. Uehara, P. T. Kwok, P. R. Gray, "Design
`Considerations for a High-Performance 3-)lm
`CMOS Analog Standard-Cell Library"
`IEEE
`Journal of Solid-State Circuits, April 1987.
`
`8. E. B. Eichelberger, T. W. Williams, "A Logic
`Design Structure
`for LSI Testability,"
`ACM/IEEE Fourteenth DA Conference Pro(cid:173)
`ceedings, 1977.
`
`24.1.6
`
`0006
`
`