578
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. SCAMS, N0. 5. OCTOBER 1983
`
`people involved made a significant contributions to this pro}
`ect; We Would like to thank Z. Fazarinc and R. Eschenbach
`of HP Labs and J. Homer and D. Hunsinger at the Santa Clara
`Division for their enthusiastic and continuous support of
`this project. We also benefited from the excellent help and
`cooperation of a team of people in IC R&D and CAA design,
`namely,
`1. Pesic, J. DeGrenier, K. Kikuta, K. letter, and E.
`Burke. A. Wang,
`J. Pecenco, and A. Motamedi were respon—
`sible for the IC process, and W. Scott and J. Struss for the pro-
`duction. H. Hofrnann, K. Purdue, R. Eaton, and R. Wan wrote
`all the PLM tools software, which is such an important part of
`this short turnaround design cycle. Finally, we deeply appre-
`ciate the efforts of many others involved in the mask making,
`processing, production, testing, and packaging phases of this
`project.
`
`REFERENCES
`
`[1]
`
`ll. Eichelbcrger and T. W. Williams, "A logic design structure
`13.
`for LSI tastabiljty,” in Proc‘. 14?}! Design Atttomtr'on Confi, New
`Orleans LA, June 19W, pp. 462468.
`[2] F. F. Tsui, “ln—situ testability design,” Proc. IEEE, vol 70, pp.
`59u81 Jan. 1932.
`[3] W. Twadel], “Uncotmnitted IC logic,“ EDN, PP. 89—98. Apr. 5,
`1980.
`
`[4]
`
`J. Birkncr. “Reduce random-logic complexity,” Electron Design.
`pp. 98—105, Aug. 16, 19m
`[5] W. R.
`lvcrsen. “3,000—gatc array has 600-135 delay," Electronics,
`pp. it's-176, Feb. 10. 1983.
`[6] D. Bursky, “Chips get denser. faster, as software shortens turn-
`around,” Electron. Design, pp. 91-102, Dec. 9, 1982.
`{7] 2. E. Skokan, “Emitter function logic,” IEEEJ Solid—Stare Cir-
`cuit‘s, vol. 308, Oct. 1913.
`[3] K. M. Ferguson and L. R. Dickstein, “Time synthesizer generates
`precise pulse width .
`.
`. ," HPI, Aug, 1978.
`[9] B. W. Wong and W._ D. Jackson, “A high—performance bipolar LSI
`counter chip using EFL and Ill. circuits."HP .1, Jan. 1979.
`
`
`
`Zdenek E. Skokan received his education in
`Prague, Czechoslovakia.
`From 1963 to 1968 he worked in the Govern-
`ment Computer Research Institute, Prague. His
`experience there included high-speed instrumen—
`tation design and circuitry for thin-film memo-
`ries. Since 1969 he has worked as a member of
`the Technical Staff at Hewlett-Packard Labora-
`tories, Palo Alto, CA. His main area of interest
`is in high-speed bipolar integrated circuits for
`instrumentation and computation. He holds a
`number of patents in the area of logic circuit design. In his spare time,
`he does R&D wa rlr for electric automobiles as a founder and President
`of Electric Vehicles, Inc.
`
`A 20K—Gate CIVIOS Gate Array
`
`TAKASHI SAIGO, HARUYUKI TACO, MASAZUMI SHIOCHI, TAMOTSU HIWATASHI, KlYOSlll NIWA,
`TAKAHIKO MORIYA
`SHOHEI SHIMA. AND
`
`Abstract-LComhining an advanced 2 um CMOS technology with a
`newly developed triple level metallization technology, a high-perfor-
`mance 20K—gate CMOS gate array has been developed. An advantage
`of triple level metallization for area saving in a large scale gate array was
`evaluated by a computer simulation. The typical gate delay is [.5 us
`with fan-out 3, and 3 mm metal interconnect length. Asa test vehicle
`for verifying the hightperl‘ormance gate array, a 32 X 32 bit parallel
`multiplier has been successfully designed and fabricated. Cell utiliza-
`tion is about 65 percent. Typical multiplying time is 120 ns at a 5 MHz
`clock rate with a power dissipation of 400 mW.
`
`I.
`
`INTRODUCTION
`
`7
`
`ATE arrays have been widely used because of their short
`turnaround time nature and costlperformance advantage.
`The CMOS approach especially has become a dominant tech-
`nology trend due to several advantages such as low~power
`dissipation, high density and high Speed, as also reported in
`memory device papers [l]-[31.
`'
`
`Manuscript received April 19, 1983; revised June 2‘7, 1983.
`The authors are with VLSI Application Department, Toshiba R and D
`Center, Toshiba Corporation, KawaSaki, Japan.
`
`6K and SK-gate CMOS gate arrays with double level metalliza-
`tion have been developed and reported [4]—{6]. However,
`demand for larger scale gate arrays is still increasing, especially
`in applications to large computers.
`Combining an advanced CMOS technology with a newly
`developed triple level metallization technology, a high-perfor-
`mance ZOK-gate CMOS gate array has been dechOped. The
`first part of- this paper describes advantages of triple level
`metallizaiion for large scale gate arrays. Then, the fabrication
`process is discussed. The basic cell, lfO cell, and chip configura-
`tion as well as the basic performance of the array are discussed
`next, and finally the circuits, the design, and the performance
`of a 32 X 32 bit parallel multiplier as a test vehicle of a 20K—
`gate gate array are described.
`
`it. ADVANTAGE or TRIPLE LEVEL ME'I'ALLIZA'I'ION
`
`In the conventional, double level metallization CMOS gate
`arrays, the second metal layer is usually used for the periphery
`of the chip for power buses.
`[t
`is widely known that the
`power buses occupy a large area on a large scale gate array
`
`01318-920083}WHO-057850190 © 1983 IEEE
`
`0001
`
`AMD EX1016
`
`US. Patent No. 6,239,614
`
`0001
`
`AMD EX1016
`U.S. Patent No. 6,239,614
`
`

`

`SAIGO er 0L: 20K-GATE CMDS ARRAY
`
`579
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`Area
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`
`Fig. 3. A part of equivalent circuit including an inverter.
`
`lines run vertically
`the first metal
`reported gate array [4],
`{along the channel) and the second metal lines run horizontally,
`on the basic cell array. The first metal layer is used both for
`power buses on the array and for signal
`lines. The second
`metal layer is used for signal lines on the array and for power
`buses on the U0 area. Then, we also considered the case
`where the third metal
`lines used for the power buses run
`horizontally on the array (perpendicular to the first metal
`lines used for power buses) and along the periphery on the IKO
`area.
`In this case, connecting the third to the first metal lines
`on the array is desirable, in order to prevent voltage fluctuation
`along the power buses. Fig. 2 shows the equivalent circuit of
`the power buses for the double level metallization. RP and LP
`are resistance and inductance along the inner leads of the pack-
`age, respectively. Fig. 3 shows a part of the circuit including
`an equivalent large inverter composed of twenty pairs of p-
`and n-cbannel transistors in the basic cell, each connected in
`parallel. The inverter is located in the center of the circuit.
`The bold solid lines correspond to the third metal power
`buses.
`Fig. 4 shows the results of simulation for the circuit
`
`0002
`
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`
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`Number of adios
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`
`10K 20K 30K
`
`Fig. 1. Calculated ratio of area required for power buses to the total
`chip area.
`
`chip. By employing the third metal layer as additional power
`buses, this problem can be eased drastically. Fig. 1 shows the
`calculated ratios of the area required for power buses to the
`total chip area for double and triple level metallizations.
`The hatched area is for power buses. The rest of the chip
`area is available for signal lines. The calculation is performed
`as follows.
`
`The chip area is the sum of the core area and the power bus
`area which is surrounding the core area.
`When the number of gates is given, the core area and power
`bus area are calculated as follows.
`
`1) CoreAr-ca Calculation:
`The basic cell size and wiring channel width are fixed and are
`90 X 20.1 and 100 um, respectively.
`The core area is calculated for the shape which is chosen to
`be as Square as possible.
`The core area does not depend on whether the metallizaiion
`is double or triple.
`2) Power Bus Area Calculation:
`The current density limit is 105 Mcmz.
`The thickness of each level metal line is 1 pm.
`The each basic cell operates at a cycle clock of 25 MHz,
`and power dissipation is 250 ,uWibasic cell [VDD = 5 V].
`Every metal
`line on the core area is available for a signal
`line and power bus.
`The first metal
`line is also available for a signal line and
`power bus.
`The power bus area is calculated for both double level and
`triple level metallizations under
`the conditions mentioned
`above.
`.
`
`~
`
`Then, the total chip area and the ratio are obtained. At the
`ZDK-gate level, about 60 percent of the chip area is required
`for power buses in the double level metallization. However,
`in the triple level metallization, only 35 percent of the chip
`area is required for power buses. The result clearly shows
`that
`triple level metallization is useful for large scale gate
`arrays. Obviously,
`there exist many other advantages of
`triple level metallization For CMOS gate arrays as discussed
`in [7].
`As the first application of the triple level metallizaiion to
`CMOS gate arrays, we considered a case of the third metal
`layer being used only for V313 and VSS lines.
`In the earlier
`
`0002
`
`

`

`580
`
`[EEE JOURNAL OF SOLID-STATE CIRCUITS. VOL
`
`. SC—lS, NO. 5, OCTOBER 1933
`
`Substrate
`N-type SIJOfl -cm
`Gate Dildo Thickness
`4005
`I 5pm
`Ettmm Channel Length
`1 08V
`Tmsrmm varoqos
`Contact Hot: Sue
`2pm a
`lat Al Line I Pitch
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`“we?”
`VIoZ Size
`7pms5J-Im
`3rd AI Linefspaol
`
`I1yml5fim
`
`Fig. 6. Key process parameters and design rules.
`
`RIE [CF‘ -H.'.'
`
`U-
`
`s:
`m M or H...
`
`
`
`Voltage[V]
`
`
`
`Voltage[Vl
`
`
`
`Voltage[Vl
`
`VoltageW}
`
`45
`05
`
`05
`0
`
`042-O01‘.”0!
`
`Time
`
`lnsl
`
`Fig. 4. Voltage fluctuations along V131) and V33 lines in double level
`metallization.
`
`
`
`Voltoqe[W
`
`on0menor
`
`
`
`Voltage[V]
`
`o
`
`a:_<
`
`s‘at
`
`20
`Time
`Ins)
`
`40
`
`Fig. 5. Voltage fluctuations along V013 and VSS lines in triple level
`metallization.
`
`in the double level metallization. Values of resistances,
`
`capacitances, and inductances are estimated from the structure
`of the ZOK-gate gate array described in Section IV. The upper
`waveforms show the input and output signals. The other
`waveforms show voltage fluctuations of the VDD and V55 lines
`at
`the points shown in Figs. 2 and 3.
`In the double level
`metallization,
`the fluctuation of the power buses is rather
`serious, as shown in Fig. 4. However, the fluctuation of the
`power buses is reasonably suppressed by employing triple level
`metallization, as shown in Fig. 5. From these results it is clear
`that the triple level metallization is effective in suppressing the
`fluctuation of power buses, when many basic cells operate
`simultaneously.
`
`Ill. FABRICATION PROCESS
`A. Master Process
`
`The device structure is a conventional p-wel] with single
`level Si-gate, similar to that of 64K CMOS RAM [2]. Fig. 6
`shows some of the key process parameters and design rules.
`For
`realizing the 2 pm design rules, dry etching and ion
`implantation processes are fully utilized. The master process
`
`0003
`
`RHEISl Removal
`
`l-Wa-l
`
`and Etch
`
`{5)
`
`(c)
`
`M 5‘0
`wt. .4
`s: z
`gRIEic,r.+H,i
`SID:
`5.
`“Mr “N: I
`M
`I
`(d) My. A! Metalllzutrm
`Fig. 7. Flow chart of “round etch."
`
`is almost identical to the earlier reported 6K-gate gate array
`process [4].
`
`B. Personalization Process
`
`The personalization process is constructed by triple level
`metallization and 2 pm design rules, different from the 6K-
`gate gate array [4] . For introducing these tight design rules
`as shown in Fig. 6, reactive ion etching (RIB) technology is
`quite essential. Consequently, steep pattern edge steps pro-
`duced during the etching process tend to cause several problems.
`Two major problems are discontinuity and pattern deteriora-
`tion of upper level Al interconnecting lines, and poor Al step
`coverage at hole edges. which causes open failuc in intercom
`necting lines. Two new processes have been developed to
`overcome these difficulties. The first one is a rounding tech-
`nique of hole edges, which has been already described briefly
`[8]. Fig. 7 shows the flow chart of the rounding edge ofholes.
`in the first step, the hole is anisotropieally etched using CF},
`and H2.
`in step (c) after the resist removal, RlEin the mixture
`of C3175 and H3 bevels the edge of the holes. The step edge
`of the holes is out roundly without any change in the bottom
`size. This technology is applied to contact holes and via 1
`holes (between the first and second metal layers) fermations.
`The second is the low—temperature planarization technique
`using plasma SiN [9].
`Fig. 8 shows the flowchart of the
`planarization. This technology utilizes the phenomenon that
`the silicon nitride etch rate at the groove bottom is suppressed
`in the CF4 and H2 gas environment.
`In step (c) after depOsL
`tion of SiOz and SiN films, the SiN film is etched so as to fill
`the SiO2 grooves with the SEN. The following RIE process is
`carried out with the same etch rate for SEN and 3102 films.
`Then,
`the SiO; surface is planarized as shown in ((1). This
`
`0003
`
`

`

`SAIGO et at: ZOE-GATE CMOS ARRAY
`
`581
`
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`
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`
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`(c) W lst Step Etch Back by RIE
`
`2nd Slap Etch Back by RIE Depositing
`
`5502
`
`Fig. 8. Flowchart of planartzation.
`
`
`
`435 Born: Cell/Cot
`lBO [/0 Pads
`20 Trucks Between Each Col.
`Chip Size 9.99 x 9 99 mm'
`
`
`
`EAL
`
`Fig. 9. Microphotograph of triple level metallization.
`
`planarization technique is applied to two interlayer SiOz
`films.
`Fig. 9 is a SEM microphotograph of the triple level
`metallization. A 2 pm minimum linewidth and good step
`coverage of every metal layer are realized.
`
`1V. ARRAY OF BASIC CELL AND HO CELL
`A. Basic Cell
`
`The basic cell consists of two pairs of n- and p-channel
`transistors. One pair has a polygate in common and the other
`has separate gates [4]. The basic cell size is 90 X 20.1 pm.
`The channel width of the transistors is 24 um each. The
`effective channel length is 1.5 1.1m each. The basic cell size
`is minimized by a tight Al pitch and fine alignment tolerance.
`
`3. 1/0 Cell
`
`Fig. 10. Chip configuration of ZUK-gate gate array.
`
`C. Chip Configuration
`
`Fig. 10 shows the chip configuration of the ZOK—gate array.
`There are 46 columns on the chip and 435 basic cells are in
`each column.
`In total, 20 010 basic cells are laid out on the
`chip. Between each column, there are 20 tracks of the first
`A] interconnecting lines with a 5 pm pitch. The first A] inter-
`connecting lines run vertically, and the second Al
`intercon-
`necting lines run horizontally with 6.7 rim pitch. The third
`Al interconnecting lines, which are used for power buses, run
`horizontally with a 47 basic cell pitch. The third Al lines are
`connected indirectly to the first Al lines used for power buses,
`through the second Al
`lines. Location of both via 2 holes
`(between the second and third metal layers) and the third Al
`interconnecting line pattern are fixed, therefore, four layers
`of masks (contact hole, first metal, via 1, and second metal)
`are used for personalization.
`There are 180 U0 cells on the periphery of the chip. each
`of which is programmable as an input, output, or tristate
`buffer with TTL compatibility.
`The chip size measures
`9.99 X 9.99 mm.
`
`D. Performance ofArray
`
`The performance of the array was evaluated by measuring
`frequencies of various ring oscillators designed by the basic
`cells. Gate delay time is typically 1.5 us under the conditions
`of fan-out 3 and 3 mm metal interconnect length. The output
`buffer delay is less than 5 as for output load of 1~TTL gate
`and 15 pF capacitance. The sink and source currents are about
`13 mA (V01. = 0.4 V) and 5 mA (V03 = 4.5 V), respectively.
`Fig. 11 shows the typical JOL'VOL characteristics of the Out-
`put buffer. The buffer has high drive capability.
`
`An HO cell is important as well as a basic cell, which deter-
`mines performance and compatibility to the interface.
`In a
`large scale gate array with many HO cells, chip size is highly
`dependent on the U0 cell size. Therefore. in order to minimize
`the U0 cell area, the U0 cell is designed as acne—stage inverter.
`The effective channel length is designed to be 2 pm in order to
`reduce leakage currents. For the input cell, the channel widths
`are 240 and 24 um for n- and p-channel transistors. The basic
`cell is used for interfacing the U0 cell and the array.
`
`V. 32 X 32 BIT MULTIPLIER
`
`A. Configuration ofMulrr'ptier
`
`The 20K-gate gate array is applied to a 32 bit parallel multi-
`plier. The utilization of the basic cells is about 65 percent.
`Fig. 12 shows the block diagram of the multiplier. This con-
`figuration is an array type. Fig. 13 shows the logic diagram of
`the basic multiplier cell. All partial products are generated
`simultaneously, and the product is obtained by adding these
`
`0004
`
`0004
`
`

`

`582
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 8018, NO. 5. OCTOBER 1983
`
`
`
`10L
`
`[mm
`
`Fig. 11. Characteristics of output buffer.
`
`A15
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`Fig. 14. Configuration of 31 bit wide CLA.
`
`CLKX
`
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`
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`
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`
`Fig. 15. Logic diagram of 8 bit CLA l.
`
`delay. Fig. 14 shows the configuration of the 8 bits x 4 type
`CLA. The 31 bit wide CLA is divided into four blocks. Fig.
`15 shows the logic diagram of the 8 bit CLA.
`In this case, we
`choose NAND instead of NOR gates for CMOS circuits. The
`number of input signals to the NAND gate is limited to eight.
`
`C. Design ofMultiplier
`
`The multiplier has been designed in three steps. The first is
`choice of the multiplier type mentioned above. The second
`is the logic design of the multiplier. The third is the layout
`and pattern design.
`For logical verification of the multiplier, a logic simulation
`has been performed.
`In order to save CPU time and memory
`requirements, a basic multiplier cell is defined as a functional
`description in the simulation. By using this technique, the
`number of gates for the logic simulation is reduced to 4K
`gates.
`Fig. 16 shows a part of the simulation result. Before
`the layout, macrocells and super macrocells are prepared.
`
`r... _LSF' our
`'
`Fig. 12. Block diagram of 32 X 32 bit parallel multiplier.
`
`
`
`Fig. 13. Logic diagram of basic multiplier cell.
`
`partial products. The TCX signal selects the signed or unsigned
`multiplication, and the RND signal selects the output rounding
`mode or nonrounding mode. The format of the multiplied
`output is controlled by the FORMAT SELECT signal.
`
`3. Carri} Look Ahead Adder
`
`In an array-typo multiplier, large propagation delay time of
`the carry signal tends to limit performance of the multiplier.
`For achieving fast operational speed, a carry look ahead adder
`(CLA) circuit is employed for addition of upper 31 bits. The
`31 bit wide CLA is divided into blocks to minimize carry path
`delag.r under the limitation of fanout number in actual MOS
`circuits. Compared to 4 bits X 8 organization, 8 bits X 4 type
`needs more basic cells, but it offers much shorter carry path
`
`0005
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`Fig. 1?. Wiring length distribution in CLA circuits.
`
`Fig. 20. Power dissipation characteristics of multiplier.
`
`Every macrocell is designed manually and checked by using a
`circuit extraction program, EMAP [10] , and a logic simulator,
`MACLOS [l l] . The super macroccll is constructed by several
`The
`macrocells.
`The CLA is one of the super macroeells.
`CLA is laid out interactively. Fig. 17 shows the wiring length
`distribution of the CLA circuits.
`The multiplier has been
`designed manually by using macrocells and supermacrocells.
`The total design effort of the multiplier is ten man months.
`Fig. 18 shows a microphotograph of the 32 bit parallel multi-
`plier fabricated as a test vehicle.
`
`D. Performnce of32 X 32 Bit Multiplier
`
`The typical multiplying time is a 120 ns delay from clock
`input to data output, as shown in Fig. 19. Fig. 20 shows the
`power dissipation against the input clock rate. Power dissipa-
`tion is 400 mW at 5 MHz.
`It indicates that this device can
`
`Operate without any special cooling efforts.
`V1. CONCLUSION
`
`A 2 pm ZOK-gate CMOS gate array has been designed and
`fabricated based on a newly developed triple level metallization
`
`0006
`
`0006
`
`

`

`584
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SCI-18, N0. 5, OCTOBER 1933
`
`technology by combining the low-temperature planarization
`technique and the hole edge rounding techniques.
`The features of the gate array are high density (20 010 gates,
`900 transistors per square mm], high speed (1.5 nsl'stage typi-
`cal propagation delay time), and efficient and flexible Ir’O
`capability (180 UO’s are programmable as an input, output, or
`tristate buffer).
`A 32 X 32 bit parallel multiplier has been designed on the
`gate array, and its high performance has been successfully
`demonstrated.
`
`
`
`Haruyuki Tago was born in Tokyo, Japan. on
`October 8. 1952. He received the 13.8. and
`MS. degrees in instrumentation engineering
`from Keio University, Tokyo, Japan, in 1975
`and 197?, respectively.
`In 1977 he joined the Semiconductor Division
`of the Tokyo Shibaura Electric Corporation.
`Kanagawa‘, Japan. He is currently working on
`CMOS gate arrays in the Toshiba R and [1
`Center, Toshiba Corporation, Kanagawa, J span.
`Mr. Tago is a member of the Japan Society
`of Instrument and Control Engineers and the Institute of Electronics
`and. Communication Engineers of Japan.
`
`ACKNOWLEDGMENT
`
`The authors would like to thank S. Yamamoto,M. Kashiwagi,
`S. Mirnura, and H. Hara for their continuous encouragement
`throughout
`this work and also Y. Hazuki, T. Takada, Y.
`Ushiku, and many others for their discussions and contribu-
`tions during the course of this work.
`
`Rerenences
`
`[1] 0. Mir-taro, T. Masuhara, T. Sasaki, Y. Sakai, T. Hayashi, K.
`Nagasawa, K. Nishimura, and T. Yasui, “A HI-CMOSII 8K X 81:
`static RAM,” inDr'g. Tech. Papers,fSSCC. Feb. 1982, pp. 256-251
`[2] S. Konishi, J. Matsunaga, T. Ohtani,M. Sekine, M.lsobe,T. lizuka,
`Y. Uchida, and S. Kohyama, “A 64Kb CMOS RAM,” in Big.
`Tech. Papers,ISSCC, Feb. 1982, pp. 258459.
`[3] K. Ochii, K. Hashimoto, H. Yasuda, M. Masuda, T. Kondo,
`H. Nozawa, and S. Kohyama, "A 50 low Standby Power 64Kb
`CMOS RAM,” in Dig. Tech. Papers, ISSCC, Feb. 1982, pp.
`261L261.
`[4] T. Kobayashi, H. Tago, M. Kobayashi, T. Moriya, and S. Yama-
`moto, “A fiK-gato CMOS gate array,“ in Dig. Tech. Papers,
`ISSCC, Feb. 1982, pp. 174-175.
`[5] T. Itoh, M. Takechi, M. Fujita, A. Masaki, M. Asano, S. Murata,
`S. Horiguchi, and H. Yoshirnura, "A éflfifl-gate CMOS gate
`array," in Big. Tech. Papers, ISSC'C, Feb. 19132, pp. 176-177.
`[6] Eteetmnr'cs, p. 63, Feb. 1932.
`[‘l']
`J. W. Tomkins and S. Hollock, “The impact of multi-ievel metal-
`lizatiori on semicustom LSl," in Proc. CICC, May 1982, pp.
`276—280.
`[8] Y. Hazuki, T. Moriya. and M. Kashiwagi, “A new application of
`R115. to planarization and edge rounding of Si02 hole in the A1
`multilevel interconnection,” in Dig. Tech. Papers, VLSJ Sympt,
`Sept. 1982, pp. 18-19.
`[9] T. Moriya, Y. Hazuki, S. Shima, M. Chiba, and M. Kashiwagi,
`“Aluminum two-level interconnection for VLSI," in Dig. Tech.
`Papers, ECS, May 1982.
`[10] T. Mitsuhashi, T. Chiba, M. Takashima, and K. Yoshida, “An
`integrated mask artwork analysis system,” in Proc.
`.l 7th DAC,
`June 1980, pp. 277—284.
`[11] M. Kawamura and K. Hirabayashi, “Logical verification 03“ L31
`mask artwork by mixed level simulation,“ in Proc. JSCAS, May
`1982, pp. 1021—1024.
`
`
`
`Masazumi Shieehi was born in Hokkaido,
`Japan, on July 5, 1958. He received the 3.5.
`degree in electrical engineering from the Muroran
`institute of Technology, Muroran, Japan,
`in
`1981.
`In 1981, he joined the Toshiba R. and D
`Center, Toshiba Corporation, Kanagawa, Japan.
`He is currently working on CMOS gate arrays.
`
`Tamotsu Hiwatashi was born in Fukuoka,
`Japan, on May 3, 1954. He received the M.S._
`degree in mathematics from the University of
`Hokkaido, Hokkaido, Japan. in 1982.
`In 1982 he joined the Toshiba R and D
`Center, Toshiba Corporation. Kanagawa, J apa'n.
`He is currently working on the CAD system of
`LSl.
`Mr. Hiwatashi is a member of the Mathemati-
`cal Society of Japan.
`
`Kiyoshi Niwa was born in Nagoya, Japan, in
`1951'. He received the 13.5. degree in nuclear
`engineering from the University of Nagoya,
`Nagoya. Japan,
`in 1980, and the 1.1.5. degree
`in nuclear engineering from the University of
`Tokyo. Tokyo, Japan, in 1982.
`In 1982 he joined the Toshiba R and D
`Center. Toshiba Corporation. Kanagawa. Japan.
`He is currently working on CMOS gate arrays.
`
`
`
`in
`Shoitei Shima was born in Nagoya, Japan,
`1950. He received the 13.3. degree in instrw
`mentation engineering from the Nagoya Institute
`of Technology, Nagoya, Japan,
`in 19'32, and
`the MS. degree in applied physics from the
`University of Nagoya, Nagoya,
`Japan,
`in
`1974.
`In 1974 he joined the Toshiba R and D
`Center, Toshiba Corporation, Kanagswa, Japan.
`He is currently working on LSl processes for
`multilevel interconnection.
`Mr. Shit-ha is a member of the Japan Society of Applied Physics.
`
`
`
`ration, Kanagawa, Japan.
`
`Takashi Saigo was born in Shizuoka, Japan, on
`October 26, 1952. He received the 13.8. and
`MS. degrees in electrical engineering from the
`University of Nagoya, Nagoya, Japan, in 1976
`and 1978, respectively.
`In 1978, hejoined the Semiconductor Division
`of the Toshiba Corporation, Kanagawa, Japan.
`He is currently working on CMOS gate arrays
`in the Toshiba R and I) Center, Toshiba Corpow
`
`
`
`Takalliko Mariya was born in Okayama, Japan,
`on November 4, 1942.
`In 1961 he joined the Toshiba R and D
`Center, Toshiba Corporation, Kanagawa, Japan,
`where he was involved in research of semicon-
`ductor physics. He has been involved in the
`research and development of LS] processes
`since 1967. He is currently working on L3!
`processes for multilevel interconnection.
`Mr. Moriya is a member of the Japan Society
`of Applied Physics.
`
`0007
`
`0007
`
`